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AMDGPU: Release the scavenged offset register during VGPR spill
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Authored by nhaehnle on Jan 25 2016, 1:44 PM.

Details

Summary

This fixes a crash where subsequent spills would be unable to scavenge
a register. In particular, it fixes a crash in piglit's
spec@glsl-1.50@execution@geometry@max-input-components (the test still
has a shader that fails to compile because of too many SGPR spills, but
at least it doesn't crash any more).

This is a candidate for the release branch.

Diff Detail

Repository
rL LLVM

Event Timeline

nhaehnle updated this revision to Diff 45911.Jan 25 2016, 1:44 PM
nhaehnle retitled this revision from to AMDGPU: Release the scavenged offset register during VGPR spill.
nhaehnle updated this object.
nhaehnle added reviewers: arsenm, tstellarAMD.
arsenm accepted this revision.Jan 25 2016, 1:47 PM
arsenm edited edge metadata.

LGTM with the minor test adjustments

test/CodeGen/AMDGPU/spill-scavenge-offset.ll
1 ↗(On Diff #45911)

You don't need the -mcpu here. Also this should be run with -verify-machineinstrs, and there should be a second VI run line.

This revision is now accepted and ready to land.Jan 25 2016, 1:47 PM
This revision was automatically updated to reflect the committed changes.