AMDGPU: Rename some r600 intrinsics to use correct TargetPrefix

[arsenm]

Summary

These ones aren't directly emitted by mesa and inserted by a pass.

[• tstellarAMD]

LGTM.

[arsenm]

r258523

lib/Target/AMDGPU/R600ISelLowering.cpp

case AMDGPUIntrinsic::R600_interp_zw: {
             RegisterJNode, RegisterINode);
       else
         interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
             MVT::f32, MVT::f32, DAG.getTargetConstant(slot, DL, MVT::i32),
             RegisterJNode, RegisterINode);
       return DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2f32,
           SDValue(interp, 0), SDValue(interp, 1));
     }
-    case AMDGPUIntrinsic::R600_tex:
-    case AMDGPUIntrinsic::R600_texc:
-    case AMDGPUIntrinsic::R600_txl:
-    case AMDGPUIntrinsic::R600_txlc:
-    case AMDGPUIntrinsic::R600_txb:
-    case AMDGPUIntrinsic::R600_txbc:
-    case AMDGPUIntrinsic::R600_txf:
-    case AMDGPUIntrinsic::R600_txq:
-    case AMDGPUIntrinsic::R600_ddx:
-    case AMDGPUIntrinsic::R600_ddy:
+    case AMDGPUIntrinsic::r600_tex:
+    case AMDGPUIntrinsic::r600_texc:
+    case AMDGPUIntrinsic::r600_txl:
+    case AMDGPUIntrinsic::r600_txlc:
+    case AMDGPUIntrinsic::r600_txb:
+    case AMDGPUIntrinsic::r600_txbc:
+    case AMDGPUIntrinsic::r600_txf:
+    case AMDGPUIntrinsic::r600_txq:
+    case AMDGPUIntrinsic::r600_ddx:
+    case AMDGPUIntrinsic::r600_ddy:
     case AMDGPUIntrinsic::R600_ldptr: {
       unsigned TextureOp;
       switch (IntrinsicID) {
-      case AMDGPUIntrinsic::R600_tex:
+      case AMDGPUIntrinsic::r600_tex:
         TextureOp = 0;
         break;
-      case AMDGPUIntrinsic::R600_texc:
+      case AMDGPUIntrinsic::r600_texc:
         TextureOp = 1;
         break;
-      case AMDGPUIntrinsic::R600_txl:
+      case AMDGPUIntrinsic::r600_txl:
         TextureOp = 2;
         break;
-      case AMDGPUIntrinsic::R600_txlc:
+      case AMDGPUIntrinsic::r600_txlc:
         TextureOp = 3;
         break;
-      case AMDGPUIntrinsic::R600_txb:
+      case AMDGPUIntrinsic::r600_txb:
         TextureOp = 4;
         break;
-      case AMDGPUIntrinsic::R600_txbc:
+      case AMDGPUIntrinsic::r600_txbc:
         TextureOp = 5;
         break;
-      case AMDGPUIntrinsic::R600_txf:
+      case AMDGPUIntrinsic::r600_txf:
         TextureOp = 6;
         break;
-      case AMDGPUIntrinsic::R600_txq:
+      case AMDGPUIntrinsic::r600_txq:
         TextureOp = 7;
         break;
-      case AMDGPUIntrinsic::R600_ddx:
+      case AMDGPUIntrinsic::r600_ddx:
         TextureOp = 8;
         break;
-      case AMDGPUIntrinsic::R600_ddy:
+      case AMDGPUIntrinsic::r600_ddy:
         TextureOp = 9;
         break;
       case AMDGPUIntrinsic::R600_ldptr:
         TextureOp = 10;
         break;
       default:
         llvm_unreachable("Unknow Texture Operation");
       }

lib/Target/AMDGPU/R600Intrinsics.td

 //===-- R600Intrinsics.td - R600 Instrinsic defs -------*- tablegen -*-----===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // R600 Intrinsic Definitions
 //
 //===----------------------------------------------------------------------===//
 
+// FIXME: Should migrate to using TargetPrefix that matches triple arch name.
 let TargetPrefix = "R600", isTarget = 1 in {
   class TextureIntrinsicFloatInput :
     Intrinsic<[llvm_v4f32_ty], [
       llvm_v4f32_ty, // Coord
       llvm_i32_ty, // offset_x
       llvm_i32_ty, // offset_y,
       llvm_i32_ty, // offset_z,
       llvm_i32_ty, // resource_id
Intrinsic<[llvm_v4i32_ty], [
       llvm_i32_ty, // resource_id
       llvm_i32_ty, // samplerid
       llvm_i32_ty, // coord_type_x
       llvm_i32_ty, // coord_type_y
       llvm_i32_ty, // coord_type_z
       llvm_i32_ty // coord_type_w
     ], [IntrNoMem]>;
 
+  def int_R600_ldptr : TextureIntrinsicInt32Input;
+
   def int_R600_interp_const :
     Intrinsic<[llvm_v4f32_ty], [llvm_i32_ty], [IntrNoMem]>;
   def int_R600_interp_xy :
     Intrinsic<[llvm_v2f32_ty], [llvm_i32_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
   def int_R600_interp_zw :
     Intrinsic<[llvm_v2f32_ty], [llvm_i32_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
   def int_R600_load_texbuf :
     Intrinsic<[llvm_v4f32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
-  def int_R600_tex : TextureIntrinsicFloatInput;
-  def int_R600_texc : TextureIntrinsicFloatInput;
-  def int_R600_txl : TextureIntrinsicFloatInput;
-  def int_R600_txlc : TextureIntrinsicFloatInput;
-  def int_R600_txb : TextureIntrinsicFloatInput;
-  def int_R600_txbc : TextureIntrinsicFloatInput;
-  def int_R600_txf : TextureIntrinsicInt32Input;
-  def int_R600_ldptr : TextureIntrinsicInt32Input;
-  def int_R600_txq : TextureIntrinsicInt32Input;
-  def int_R600_ddx : TextureIntrinsicFloatInput;
-  def int_R600_ddy : TextureIntrinsicFloatInput;
   def int_R600_store_swizzle :
     Intrinsic<[], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], []>;
   def int_R600_store_stream_output :
     Intrinsic<[], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
   def int_R600_store_pixel_depth :
       Intrinsic<[], [llvm_float_ty], []>;
   def int_R600_store_pixel_stencil :
       Intrinsic<[], [llvm_float_ty], []>;
   def int_R600_store_dummy :
       Intrinsic<[], [llvm_i32_ty], []>;
+} // End TargetPrefix = "R600", isTarget = 1
+
+let TargetPrefix = "r600", isTarget = 1 in {
+  def int_r600_tex : TextureIntrinsicFloatInput;
+  def int_r600_texc : TextureIntrinsicFloatInput;
+  def int_r600_txl : TextureIntrinsicFloatInput;
+  def int_r600_txlc : TextureIntrinsicFloatInput;
+  def int_r600_txb : TextureIntrinsicFloatInput;
+  def int_r600_txbc : TextureIntrinsicFloatInput;
+  def int_r600_txf : TextureIntrinsicInt32Input;
+  def int_r600_txq : TextureIntrinsicInt32Input;
+  def int_r600_ddx : TextureIntrinsicFloatInput;
+  def int_r600_ddy : TextureIntrinsicFloatInput;
 }

lib/Target/AMDGPU/R600TextureIntrinsicsReplacer.cpp

public:
   }
 
   void visitCallInst(CallInst &I) {
     if (!I.getCalledFunction())
       return;
 
     StringRef Name = I.getCalledFunction()->getName();
     if (Name == "llvm.AMDGPU.tex") {
-      ReplaceTexIntrinsic(I, false, TexSign, "llvm.R600.tex", "llvm.R600.texc");
+      ReplaceTexIntrinsic(I, false, TexSign, "llvm.r600.tex", "llvm.r600.texc");
       return;
     }
     if (Name == "llvm.AMDGPU.txl") {
-      ReplaceTexIntrinsic(I, true, TexSign, "llvm.R600.txl", "llvm.R600.txlc");
+      ReplaceTexIntrinsic(I, true, TexSign, "llvm.r600.txl", "llvm.r600.txlc");
       return;
     }
     if (Name == "llvm.AMDGPU.txb") {
-      ReplaceTexIntrinsic(I, true, TexSign, "llvm.R600.txb", "llvm.R600.txbc");
+      ReplaceTexIntrinsic(I, true, TexSign, "llvm.r600.txb", "llvm.r600.txbc");
       return;
     }
     if (Name == "llvm.AMDGPU.txf") {
       ReplaceTXF(I);
       return;
     }
     if (Name == "llvm.AMDGPU.txq") {
-      ReplaceTexIntrinsic(I, false, TexQSign, "llvm.R600.txq", "llvm.R600.txq");
+      ReplaceTexIntrinsic(I, false, TexQSign, "llvm.r600.txq", "llvm.r600.txq");
       return;
     }
     if (Name == "llvm.AMDGPU.ddx") {
-      ReplaceTexIntrinsic(I, false, TexSign, "llvm.R600.ddx", "llvm.R600.ddx");
+      ReplaceTexIntrinsic(I, false, TexSign, "llvm.r600.ddx", "llvm.r600.ddx");
       return;
     }
     if (Name == "llvm.AMDGPU.ddy") {
-      ReplaceTexIntrinsic(I, false, TexSign, "llvm.R600.ddy", "llvm.R600.ddy");
+      ReplaceTexIntrinsic(I, false, TexSign, "llvm.r600.ddy", "llvm.r600.ddy");
       return;
     }
   }
 
 };
 
 char R600TextureIntrinsicsReplacer::ID = 0;
 
 }
 
 FunctionPass *llvm::createR600TextureIntrinsicsReplacer() {
   return new R600TextureIntrinsicsReplacer();
 }

test/CodeGen/AMDGPU/tex-clause-antidep.ll

 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
 
 ;CHECK: TEX
 ;CHECK-NEXT: ALU
 
 define void @test(<4 x float> inreg %reg0) #0 {
   %1 = extractelement <4 x float> %reg0, i32 0
   %2 = extractelement <4 x float> %reg0, i32 1
   %3 = extractelement <4 x float> %reg0, i32 2
   %4 = extractelement <4 x float> %reg0, i32 3
   %5 = insertelement <4 x float> undef, float %1, i32 0
   %6 = insertelement <4 x float> %5, float %2, i32 1
   %7 = insertelement <4 x float> %6, float %3, i32 2
   %8 = insertelement <4 x float> %7, float %4, i32 3
-  %9 = call <4 x float> @llvm.R600.tex(<4 x float> %8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
-  %10 = call <4 x float> @llvm.R600.tex(<4 x float> %8, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
+  %9 = call <4 x float> @llvm.r600.tex(<4 x float> %8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
+  %10 = call <4 x float> @llvm.r600.tex(<4 x float> %8, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
   %11 = fadd <4 x float> %9, %10
   call void @llvm.R600.store.swizzle(<4 x float> %11, i32 0, i32 0)
   ret void
 }
 
-declare <4 x float> @llvm.R600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readnone
+declare <4 x float> @llvm.r600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readnone
 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
 
-attributes #0 = { "ShaderType"="1" }
+attributes #0 = { "ShaderType"="1" }
 

test/CodeGen/AMDGPU/texture-input-merge.ll

define void @test(<4 x float> inreg %reg0) #0 {
   %6 = fmul float %2, 3.0
   %7 = fmul float %3, 3.0
   %8 = fmul float %4, 3.0
   %9 = insertelement <4 x float> undef, float %5, i32 0
   %10 = insertelement <4 x float> %9, float %6, i32 1
   %11 = insertelement <4 x float> undef, float %7, i32 0
   %12 = insertelement <4 x float> %11, float %5, i32 1
   %13 = insertelement <4 x float> undef, float %8, i32 0
-  %14 = call <4 x float> @llvm.R600.tex(<4 x float> %10, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
-  %15 = call <4 x float> @llvm.R600.tex(<4 x float> %12, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
-  %16 = call <4 x float> @llvm.R600.tex(<4 x float> %13, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
+  %14 = call <4 x float> @llvm.r600.tex(<4 x float> %10, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
+  %15 = call <4 x float> @llvm.r600.tex(<4 x float> %12, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
+  %16 = call <4 x float> @llvm.r600.tex(<4 x float> %13, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
   %17 = fadd <4 x float> %14, %15
   %18 = fadd <4 x float> %17, %16
   call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 0)
   ret void
 }
 
-declare <4 x float> @llvm.R600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readnone
+declare <4 x float> @llvm.r600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readnone
 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
 
-attributes #0 = { "ShaderType"="1" }
+attributes #0 = { "ShaderType"="1" }