AMDGPU/SI: Promote i1 SETCC operations

[• tstellarAMD]

Summary

While working on uniform branching, I've hit a few cases where we emit
i1 SETCC operations.

[arsenm]

From the testcase, I don't see why promotion would be necessary here

[• tstellarAMD]

In D16233#328073, @arsenm wrote:

From the testcase, I don't see why promotion would be necessary here

The basic block order is swapped by SelectionDAG, so an i1 xor is inserted before the branch instruction. This is optimized to an i1 setcc instruction by the DAGCombine. This isn't an issue now, because SIISelLowering::LowerBRCOND was folding these into the branch intrinsic, but it will be an issue when we switch to uniform branching.

[arsenm]

In D16233#329609, @tstellarAMD wrote:

In D16233#328073, @arsenm wrote:

From the testcase, I don't see why promotion would be necessary here

The basic block order is swapped by SelectionDAG, so an i1 xor is inserted before the branch instruction. This is optimized to an i1 setcc instruction by the DAGCombine. This isn't an issue now, because SIISelLowering::LowerBRCOND was folding these into the branch intrinsic, but it will be an issue when we switch to uniform branching.

Can you swap the block order and insert the xor here for the same effect so the DAG builder doesn't do this?

[• tstellarAMD]

Put explicit i1 xor in test case.

[arsenm]

LGTM

lib/Target/AMDGPU/SIISelLowering.cpp

SITargetLowering::SITargetLowering(TargetMachine &TM,
   setOperationAction(ISD::SELECT, MVT::f64, Promote);
   AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
 
   setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
   setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
   setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
   setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
 
+  setOperationAction(ISD::SETCC, MVT::i1, Promote);
   setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
   setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
 
   setOperationAction(ISD::BSWAP, MVT::i32, Legal);
   setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
 
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Legal);
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);

test/CodeGen/AMDGPU/setcc.ll

define void @setcc-i1(i32 %in) {
   %and = and i32 %in, 1
   %cmp = icmp eq i32 %and, 0
   br i1 %cmp, label %endif, label %if
 if:
   unreachable
 endif:
   ret void
 }
+
+; FUNC-LABEL: setcc-i1-and
+; SI-DAG: v_cmp_le_f32_e64 [[A:s\[[0-9]+:[0-9]+\]]], 0, s{{[0-9]+}}
+; SI-DAG: v_cmp_ge_f32_e64 [[B:s\[[0-9]+:[0-9]+\]]], 1.0, s{{[0-9]+}}
+; SI: s_and_b64 s[2:3], [[A]], [[B]]
+define void @setcc-i1-and(i32 addrspace(1)* %out, float %cond) #0 {
+bb0:
+  %tmp5 = fcmp oge float %cond, 0.000000e+00
+  %tmp7 = fcmp ole float %cond, 1.000000e+00
+  %tmp9 = and i1 %tmp5, %tmp7
+  br i1 %tmp9, label %bb1, label %bb2
+
+bb1:
+  store i32 0, i32 addrspace(1)* %out
+  br label %bb2
+
+bb2:
+  ret void
+}