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Differential D156862

[InstCombine] Test cases for D156811
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Authored by antoniofrighetto on Aug 2 2023, 1:16 AM.

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Reviewers
goldstein.w.n
nikic
Commits
rGf5cb6265eaf8: [InstCombine] Introduce tests for D156811

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antoniofrighetto created this revision.Aug 2 2023, 1:16 AM
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antoniofrighetto requested review of this revision.Aug 2 2023, 1:16 AM
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antoniofrighetto added a child revision: D156811: [InstCombine] Fold `select` of `srem` and conditional add.Aug 2 2023, 1:16 AM
Harbormaster completed remote builds in B249695: Diff 546349.Aug 2 2023, 2:34 AM
antoniofrighetto updated this revision to Diff 546749.Aug 3 2023, 1:50 AM
Harbormaster completed remote builds in B249986: Diff 546749.Aug 3 2023, 3:45 AM
This revision was not accepted when it landed; it landed in state Needs Review.Aug 7 2023, 5:04 PM
Closed by commit rGf5cb6265eaf8: [InstCombine] Introduce tests for D156811 (authored by antoniofrighetto). · Explain Why
This revision was automatically updated to reflect the committed changes.
antoniofrighetto added a commit: rGf5cb6265eaf8: [InstCombine] Introduce tests for D156811.

Revision Contents

PathSize
llvm/
test/
Transforms/
InstCombine/
122 lines

Diff 547997

llvm/test/Transforms/InstCombine/select-divrem.ll

Show First 20 Lines • Show All 207 Lines • ▼ Show 20 Lines
; CHECK-NEXT: [[SEL:%.*]] = urem i5 [[X:%.*]], [[SEL_V]] ; CHECK-NEXT: [[SEL:%.*]] = urem i5 [[X:%.*]], [[SEL_V]]
; CHECK-NEXT: ret i5 [[SEL]] ; CHECK-NEXT: ret i5 [[SEL]]
; ;
%r1 = urem i5 %x, %y %r1 = urem i5 %x, %y
%r2 = urem i5 %x, %z %r2 = urem i5 %x, %z
%sel = select i1 %b, i5 %r2, i5 %r1 %sel = select i1 %b, i5 %r2, i5 %r1
ret i5 %sel ret i5 %sel
} }
define i32 @rem_euclid_1(i32 %0) {
; CHECK-LABEL: @rem_euclid_1(
; CHECK-NEXT: [[REM:%.*]] = srem i32 [[TMP0:%.*]], 8
; CHECK-NEXT: [[COND:%.*]] = icmp slt i32 [[REM]], 0
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[REM]], 8
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND]], i32 [[ADD]], i32 [[REM]]
; CHECK-NEXT: ret i32 [[SEL]]
;
%rem = srem i32 %0, 8
%cond = icmp slt i32 %rem, 0
%add = add i32 %rem, 8
%sel = select i1 %cond, i32 %add, i32 %rem
ret i32 %sel
}
define i32 @rem_euclid_2(i32 %0) {
; CHECK-LABEL: @rem_euclid_2(
; CHECK-NEXT: [[REM:%.*]] = srem i32 [[TMP0:%.*]], 8
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[REM]], 8
; CHECK-NEXT: [[COND1:%.*]] = icmp slt i32 [[REM]], 0
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND1]], i32 [[ADD]], i32 [[REM]]
; CHECK-NEXT: ret i32 [[SEL]]
;
%rem = srem i32 %0, 8
%cond = icmp sgt i32 %rem, -1
%add = add i32 %rem, 8
%sel = select i1 %cond, i32 %rem, i32 %add
ret i32 %sel
}
define i32 @rem_euclid_wrong_sign_test(i32 %0) {
; CHECK-LABEL: @rem_euclid_wrong_sign_test(
; CHECK-NEXT: [[REM:%.*]] = srem i32 [[TMP0:%.*]], 8
; CHECK-NEXT: [[COND:%.*]] = icmp sgt i32 [[REM]], 0
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[REM]], 8
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND]], i32 [[ADD]], i32 [[REM]]
; CHECK-NEXT: ret i32 [[SEL]]
;
%rem = srem i32 %0, 8
%cond = icmp sgt i32 %rem, 0
%add = add i32 %rem, 8
%sel = select i1 %cond, i32 %add, i32 %rem
ret i32 %sel
}
define i32 @rem_euclid_add_different_const(i32 %0) {
; CHECK-LABEL: @rem_euclid_add_different_const(
; CHECK-NEXT: [[REM:%.*]] = srem i32 [[TMP0:%.*]], 8
; CHECK-NEXT: [[COND:%.*]] = icmp slt i32 [[REM]], 0
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[REM]], 9
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND]], i32 [[ADD]], i32 [[REM]]
; CHECK-NEXT: ret i32 [[SEL]]
;
%rem = srem i32 %0, 8
%cond = icmp slt i32 %rem, 0
%add = add i32 %rem, 9
%sel = select i1 %cond, i32 %add, i32 %rem
ret i32 %sel
}
define i32 @rem_euclid_wrong_operands_select(i32 %0) {
; CHECK-LABEL: @rem_euclid_wrong_operands_select(
; CHECK-NEXT: [[REM:%.*]] = srem i32 [[TMP0:%.*]], 8
; CHECK-NEXT: [[COND:%.*]] = icmp slt i32 [[REM]], 0
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[REM]], 8
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND]], i32 [[REM]], i32 [[ADD]]
; CHECK-NEXT: ret i32 [[SEL]]
;
%rem = srem i32 %0, 8
%cond = icmp slt i32 %rem, 0
%add = add i32 %rem, 8
%sel = select i1 %cond, i32 %rem, i32 %add
ret i32 %sel
}
define <2 x i32> @rem_euclid_vec(<2 x i32> %0) {
; CHECK-LABEL: @rem_euclid_vec(
; CHECK-NEXT: [[REM:%.*]] = srem <2 x i32> [[TMP0:%.*]], <i32 8, i32 8>
; CHECK-NEXT: [[COND:%.*]] = icmp slt <2 x i32> [[REM]], zeroinitializer
; CHECK-NEXT: [[ADD:%.*]] = add nsw <2 x i32> [[REM]], <i32 8, i32 8>
; CHECK-NEXT: [[SEL:%.*]] = select <2 x i1> [[COND]], <2 x i32> [[ADD]], <2 x i32> [[REM]]
; CHECK-NEXT: ret <2 x i32> [[SEL]]
;
%rem = srem <2 x i32> %0, <i32 8, i32 8>
%cond = icmp slt <2 x i32> %rem, <i32 0, i32 0>
%add = add <2 x i32> %rem, <i32 8, i32 8>
%sel = select <2 x i1> %cond, <2 x i32> %add, <2 x i32> %rem
ret <2 x i32> %sel
}
define i128 @rem_euclid_i128(i128 %0) {
; CHECK-LABEL: @rem_euclid_i128(
; CHECK-NEXT: [[REM:%.*]] = srem i128 [[TMP0:%.*]], 8
; CHECK-NEXT: [[COND:%.*]] = icmp slt i128 [[REM]], 0
; CHECK-NEXT: [[ADD:%.*]] = add nsw i128 [[REM]], 8
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND]], i128 [[ADD]], i128 [[REM]]
; CHECK-NEXT: ret i128 [[SEL]]
;
%rem = srem i128 %0, 8
%cond = icmp slt i128 %rem, 0
%add = add i128 %rem, 8
%sel = select i1 %cond, i128 %add, i128 %rem
ret i128 %sel
}
define i8 @rem_euclid_non_const_pow2(i8 %0, i8 %1) {
; CHECK-LABEL: @rem_euclid_non_const_pow2(
; CHECK-NEXT: [[POW2:%.*]] = shl nuw i8 1, [[TMP0:%.*]]
; CHECK-NEXT: [[REM:%.*]] = srem i8 [[TMP1:%.*]], [[POW2]]
; CHECK-NEXT: [[COND:%.*]] = icmp slt i8 [[REM]], 0
; CHECK-NEXT: [[ADD:%.*]] = select i1 [[COND]], i8 [[POW2]], i8 0
; CHECK-NEXT: [[SEL:%.*]] = add i8 [[REM]], [[ADD]]
; CHECK-NEXT: ret i8 [[SEL]]
;
%pow2 = shl i8 1, %0
%rem = srem i8 %1, %pow2
%cond = icmp slt i8 %rem, 0
%add = add i8 %rem, %pow2
%sel = select i1 %cond, i8 %add, i8 %rem
ret i8 %sel
}