[LoongArch] Optimize conditional selection of integer

[hev]

Summary

This patch optimizes code generation by leveraging the zeroing behavior of the maskeqz/masknez instructions.

int sel(int a, int b)
{
    return (a < b) ? a : 0;
}

slt	$a1,$a0,$a1
masknez	$a2,$r0,$a1
maskeqz	$a0,$a0,$a1
or	$a0,$a0,$a2

>

slt	$a1,$a0,$a1
maskeqz	$a0,$a0,$a1

[xry111]

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

1202

Can we just write

def : Pat<(select GPR:$cond, GPR:$t, 0), (MASKEQZ GPR:$t, GPR:$cond)>;

here? I see RISC-V uses an untyped 0 in similar select patterns.

[hev]

1. Update to use untyped immediate operand in select patterns.
2. Add test cases.

[hev]

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

1202

Yeap, thanks.

[SixWeining]

Thanks for the improvement.

[SixWeining]

Sorry, I forgot to amend the author name and email when merging this patch. I will revert and re-commit later.

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

 } // Predicates = [IsLA64]
 def : Pat<(setugt GPR:$rj, GPR:$rk), (SLTU GPR:$rk, GPR:$rj)>;
 def : Pat<(setuge GPR:$rj, GPR:$rk), (XORI (SLTU GPR:$rj, GPR:$rk), 1)>;
 def : Pat<(setule GPR:$rj, GPR:$rk), (XORI (SLTU GPR:$rk, GPR:$rj), 1)>;
 def : Pat<(setgt GPR:$rj, GPR:$rk), (SLT GPR:$rk, GPR:$rj)>;
 def : Pat<(setge GPR:$rj, GPR:$rk), (XORI (SLT GPR:$rj, GPR:$rk), 1)>;
 def : Pat<(setle GPR:$rj, GPR:$rk), (XORI (SLT GPR:$rk, GPR:$rj), 1)>;
 
 /// Select
 
+def : Pat<(select GPR:$cond, GPR:$t, 0), (MASKEQZ GPR:$t, GPR:$cond)>;
+def : Pat<(select GPR:$cond, 0, GPR:$f), (MASKNEZ GPR:$f, GPR:$cond)>;
 def : Pat<(select GPR:$cond, GPR:$t, GPR:$f),
           (OR (MASKEQZ GPR:$t, GPR:$cond), (MASKNEZ GPR:$f, GPR:$cond))>;
 
 /// Branches and jumps
 
 class BccPat<PatFrag CondOp, LAInst Inst>
     : Pat<(brcond (GRLenVT (CondOp GPR:$rj, GPR:$rd)), bb:$imm16),
           (Inst GPR:$rj, GPR:$rd, bb:$imm16)>;

llvm/test/CodeGen/LoongArch/atomicrmw-uinc-udec-wrap.ll

 ; LA64-NEXT:    # =>This Loop Header: Depth=1
 ; LA64-NEXT:    # Child Loop BB0_3 Depth 2
 ; LA64-NEXT:    srl.w $a5, $a3, $a0
 ; LA64-NEXT:    andi $a6, $a5, 255
 ; LA64-NEXT:    sltu $a6, $a6, $a1
 ; LA64-NEXT:    addi.d $a5, $a5, 1
 ; LA64-NEXT:    xori $a6, $a6, 1
 ; LA64-NEXT:    masknez $a5, $a5, $a6
-; LA64-NEXT:    maskeqz $a6, $zero, $a6
-; LA64-NEXT:    or $a5, $a6, $a5
 ; LA64-NEXT:    andi $a5, $a5, 255
 ; LA64-NEXT:    sll.w $a5, $a5, $a0
 ; LA64-NEXT:    and $a6, $a3, $a4
 ; LA64-NEXT:    or $a6, $a6, $a5
 ; LA64-NEXT:  .LBB0_3: # %atomicrmw.start
 ; LA64-NEXT:    # Parent Loop BB0_1 Depth=1
 ; LA64-NEXT:    # => This Inner Loop Header: Depth=2
 ; LA64-NEXT:    ll.w $a5, $a2, 0

 ; LA64-NEXT:    # =>This Loop Header: Depth=1
 ; LA64-NEXT:    # Child Loop BB1_3 Depth 2
 ; LA64-NEXT:    srl.w $a5, $a3, $a0
 ; LA64-NEXT:    bstrpick.d $a6, $a5, 15, 0
 ; LA64-NEXT:    sltu $a6, $a6, $a1
 ; LA64-NEXT:    addi.d $a5, $a5, 1
 ; LA64-NEXT:    xori $a6, $a6, 1
 ; LA64-NEXT:    masknez $a5, $a5, $a6
-; LA64-NEXT:    maskeqz $a6, $zero, $a6
-; LA64-NEXT:    or $a5, $a6, $a5
 ; LA64-NEXT:    bstrpick.d $a5, $a5, 15, 0
 ; LA64-NEXT:    sll.w $a5, $a5, $a0
 ; LA64-NEXT:    and $a6, $a3, $a4
 ; LA64-NEXT:    or $a6, $a6, $a5
 ; LA64-NEXT:  .LBB1_3: # %atomicrmw.start
 ; LA64-NEXT:    # Parent Loop BB1_1 Depth=1
 ; LA64-NEXT:    # => This Inner Loop Header: Depth=2
 ; LA64-NEXT:    ll.w $a5, $a2, 0

 ; LA64-NEXT:  .LBB2_1: # %atomicrmw.start
 ; LA64-NEXT:    # =>This Loop Header: Depth=1
 ; LA64-NEXT:    # Child Loop BB2_3 Depth 2
 ; LA64-NEXT:    bstrpick.d $a1, $a3, 31, 0
 ; LA64-NEXT:    sltu $a1, $a1, $a2
 ; LA64-NEXT:    xori $a1, $a1, 1
 ; LA64-NEXT:    addi.d $a4, $a3, 1
 ; LA64-NEXT:    masknez $a4, $a4, $a1
-; LA64-NEXT:    maskeqz $a1, $zero, $a1
-; LA64-NEXT:    or $a4, $a1, $a4
 ; LA64-NEXT:  .LBB2_3: # %atomicrmw.start
 ; LA64-NEXT:    # Parent Loop BB2_1 Depth=1
 ; LA64-NEXT:    # => This Inner Loop Header: Depth=2
 ; LA64-NEXT:    ll.w $a1, $a0, 0
 ; LA64-NEXT:    bne $a1, $a3, .LBB2_5
 ; LA64-NEXT:  # %bb.4: # %atomicrmw.start
 ; LA64-NEXT:    # in Loop: Header=BB2_3 Depth=2
 ; LA64-NEXT:    dbar 0

 ; LA64-NEXT:  .LBB3_1: # %atomicrmw.start
 ; LA64-NEXT:    # =>This Loop Header: Depth=1
 ; LA64-NEXT:    # Child Loop BB3_3 Depth 2
 ; LA64-NEXT:    move $a3, $a2
 ; LA64-NEXT:    sltu $a2, $a2, $a1
 ; LA64-NEXT:    xori $a2, $a2, 1
 ; LA64-NEXT:    addi.d $a4, $a3, 1
 ; LA64-NEXT:    masknez $a4, $a4, $a2
-; LA64-NEXT:    maskeqz $a2, $zero, $a2
-; LA64-NEXT:    or $a4, $a2, $a4
 ; LA64-NEXT:  .LBB3_3: # %atomicrmw.start
 ; LA64-NEXT:    # Parent Loop BB3_1 Depth=1
 ; LA64-NEXT:    # => This Inner Loop Header: Depth=2
 ; LA64-NEXT:    ll.d $a2, $a0, 0
 ; LA64-NEXT:    bne $a2, $a3, .LBB3_5
 ; LA64-NEXT:  # %bb.4: # %atomicrmw.start
 ; LA64-NEXT:    # in Loop: Header=BB3_3 Depth=2
 ; LA64-NEXT:    dbar 0

llvm/test/CodeGen/LoongArch/ir-instruction/select-bare-int.ll

 ; LA64-NEXT:    andi $a0, $a0, 1
 ; LA64-NEXT:    masknez $a2, $a2, $a0
 ; LA64-NEXT:    maskeqz $a0, $a1, $a0
 ; LA64-NEXT:    or $a0, $a0, $a2
 ; LA64-NEXT:    ret
   %res = select i1 %a, i64 %b, i64 %c
   ret i64 %res
 }
+
+define i16 @bare_select_zero_i16(i1 %a, i16 %b) {
+; LA32-LABEL: bare_select_zero_i16:
+; LA32:       # %bb.0:
+; LA32-NEXT:    andi $a0, $a0, 1
+; LA32-NEXT:    masknez $a0, $a1, $a0
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: bare_select_zero_i16:
+; LA64:       # %bb.0:
+; LA64-NEXT:    andi $a0, $a0, 1
+; LA64-NEXT:    masknez $a0, $a1, $a0
+; LA64-NEXT:    ret
+  %res = select i1 %a, i16 0, i16 %b
+  ret i16 %res
+}
+
+define i32 @bare_select_zero_i32(i1 %a, i32 %b) {
+; LA32-LABEL: bare_select_zero_i32:
+; LA32:       # %bb.0:
+; LA32-NEXT:    andi $a0, $a0, 1
+; LA32-NEXT:    maskeqz $a0, $a1, $a0
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: bare_select_zero_i32:
+; LA64:       # %bb.0:
+; LA64-NEXT:    andi $a0, $a0, 1
+; LA64-NEXT:    maskeqz $a0, $a1, $a0
+; LA64-NEXT:    ret
+  %res = select i1 %a, i32 %b, i32 0
+  ret i32 %res
+}