[DAG] Calculate the number of sign bits for constant BUILD_VECTOR directly.

[dmgreen]

Summary

For constant BUILD_VECTORs the operands need to be legal types. This can mean that when the number of sign bits is calculated it may look that the entire constant and inefficiently produce less sign bits than it could. For example i8 vectors could use i32 elements, for which 0x000000ff would be incorrectly limited to 1 sign bit as the original value has 24 sign bits. This makes it look at the constant directly, truncated to the correct type for the element so that it can correctly return 8.

[RKSimon]

Makes sense - we could go further and use ComputeKnownBits on the element whenever there is implicit truncation and chose between it and the ComputeNumSignBits call - but this is probably good enough in most cases.

[dmgreen]

Thanks

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
   case ISD::BUILD_VECTOR:
     assert(!VT.isScalableVector());
     Tmp = VTBits;
     for (unsigned i = 0, e = Op.getNumOperands(); (i < e) && (Tmp > 1); ++i) {
       if (!DemandedElts[i])
         continue;
 
       SDValue SrcOp = Op.getOperand(i);
+      // BUILD_VECTOR can implicitly truncate sources, we handle this specially
+      // for constant nodes to ensure we only look at the sign bits.
+      if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SrcOp)) {
+        APInt T = C->getAPIntValue().trunc(VTBits);
+        Tmp2 = T.getNumSignBits();
+      } else {
         Tmp2 = ComputeNumSignBits(SrcOp, Depth + 1);
 
-      // BUILD_VECTOR can implicitly truncate sources, we must handle this.
         if (SrcOp.getValueSizeInBits() != VTBits) {
           assert(SrcOp.getValueSizeInBits() > VTBits &&
                  "Expected BUILD_VECTOR implicit truncation");
           unsigned ExtraBits = SrcOp.getValueSizeInBits() - VTBits;
           Tmp2 = (Tmp2 > ExtraBits ? Tmp2 - ExtraBits : 1);
         }
+      }
       Tmp = std::min(Tmp, Tmp2);
     }
     return Tmp;
 
   case ISD::VECTOR_SHUFFLE: {
     // Collect the minimum number of sign bits that are shared by every vector
     // element referenced by the shuffle.
     APInt DemandedLHS, DemandedRHS;

llvm/test/CodeGen/AArch64/dag-combine-setcc.ll

 
 define i1 @combine_setcc_ne_vecreduce_and_v32i1(<32 x i8> %a) {
 ; CHECK-LABEL: combine_setcc_ne_vecreduce_and_v32i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmtst v0.16b, v0.16b, v0.16b
 ; CHECK-NEXT:    mov w8, #1 // =0x1
 ; CHECK-NEXT:    cmeq v1.16b, v1.16b, #0
 ; CHECK-NEXT:    bic v0.16b, v0.16b, v1.16b
-; CHECK-NEXT:    shl v0.16b, v0.16b, #7
-; CHECK-NEXT:    cmlt v0.16b, v0.16b, #0
 ; CHECK-NEXT:    uminv b0, v0.16b
 ; CHECK-NEXT:    fmov w9, s0
 ; CHECK-NEXT:    bic w0, w8, w9
 ; CHECK-NEXT:    ret
   %cmp1 = icmp ne <32 x i8> %a, zeroinitializer
   %cast = bitcast <32 x i1> %cmp1 to i32
   %cmp2 = icmp ne i32 %cast, -1
   ret i1 %cmp2
 }
 
 define i1 @combine_setcc_ne_vecreduce_and_v64i1(<64 x i8> %a) {
 ; CHECK-LABEL: combine_setcc_ne_vecreduce_and_v64i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmtst v1.16b, v1.16b, v1.16b
 ; CHECK-NEXT:    mov w8, #1 // =0x1
 ; CHECK-NEXT:    cmtst v0.16b, v0.16b, v0.16b
 ; CHECK-NEXT:    cmeq v3.16b, v3.16b, #0
 ; CHECK-NEXT:    cmeq v2.16b, v2.16b, #0
 ; CHECK-NEXT:    bic v1.16b, v1.16b, v3.16b
 ; CHECK-NEXT:    bic v0.16b, v0.16b, v2.16b
 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT:    shl v0.16b, v0.16b, #7
-; CHECK-NEXT:    cmlt v0.16b, v0.16b, #0
 ; CHECK-NEXT:    uminv b0, v0.16b
 ; CHECK-NEXT:    fmov w9, s0
 ; CHECK-NEXT:    bic w0, w8, w9
 ; CHECK-NEXT:    ret
   %cmp1 = icmp ne <64 x i8> %a, zeroinitializer
   %cast = bitcast <64 x i1> %cmp1 to i64
   %cmp2 = icmp ne i64 %cast, -1
   ret i1 %cmp2