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Differential D14810

AVX512 : vmovq.s implementation.
ClosedPublic

Authored by igorb on Nov 19 2015, 1:30 AM.

Details

Reviewers
AsafBadouh
delena
Commits
rGe293e83f5dd2: AVX512:Implemented encoding for the vmovq.s instruction.
rL254248: AVX512:Implemented encoding for the vmovq.s instruction.
Summary

AVX512: Implemented encoding for the vmovq.s instruction.

Diff Detail

Repository
rL LLVM

Event Timeline

igorb updated this revision to Diff 40612.Nov 19 2015, 1:30 AM
igorb retitled this revision from to AVX512 : vmovq.s implementation..
igorb updated this object.
igorb added reviewers: delena, AsafBadouh.
igorb set the repository for this revision to rL LLVM.
igorb added a subscriber: llvm-commits.
delena accepted this revision.Nov 28 2015, 11:05 PM
delena edited edge metadata.

LGTM

This revision is now accepted and ready to land.Nov 28 2015, 11:05 PM
Closed by commit rL254248: AVX512:Implemented encoding for the vmovq.s instruction. (authored by ibreger). · Explain WhyNov 28 2015, 11:44 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
X86/
5 lines
test/
MC/
X86/
16 lines

Diff 41342

llvm/trunk/lib/Target/X86/X86InstrAVX512.td

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def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs), def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
(ins i64mem:$dst, VR128X:$src), (ins i64mem:$dst, VR128X:$src),
"vmovq\t{$src, $dst|$dst, $src}", "vmovq\t{$src, $dst|$dst, $src}",
[(store (extractelt (v2i64 VR128X:$src), (iPTR 0)), [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
addr:$dst)], IIC_SSE_MOVDQ>, addr:$dst)], IIC_SSE_MOVDQ>,
EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>, EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>; Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
def VMOV64toPQIZrr_REV : AVX512BI<0xD6, MRMDestReg, (outs VR128X:$dst),
(ins VR128X:$src),
"vmovq.s\t{$src, $dst|$dst, $src}",[]>,
EVEX, VEX_W, VEX_LIG;
// Move Scalar Single to Double Int // Move Scalar Single to Double Int
// //
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
(ins FR32X:$src), (ins FR32X:$src),
"vmovd\t{$src, $dst|$dst, $src}", "vmovd\t{$src, $dst|$dst, $src}",
[(set GR32:$dst, (bitconvert FR32X:$src))], [(set GR32:$dst, (bitconvert FR32X:$src))],
IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG; IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
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llvm/trunk/test/MC/X86/avx512-encodings.s

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// CHECK: vmovups.s %zmm20, %zmm27 {%k6} // CHECK: vmovups.s %zmm20, %zmm27 {%k6}
// CHECK: encoding: [0x62,0x81,0x7c,0x4e,0x11,0xe3] // CHECK: encoding: [0x62,0x81,0x7c,0x4e,0x11,0xe3]
vmovups.s %zmm20, %zmm27 {%k6} vmovups.s %zmm20, %zmm27 {%k6}
// CHECK: vmovups.s %zmm20, %zmm27 {%k6} {z} // CHECK: vmovups.s %zmm20, %zmm27 {%k6} {z}
// CHECK: encoding: [0x62,0x81,0x7c,0xce,0x11,0xe3] // CHECK: encoding: [0x62,0x81,0x7c,0xce,0x11,0xe3]
vmovups.s %zmm20, %zmm27 {%k6} {z} vmovups.s %zmm20, %zmm27 {%k6} {z}
// CHECK: vmovq.s %xmm9, %xmm29
// CHECK: encoding: [0x62,0x11,0xfd,0x08,0xd6,0xcd]
vmovq.s %xmm9, %xmm29
// CHECK: vmovq.s %xmm5, %xmm18
// CHECK: encoding: [0x62,0xb1,0xfd,0x08,0xd6,0xea]
vmovq.s %xmm5, %xmm18
// CHECK: vmovq.s %xmm14, %xmm25
// CHECK: encoding: [0x62,0x11,0xfd,0x08,0xd6,0xf1]
vmovq.s %xmm14, %xmm25
// CHECK: vmovq.s %xmm24, %xmm12
// CHECK: encoding: [0x62,0x41,0xfd,0x08,0xd6,0xc4]
vmovq.s %xmm24, %xmm12