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Differential D14766

AVX512 : vpextrw.s implementation.
ClosedPublic

Authored by igorb on Nov 17 2015, 11:47 PM.

Details

Reviewers
AsafBadouh
delena
Commits
rG5574730454e8: AVX512: Implemented encoding for vpextrw.s instruction.
rL253447: AVX512: Implemented encoding for vpextrw.s instruction.
Summary

AVX512: Implemented encoding for vpextrw.s instructions.

Diff Detail

Repository
rL LLVM

Event Timeline

igorb updated this revision to Diff 40475.Nov 17 2015, 11:47 PM
igorb retitled this revision from to AVX512 : vpextrw.s implementation..
igorb updated this object.
igorb added reviewers: delena, AsafBadouh.
igorb set the repository for this revision to rL LLVM.
igorb added a subscriber: llvm-commits.
delena accepted this revision.Nov 17 2015, 11:52 PM
delena edited edge metadata.

LGTM

This revision is now accepted and ready to land.Nov 17 2015, 11:52 PM
Closed by commit rL253447: AVX512: Implemented encoding for vpextrw.s instruction. (authored by ibreger). · Explain WhyNov 18 2015, 12:49 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
X86/
5 lines
test/
MC/
X86/
48 lines

Diff 40475

lib/Target/X86/X86InstrAVX512.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 7,193 Lines • ▼ Show 20 Linesmulticlass avx512_extract_elt_w<string OpcodeStr, X86VectorVTInfo _> {
let Predicates = [HasBWI] in { let Predicates = [HasBWI] in {
def rr : AVX512Ii8<0xC5, MRMSrcReg, (outs GR32orGR64:$dst), def rr : AVX512Ii8<0xC5, MRMSrcReg, (outs GR32orGR64:$dst),
(ins _.RC:$src1, u8imm:$src2), (ins _.RC:$src1, u8imm:$src2),
OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
[(set GR32orGR64:$dst, [(set GR32orGR64:$dst,
(X86pextrw (_.VT _.RC:$src1), imm:$src2))]>, (X86pextrw (_.VT _.RC:$src1), imm:$src2))]>,
EVEX, PD; EVEX, PD;
def rr_REV : AVX512Ii8<0x15, MRMDestReg, (outs GR32orGR64:$dst),
(ins _.RC:$src1, u8imm:$src2),
OpcodeStr#".s\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
EVEX, TAPD;
defm NAME : avx512_extract_elt_bw_m<0x15, OpcodeStr, X86pextrw, _>, TAPD; defm NAME : avx512_extract_elt_bw_m<0x15, OpcodeStr, X86pextrw, _>, TAPD;
} }
} }
multiclass avx512_extract_elt_dq<string OpcodeStr, X86VectorVTInfo _, multiclass avx512_extract_elt_dq<string OpcodeStr, X86VectorVTInfo _,
RegisterClass GRC> { RegisterClass GRC> {
let Predicates = [HasDQI] in { let Predicates = [HasDQI] in {
def rr : AVX512Ii8<0x16, MRMDestReg, (outs GRC:$dst), def rr : AVX512Ii8<0x16, MRMDestReg, (outs GRC:$dst),
▲ Show 20 Lines • Show All 195 Lines • Show Last 20 Lines

test/MC/X86/x86-64-avx512bw.s

Show First 20 Lines • Show All 4,685 Lines • ▼ Show 20 Lines
// CHECK: vpbroadcastw %eax, %zmm24 {%k1} // CHECK: vpbroadcastw %eax, %zmm24 {%k1}
// CHECK: encoding: [0x62,0x62,0x7d,0x49,0x7b,0xc0] // CHECK: encoding: [0x62,0x62,0x7d,0x49,0x7b,0xc0]
vpbroadcastw %eax, %zmm24 {%k1} vpbroadcastw %eax, %zmm24 {%k1}
// CHECK: vpbroadcastw %eax, %zmm24 {%k1} {z} // CHECK: vpbroadcastw %eax, %zmm24 {%k1} {z}
// CHECK: encoding: [0x62,0x62,0x7d,0xc9,0x7b,0xc0] // CHECK: encoding: [0x62,0x62,0x7d,0xc9,0x7b,0xc0]
vpbroadcastw %eax, %zmm24 {%k1} {z} vpbroadcastw %eax, %zmm24 {%k1} {z}
// CHECK: vpextrw.s $171, %xmm28, %eax
// CHECK: encoding: [0x62,0x63,0x7d,0x08,0x15,0xe0,0xab]
vpextrw.s $0xab, %xmm28, %eax
// CHECK: vpextrw.s $123, %xmm28, %eax
// CHECK: encoding: [0x62,0x63,0x7d,0x08,0x15,0xe0,0x7b]
vpextrw.s $0x7b, %xmm28, %eax
// CHECK: vpextrw.s $123, %xmm28, %r8d
// CHECK: encoding: [0x62,0x43,0x7d,0x08,0x15,0xe0,0x7b]
vpextrw.s $0x7b, %xmm28, %r8d
// CHECK: vpextrw.s $171, %xmm28, %eax
// CHECK: encoding: [0x62,0x63,0x7d,0x08,0x15,0xe0,0xab]
vpextrw.s $0xab, %xmm28, %eax
// CHECK: vpextrw.s $123, %xmm28, %eax
// CHECK: encoding: [0x62,0x63,0x7d,0x08,0x15,0xe0,0x7b]
vpextrw.s $0x7b, %xmm28, %eax
// CHECK: vpextrw.s $123, %xmm28, %r8d
// CHECK: encoding: [0x62,0x43,0x7d,0x08,0x15,0xe0,0x7b]
vpextrw.s $0x7b, %xmm28, %r8d
// CHECK: vpextrw.s $171, %xmm20, %eax
// CHECK: encoding: [0x62,0xe3,0x7d,0x08,0x15,0xe0,0xab]
vpextrw.s $0xab, %xmm20, %eax
// CHECK: vpextrw.s $123, %xmm20, %eax
// CHECK: encoding: [0x62,0xe3,0x7d,0x08,0x15,0xe0,0x7b]
vpextrw.s $0x7b, %xmm20, %eax
// CHECK: vpextrw.s $123, %xmm20, %r8d
// CHECK: encoding: [0x62,0xc3,0x7d,0x08,0x15,0xe0,0x7b]
vpextrw.s $0x7b, %xmm20, %r8d
// CHECK: vpextrw.s $171, %xmm19, %eax
// CHECK: encoding: [0x62,0xe3,0x7d,0x08,0x15,0xd8,0xab]
vpextrw.s $0xab, %xmm19, %eax
// CHECK: vpextrw.s $123, %xmm19, %eax
// CHECK: encoding: [0x62,0xe3,0x7d,0x08,0x15,0xd8,0x7b]
vpextrw.s $0x7b, %xmm19, %eax
// CHECK: vpextrw.s $123, %xmm19, %r8d
// CHECK: encoding: [0x62,0xc3,0x7d,0x08,0x15,0xd8,0x7b]
vpextrw.s $0x7b, %xmm19, %r8d