This is an archive of the discontinued LLVM Phabricator instance.

Differential D145630

[test] Remove occurences of br undef in CodeGen/Hexagon tests
Needs RevisionPublic

Authored by kritgpt on Mar 8 2023, 4:29 PM.

Details

Reviewers
nlopes
Summary

This patch removes br undef as suggested by https://discourse.llvm.org/t/please-dont-use-br-undef-in-tests-aka-please-avoid-test-cases-with-ub/63115. Script used: https://gist.github.com/kritgpt/69bfc7ef78e1784716c693d531a58adf.

Diff Detail

Unit TestsFailed

TimeTest
60 msx64 debian > LLVM.CodeGen/Hexagon::branchfolder-keep-impdef.ll
50 msx64 debian > LLVM.CodeGen/Hexagon::bug17386.ll
40 msx64 debian > LLVM.CodeGen/Hexagon::getBlockAddress.ll
80 msx64 debian > LLVM.CodeGen/Hexagon::packetize-impdef-1.ll
60 msx64 debian > LLVM.CodeGen/Hexagon::swp-prolog-phi.ll
View Full Test Results (6 Failed)

Event Timeline

kritgpt created this revision.Mar 8 2023, 4:29 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 8 2023, 4:29 PM
Herald added subscribers: arphaman, qcolombet, MatzeB. · View Herald Transcript
kritgpt requested review of this revision.Mar 8 2023, 4:29 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 8 2023, 4:29 PM
Herald added a subscriber: llvm-commits. · View Herald Transcript
kritgpt added a reviewer: nlopes.Mar 8 2023, 4:35 PM
Harbormaster completed remote builds in B218242: Diff 503559.Mar 8 2023, 5:32 PM
nlopes requested changes to this revision.Mar 9 2023, 12:06 AM

tests failing

This revision now requires changes to proceed.Mar 9 2023, 12:06 AM

Revision Contents

PathSize
llvm/
test/
CodeGen/
Hexagon/
6 lines
8 lines
24 lines
4 lines
4 lines
autohvx/
4 lines
4 lines
4 lines
4 lines
4 lines
10 lines
6 lines
4 lines
4 lines
4 lines
12 lines
4 lines
12 lines
4 lines
20 lines
4 lines
4 lines
4 lines
10 lines
4 lines
4 lines
6 lines
6 lines
6 lines
8 lines
4 lines
4 lines
4 lines
4 lines
10 lines
4 lines
10 lines
8 lines
11 lines
14 lines
6 lines
4 lines
4 lines
8 lines
4 lines
4 lines
6 lines
4 lines
6 lines
6 lines
4 lines
4 lines
8 lines
6 lines
29 lines
4 lines
4 lines
4 lines
loop-idiom/
10 lines
6 lines
5 lines
16 lines
4 lines
8 lines
6 lines
6 lines
36 lines
10 lines
32 lines
4 lines
4 lines
4 lines
22 lines
6 lines
4 lines
10 lines
8 lines
28 lines
4 lines
8 lines
4 lines
4 lines
4 lines
4 lines
4 lines
4 lines
12 lines
22 lines
6 lines
4 lines
8 lines
6 lines
4 lines
6 lines
4 lines
8 lines
12 lines
4 lines
16 lines
7 lines
11 lines
4 lines
10 lines
4 lines
4 lines
4 lines
4 lines
6 lines
8 lines
6 lines
7 lines
18 lines
8 lines
4 lines
6 lines
12 lines
6 lines
8 lines
13 lines
4 lines
17 lines
6 lines
4 lines
6 lines
4 lines
4 lines
4 lines
16 lines
4 lines
4 lines
7 lines
6 lines
8 lines
7 lines
4 lines
4 lines
14 lines
4 lines
4 lines
10 lines
5 lines
11 lines
6 lines
4 lines
8 lines
6 lines
4 lines
4 lines
4 lines
4 lines
4 lines
vect/
4 lines
6 lines
8 lines
10 lines
10 lines
8 lines
4 lines
4 lines
4 lines

Diff 503559

llvm/test/CodeGen/Hexagon/Halide_vec_cast_trunc1.ll

; RUN: llc -march=hexagon -O2 < %s ; RUN: llc -march=hexagon -O2 < %s
; REQUIRES: asserts ; REQUIRES: asserts
target triple = "hexagon-unknown--elf" target triple = "hexagon-unknown--elf"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0() #0 { define void @f0(i1 %c0, i1 %c1) #0 {
b0: b0:
br i1 undef, label %b1, label %b4, !prof !3 br i1 %c0, label %b1, label %b4, !prof !3
b1: ; preds = %b3, %b0 b1: ; preds = %b3, %b0
br label %b2 br label %b2
b2: ; preds = %b2, %b1 b2: ; preds = %b2, %b1
%v0 = load <32 x i32>, ptr undef, align 512, !tbaa !4 %v0 = load <32 x i32>, ptr undef, align 512, !tbaa !4
%v1 = shufflevector <32 x i32> %v0, <32 x i32> undef, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63> %v1 = shufflevector <32 x i32> %v0, <32 x i32> undef, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
%v2 = shufflevector <64 x i32> %v1, <64 x i32> undef, <128 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63, i32 64, i32 65, i32 66, i32 67, i32 68, i32 69, i32 70, i32 71, i32 72, i32 73, i32 74, i32 75, i32 76, i32 77, i32 78, i32 79, i32 80, i32 81, i32 82, i32 83, i32 84, i32 85, i32 86, i32 87, i32 88, i32 89, i32 90, i32 91, i32 92, i32 93, i32 94, i32 95, i32 96, i32 97, i32 98, i32 99, i32 100, i32 101, i32 102, i32 103, i32 104, i32 105, i32 106, i32 107, i32 108, i32 109, i32 110, i32 111, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126, i32 127> %v2 = shufflevector <64 x i32> %v1, <64 x i32> undef, <128 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63, i32 64, i32 65, i32 66, i32 67, i32 68, i32 69, i32 70, i32 71, i32 72, i32 73, i32 74, i32 75, i32 76, i32 77, i32 78, i32 79, i32 80, i32 81, i32 82, i32 83, i32 84, i32 85, i32 86, i32 87, i32 88, i32 89, i32 90, i32 91, i32 92, i32 93, i32 94, i32 95, i32 96, i32 97, i32 98, i32 99, i32 100, i32 101, i32 102, i32 103, i32 104, i32 105, i32 106, i32 107, i32 108, i32 109, i32 110, i32 111, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126, i32 127>
%v3 = trunc <128 x i32> %v2 to <128 x i16> %v3 = trunc <128 x i32> %v2 to <128 x i16>
%v4 = mul nsw <128 x i16> undef, %v3 %v4 = mul nsw <128 x i16> undef, %v3
%v5 = bitcast <128 x i16> %v4 to <64 x i32> %v5 = bitcast <128 x i16> %v4 to <64 x i32>
%v6 = tail call <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32> undef, <64 x i32> %v5) %v6 = tail call <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32> undef, <64 x i32> %v5)
%v7 = tail call <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32> %v6, <64 x i32> undef) %v7 = tail call <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32> %v6, <64 x i32> undef)
br i1 undef, label %b3, label %b2 br i1 %c1, label %b3, label %b2
b3: ; preds = %b2 b3: ; preds = %b2
%v8 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v7) %v8 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v7)
%v9 = tail call <32 x i32> @llvm.hexagon.V6.vasrhubsat.128B(<32 x i32> %v8, <32 x i32> undef, i32 4) %v9 = tail call <32 x i32> @llvm.hexagon.V6.vasrhubsat.128B(<32 x i32> %v8, <32 x i32> undef, i32 4)
store <32 x i32> %v9, ptr undef, align 1, !tbaa !7 store <32 x i32> %v9, ptr undef, align 1, !tbaa !7
br label %b1 br label %b1
b4: ; preds = %b0 b4: ; preds = %b0
Show All 26 Lines

llvm/test/CodeGen/Hexagon/Halide_vec_cast_trunc2.ll

; RUN: llc -march=hexagon -O2 < %s ; RUN: llc -march=hexagon -O2 < %s
; REQUIRES: asserts ; REQUIRES: asserts
target triple = "hexagon-unknown--elf" target triple = "hexagon-unknown--elf"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0() #0 { define void @f0(i1 %c0, i1 %c1, i1 %c2) #0 {
b0: b0:
br i1 undef, label %b1, label %b6, !prof !3 br i1 %c0, label %b1, label %b6, !prof !3
b1: ; preds = %b0 b1: ; preds = %b0
br i1 undef, label %b2, label %b3, !prof !3 br i1 %c1, label %b2, label %b3, !prof !3
b2: ; preds = %b1 b2: ; preds = %b1
unreachable unreachable
b3: ; preds = %b1 b3: ; preds = %b1
br label %b4 br label %b4
b4: ; preds = %b4, %b3 b4: ; preds = %b4, %b3
%v0 = load <32 x i32>, ptr undef, align 512, !tbaa !4 %v0 = load <32 x i32>, ptr undef, align 512, !tbaa !4
%v1 = shufflevector <32 x i32> %v0, <32 x i32> undef, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63> %v1 = shufflevector <32 x i32> %v0, <32 x i32> undef, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
%v2 = shufflevector <64 x i32> undef, <64 x i32> %v1, <128 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63, i32 64, i32 65, i32 66, i32 67, i32 68, i32 69, i32 70, i32 71, i32 72, i32 73, i32 74, i32 75, i32 76, i32 77, i32 78, i32 79, i32 80, i32 81, i32 82, i32 83, i32 84, i32 85, i32 86, i32 87, i32 88, i32 89, i32 90, i32 91, i32 92, i32 93, i32 94, i32 95, i32 96, i32 97, i32 98, i32 99, i32 100, i32 101, i32 102, i32 103, i32 104, i32 105, i32 106, i32 107, i32 108, i32 109, i32 110, i32 111, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126, i32 127> %v2 = shufflevector <64 x i32> undef, <64 x i32> %v1, <128 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63, i32 64, i32 65, i32 66, i32 67, i32 68, i32 69, i32 70, i32 71, i32 72, i32 73, i32 74, i32 75, i32 76, i32 77, i32 78, i32 79, i32 80, i32 81, i32 82, i32 83, i32 84, i32 85, i32 86, i32 87, i32 88, i32 89, i32 90, i32 91, i32 92, i32 93, i32 94, i32 95, i32 96, i32 97, i32 98, i32 99, i32 100, i32 101, i32 102, i32 103, i32 104, i32 105, i32 106, i32 107, i32 108, i32 109, i32 110, i32 111, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126, i32 127>
%v3 = trunc <128 x i32> %v2 to <128 x i16> %v3 = trunc <128 x i32> %v2 to <128 x i16>
%v4 = mul nsw <128 x i16> undef, %v3 %v4 = mul nsw <128 x i16> undef, %v3
%v5 = bitcast <128 x i16> %v4 to <64 x i32> %v5 = bitcast <128 x i16> %v4 to <64 x i32>
%v6 = tail call <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32> undef, <64 x i32> %v5) %v6 = tail call <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32> undef, <64 x i32> %v5)
%v7 = bitcast <64 x i32> %v6 to <128 x i16> %v7 = bitcast <64 x i32> %v6 to <128 x i16>
%v8 = shufflevector <128 x i16> %v7, <128 x i16> undef, <64 x i32> <i32 64, i32 65, i32 66, i32 67, i32 68, i32 69, i32 70, i32 71, i32 72, i32 73, i32 74, i32 75, i32 76, i32 77, i32 78, i32 79, i32 80, i32 81, i32 82, i32 83, i32 84, i32 85, i32 86, i32 87, i32 88, i32 89, i32 90, i32 91, i32 92, i32 93, i32 94, i32 95, i32 96, i32 97, i32 98, i32 99, i32 100, i32 101, i32 102, i32 103, i32 104, i32 105, i32 106, i32 107, i32 108, i32 109, i32 110, i32 111, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126, i32 127> %v8 = shufflevector <128 x i16> %v7, <128 x i16> undef, <64 x i32> <i32 64, i32 65, i32 66, i32 67, i32 68, i32 69, i32 70, i32 71, i32 72, i32 73, i32 74, i32 75, i32 76, i32 77, i32 78, i32 79, i32 80, i32 81, i32 82, i32 83, i32 84, i32 85, i32 86, i32 87, i32 88, i32 89, i32 90, i32 91, i32 92, i32 93, i32 94, i32 95, i32 96, i32 97, i32 98, i32 99, i32 100, i32 101, i32 102, i32 103, i32 104, i32 105, i32 106, i32 107, i32 108, i32 109, i32 110, i32 111, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126, i32 127>
br i1 undef, label %b5, label %b4 br i1 %c2, label %b5, label %b4
b5: ; preds = %b4 b5: ; preds = %b4
store <64 x i16> %v8, ptr undef, align 1024, !tbaa !7 store <64 x i16> %v8, ptr undef, align 1024, !tbaa !7
br label %b6 br label %b6
b6: ; preds = %b5, %b0 b6: ; preds = %b5, %b0
ret void ret void
} }
Show All 23 Lines

llvm/test/CodeGen/Hexagon/NVJumpCmp.ll

; RUN: llc -march=hexagon -O2 -mcpu=hexagonv60 < %s | FileCheck %s ; RUN: llc -march=hexagon -O2 -mcpu=hexagonv60 < %s | FileCheck %s
; Look for an instruction, we really just do not want to see an abort. ; Look for an instruction, we really just do not want to see an abort.
; CHECK: trace_event ; CHECK: trace_event
; REQUIRES: asserts ; REQUIRES: asserts
target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32" target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32"
target triple = "hexagon-unknown--elf" target triple = "hexagon-unknown--elf"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @_ZN6Halide7Runtime8Internal13default_traceEPvPK18halide_trace_event() #0 { define void @_ZN6Halide7Runtime8Internal13default_traceEPvPK18halide_trace_event(i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, i1 %c10) #0 {
entry: entry:
br i1 undef, label %if.then, label %if.else br i1 %c0, label %if.then, label %if.else
if.then: ; preds = %entry if.then: ; preds = %entry
br label %while.cond br label %while.cond
while.cond: ; preds = %while.cond, %if.then while.cond: ; preds = %while.cond, %if.then
br i1 undef, label %while.cond, label %while.end br i1 %c1, label %while.cond, label %while.end
while.end: ; preds = %while.cond while.end: ; preds = %while.cond
%add = add i32 undef, 48 %add = add i32 undef, 48
br i1 undef, label %if.end, label %if.then17 br i1 %c2, label %if.end, label %if.then17
if.then17: ; preds = %while.end if.then17: ; preds = %while.end
unreachable unreachable
if.end: ; preds = %while.end if.end: ; preds = %while.end
%arrayidx21 = getelementptr inbounds [4096 x i8], ptr undef, i32 0, i32 8 %arrayidx21 = getelementptr inbounds [4096 x i8], ptr undef, i32 0, i32 8
store i8 undef, ptr %arrayidx21, align 4, !tbaa !1 store i8 undef, ptr %arrayidx21, align 4, !tbaa !1
br i1 undef, label %for.body42.preheader6, label %min.iters.checked br i1 %c3, label %for.body42.preheader6, label %min.iters.checked
for.body42.preheader6: ; preds = %vector.body.preheader, %min.iters.checked, %if.end for.body42.preheader6: ; preds = %vector.body.preheader, %min.iters.checked, %if.end
unreachable unreachable
min.iters.checked: ; preds = %if.end min.iters.checked: ; preds = %if.end
br i1 undef, label %for.body42.preheader6, label %vector.body.preheader br i1 %c4, label %for.body42.preheader6, label %vector.body.preheader
vector.body.preheader: ; preds = %min.iters.checked vector.body.preheader: ; preds = %min.iters.checked
br i1 undef, label %for.cond48.preheader, label %for.body42.preheader6 br i1 %c5, label %for.cond48.preheader, label %for.body42.preheader6
for.cond48.preheader: ; preds = %vector.body.preheader for.cond48.preheader: ; preds = %vector.body.preheader
br i1 undef, label %while.cond.i, label %for.body61.lr.ph br i1 %c6, label %while.cond.i, label %for.body61.lr.ph
for.body61.lr.ph: ; preds = %for.cond48.preheader for.body61.lr.ph: ; preds = %for.cond48.preheader
br i1 undef, label %for.body61, label %min.iters.checked595 br i1 %c7, label %for.body61, label %min.iters.checked595
min.iters.checked595: ; preds = %for.body61.lr.ph min.iters.checked595: ; preds = %for.body61.lr.ph
br i1 undef, label %for.body61, label %vector.memcheck608 br i1 %c8, label %for.body61, label %vector.memcheck608
vector.memcheck608: ; preds = %min.iters.checked595 vector.memcheck608: ; preds = %min.iters.checked595
%scevgep600 = getelementptr [4096 x i8], ptr undef, i32 0, i32 %add %scevgep600 = getelementptr [4096 x i8], ptr undef, i32 0, i32 %add
%bound0604 = icmp ule ptr %scevgep600, undef %bound0604 = icmp ule ptr %scevgep600, undef
%memcheck.conflict607 = and i1 undef, %bound0604 %memcheck.conflict607 = and i1 undef, %bound0604
br i1 %memcheck.conflict607, label %for.body61, label %vector.body590 br i1 %memcheck.conflict607, label %for.body61, label %vector.body590
vector.body590: ; preds = %vector.body590, %vector.memcheck608 vector.body590: ; preds = %vector.body590, %vector.memcheck608
br i1 undef, label %middle.block591, label %vector.body590, !llvm.loop !4 br i1 %c9, label %middle.block591, label %vector.body590, !llvm.loop !4
middle.block591: ; preds = %vector.body590 middle.block591: ; preds = %vector.body590
%cmp.n613 = icmp eq i32 undef, 0 %cmp.n613 = icmp eq i32 undef, 0
br i1 %cmp.n613, label %while.cond.i, label %for.body61 br i1 %cmp.n613, label %while.cond.i, label %for.body61
while.cond.i: ; preds = %for.body61, %while.cond.i, %middle.block591, %for.cond48.preheader while.cond.i: ; preds = %for.body61, %while.cond.i, %middle.block591, %for.cond48.preheader
br i1 undef, label %_ZN6Halide7Runtime8Internal14ScopedSpinLockC2EPVi.exit, label %while.cond.i br i1 %c10, label %_ZN6Halide7Runtime8Internal14ScopedSpinLockC2EPVi.exit, label %while.cond.i
_ZN6Halide7Runtime8Internal14ScopedSpinLockC2EPVi.exit: ; preds = %while.cond.i _ZN6Halide7Runtime8Internal14ScopedSpinLockC2EPVi.exit: ; preds = %while.cond.i
unreachable unreachable
for.body61: ; preds = %for.body61, %middle.block591, %vector.memcheck608, %min.iters.checked595, %for.body61.lr.ph for.body61: ; preds = %for.body61, %middle.block591, %vector.memcheck608, %min.iters.checked595, %for.body61.lr.ph
%cmp59 = icmp ult i32 undef, undef %cmp59 = icmp ult i32 undef, undef
br i1 %cmp59, label %for.body61, label %while.cond.i, !llvm.loop !7 br i1 %cmp59, label %for.body61, label %while.cond.i, !llvm.loop !7
Show All 16 Lines

llvm/test/CodeGen/Hexagon/addrmode-keepdeadphis.ll

Show All 13 Lines
target triple = "hexagon" target triple = "hexagon"
%s.0 = type { i8, i8, %s.1, i32 } %s.0 = type { i8, i8, %s.1, i32 }
%s.1 = type { %s.2, [128 x i8] } %s.1 = type { %s.2, [128 x i8] }
%s.2 = type { i8, i8, i64, %s.3 } %s.2 = type { i8, i8, i64, %s.3 }
%s.3 = type { i8 } %s.3 = type { i8 }
define void @f0.1() local_unnamed_addr #0 align 2 { define void @f0.1(i1 %c0) local_unnamed_addr #0 align 2 {
b0: b0:
%v0 = alloca %s.0, align 8 %v0 = alloca %s.0, align 8
%v1 = getelementptr inbounds %s.0, ptr %v0, i32 0, i32 1 %v1 = getelementptr inbounds %s.0, ptr %v0, i32 0, i32 1
store i8 4, ptr %v1, align 1 store i8 4, ptr %v1, align 1
%v2 = call signext i8 @f1.2(ptr undef) #0 %v2 = call signext i8 @f1.2(ptr undef) #0
%v3 = getelementptr inbounds %s.0, ptr %v0, i32 0, i32 2, i32 0, i32 0 %v3 = getelementptr inbounds %s.0, ptr %v0, i32 0, i32 2, i32 0, i32 0
%v4 = getelementptr inbounds %s.0, ptr %v0, i32 0, i32 2, i32 0, i32 3, i32 0 %v4 = getelementptr inbounds %s.0, ptr %v0, i32 0, i32 2, i32 0, i32 3, i32 0
store i8 -1, ptr %v4, align 8 store i8 -1, ptr %v4, align 8
br i1 undef, label %b1, label %b2 br i1 %c0, label %b1, label %b2
b1: ; preds = %b0 b1: ; preds = %b0
%v5 = call dereferenceable(12) ptr @f2.3(ptr nonnull undef, ptr nonnull dereferenceable(80) undef) #0 %v5 = call dereferenceable(12) ptr @f2.3(ptr nonnull undef, ptr nonnull dereferenceable(80) undef) #0
%v6 = call signext i8 @f1.2(ptr undef) #0 %v6 = call signext i8 @f1.2(ptr undef) #0
%v7 = call dereferenceable(12) ptr @f3(ptr nonnull %v5, i16 signext undef) #0 %v7 = call dereferenceable(12) ptr @f3(ptr nonnull %v5, i16 signext undef) #0
br label %b2 br label %b2
b2: ; preds = %b1, %b0 b2: ; preds = %b1, %b0
Show All 11 Lines

llvm/test/CodeGen/Hexagon/always-ext.ll

Show All 12 Lines
%struct.CuTest.1.28.31.37.40.43.52.55.67.85.111 = type { ptr, ptr, i32, i32, ptr, ptr } %struct.CuTest.1.28.31.37.40.43.52.55.67.85.111 = type { ptr, ptr, i32, i32, ptr, ptr }
%struct.CuSuite.2.29.32.38.41.44.53.56.68.86.112 = type { i32, [1024 x ptr], i32 } %struct.CuSuite.2.29.32.38.41.44.53.56.68.86.112 = type { i32, [1024 x ptr], i32 }
@__func__.CuSuiteAdd = external unnamed_addr constant [11 x i8], align 8 @__func__.CuSuiteAdd = external unnamed_addr constant [11 x i8], align 8
@.str24 = external unnamed_addr constant [140 x i8], align 8 @.str24 = external unnamed_addr constant [140 x i8], align 8
declare void @_Assert() declare void @_Assert()
define void @CuSuiteAddSuite() nounwind { define void @CuSuiteAddSuite(i1 %c0) nounwind {
entry: entry:
br i1 undef, label %for.body.us, label %for.end br i1 %c0, label %for.body.us, label %for.end
for.body.us: ; preds = %entry for.body.us: ; preds = %entry
%0 = load ptr, ptr null, align 4 %0 = load ptr, ptr null, align 4
%1 = load i32, ptr undef, align 4 %1 = load i32, ptr undef, align 4
%cmp.i.us = icmp slt i32 %1, 1024 %cmp.i.us = icmp slt i32 %1, 1024
br i1 %cmp.i.us, label %CuSuiteAdd.exit.us, label %cond.false6.i.us br i1 %cmp.i.us, label %CuSuiteAdd.exit.us, label %cond.false6.i.us
cond.false6.i.us: ; preds = %for.body.us cond.false6.i.us: ; preds = %for.body.us
Show All 14 Lines

llvm/test/CodeGen/Hexagon/autohvx/isel-bitcast-vsplat.ll

Show All 11 Lines
target triple = "hexagon" target triple = "hexagon"
%s.0 = type { %s.1 } %s.0 = type { %s.1 }
%s.1 = type { i32, ptr } %s.1 = type { i32, ptr }
%s.2 = type { i8, i8, [16 x i8], i8, [16 x i8] } %s.2 = type { i8, i8, [16 x i8], i8, [16 x i8] }
; Function Attrs: nounwind ; Function Attrs: nounwind
define dso_local zeroext i8 @f0(i8 zeroext %a0, ptr nocapture readonly %a1, i8 signext %a2) local_unnamed_addr #0 { define dso_local zeroext i8 @f0(i8 zeroext %a0, ptr nocapture readonly %a1, i8 signext %a2, i1 %c0) local_unnamed_addr #0 {
b0: b0:
br i1 undef, label %b2, label %b1 br i1 %c0, label %b2, label %b1
b1: ; preds = %b0 b1: ; preds = %b0
%v0 = load <64 x i8>, ptr undef, align 1 %v0 = load <64 x i8>, ptr undef, align 1
%v1 = icmp ult <64 x i8> %v0, <i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52> %v1 = icmp ult <64 x i8> %v0, <i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52>
%v2 = xor <64 x i1> %v1, zeroinitializer %v2 = xor <64 x i1> %v1, zeroinitializer
%v3 = select <64 x i1> %v2, <64 x i32> undef, <64 x i32> zeroinitializer %v3 = select <64 x i1> %v2, <64 x i32> undef, <64 x i32> zeroinitializer
%v4 = select <64 x i1> zeroinitializer, <64 x i32> <i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000>, <64 x i32> %v3 %v4 = select <64 x i1> zeroinitializer, <64 x i32> <i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000>, <64 x i32> %v3
%v5 = add <64 x i32> %v4, zeroinitializer %v5 = add <64 x i32> %v4, zeroinitializer
Show All 20 Lines

llvm/test/CodeGen/Hexagon/autohvx/isel-const-splat-imm.ll

; RUN: llc -march=hexagon -hexagon-hvx-widen=32 < %s | FileCheck %s ; RUN: llc -march=hexagon -hexagon-hvx-widen=32 < %s | FileCheck %s
; Check that this doesn't crash. A "splat_vector" was causing trouble, ; Check that this doesn't crash. A "splat_vector" was causing trouble,
; initially, so check that a vsplat appears in the output. ; initially, so check that a vsplat appears in the output.
; CHECK: vsplat ; CHECK: vsplat
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon" target triple = "hexagon"
@g0 = external dllexport local_unnamed_addr global ptr, align 4 @g0 = external dllexport local_unnamed_addr global ptr, align 4
; Function Attrs: noinline ; Function Attrs: noinline
define dso_local fastcc void @f0(ptr %a0, i32 %a1) unnamed_addr #0 { define dso_local fastcc void @f0(ptr %a0, i32 %a1, i1 %c0) unnamed_addr #0 {
b0: b0:
br i1 undef, label %b2, label %b1 br i1 %c0, label %b2, label %b1
b1: ; preds = %b0 b1: ; preds = %b0
%v0 = add nsw <8 x i32> zeroinitializer, <i32 -22, i32 -22, i32 -22, i32 -22, i32 -22, i32 -22, i32 -22, i32 -22> %v0 = add nsw <8 x i32> zeroinitializer, <i32 -22, i32 -22, i32 -22, i32 -22, i32 -22, i32 -22, i32 -22, i32 -22>
%v1 = load <8 x i32>, ptr undef, align 32 %v1 = load <8 x i32>, ptr undef, align 32
%v2 = shl <8 x i32> %v1, <i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24> %v2 = shl <8 x i32> %v1, <i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24>
%v3 = ashr exact <8 x i32> %v2, <i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24> %v3 = ashr exact <8 x i32> %v2, <i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24>
%v4 = add nsw <8 x i32> %v3, <i32 128, i32 128, i32 128, i32 128, i32 128, i32 128, i32 128, i32 128> %v4 = add nsw <8 x i32> %v3, <i32 128, i32 128, i32 128, i32 128, i32 128, i32 128, i32 128, i32 128>
%v5 = zext <8 x i32> %v4 to <8 x i64> %v5 = zext <8 x i32> %v4 to <8 x i64>
▲ Show 20 Lines • Show All 84 Lines • Show Last 20 Lines

llvm/test/CodeGen/Hexagon/autohvx/vector-align-rescale-nonint.ll

; RUN: llc -march=hexagon < %s | FileCheck %s ; RUN: llc -march=hexagon < %s | FileCheck %s
; Check that this doesn't crash. ; Check that this doesn't crash.
; CHECK: vmem ; CHECK: vmem
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon" target triple = "hexagon"
define dllexport void @f0(ptr %a0, <32 x float> %a1, <32 x float> %a2) local_unnamed_addr #0 { define dllexport void @f0(ptr %a0, <32 x float> %a1, <32 x float> %a2, i1 %c0) local_unnamed_addr #0 {
b0: b0:
%v0 = add nuw nsw i32 0, 64 %v0 = add nuw nsw i32 0, 64
%v1 = getelementptr inbounds float, ptr %a0, i32 %v0 %v1 = getelementptr inbounds float, ptr %a0, i32 %v0
%v3 = add nuw nsw i32 0, 96 %v3 = add nuw nsw i32 0, 96
%v4 = getelementptr inbounds float, ptr %a0, i32 %v3 %v4 = getelementptr inbounds float, ptr %a0, i32 %v3
br label %b1 br label %b1
b1: ; preds = %b1, %b0 b1: ; preds = %b1, %b0
br i1 undef, label %b2, label %b1 br i1 %c0, label %b2, label %b1
b2: ; preds = %b1 b2: ; preds = %b1
store <32 x float> %a1, ptr %v1, align 4 store <32 x float> %a1, ptr %v1, align 4
store <32 x float> %a2, ptr %v4, align 4 store <32 x float> %a2, ptr %v4, align 4
ret void ret void
} }
attributes #0 = { "target-features"="+hvxv69,+hvx-length128b,+hvx-qfloat" } attributes #0 = { "target-features"="+hvxv69,+hvx-length128b,+hvx-qfloat" }

llvm/test/CodeGen/Hexagon/autohvx/vector-align-scalar-mask.ll

; RUN: llc -march=hexagon < %s | FileCheck %s ; RUN: llc -march=hexagon < %s | FileCheck %s
; Check that this doesn't crash. ; Check that this doesn't crash.
; CHECK: vmem ; CHECK: vmem
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon" target triple = "hexagon"
define dllexport void @f0(ptr %a0, i32 %a1, i32 %a2, <32 x i32> %a3) local_unnamed_addr #0 { define dllexport void @f0(ptr %a0, i32 %a1, i32 %a2, <32 x i32> %a3, i1 %c0) local_unnamed_addr #0 {
b0: b0:
%v0 = add nuw nsw i32 0, 96 %v0 = add nuw nsw i32 0, 96
%v1 = getelementptr inbounds i32, ptr %a0, i32 %v0 %v1 = getelementptr inbounds i32, ptr %a0, i32 %v0
%v3 = add nuw nsw i32 0, 225 %v3 = add nuw nsw i32 0, 225
%v4 = getelementptr inbounds i32, ptr %a0, i32 %v3 %v4 = getelementptr inbounds i32, ptr %a0, i32 %v3
%v5 = add nuw nsw i32 0, 226 %v5 = add nuw nsw i32 0, 226
%v6 = getelementptr inbounds i32, ptr %a0, i32 %v5 %v6 = getelementptr inbounds i32, ptr %a0, i32 %v5
br label %b1 br label %b1
b1: ; preds = %b1, %b0 b1: ; preds = %b1, %b0
br i1 undef, label %b2, label %b1 br i1 %c0, label %b2, label %b1
b2: ; preds = %b1 b2: ; preds = %b1
store <32 x i32> %a3, ptr %v1, align 4 store <32 x i32> %a3, ptr %v1, align 4
store i32 %a1, ptr %v4, align 4 store i32 %a1, ptr %v4, align 4
store i32 %a2, ptr %v6, align 4 store i32 %a2, ptr %v6, align 4
ret void ret void
} }
attributes #0 = { "target-features"="+hvxv66,+hvx-length128b" } attributes #0 = { "target-features"="+hvxv66,+hvx-length128b" }

llvm/test/CodeGen/Hexagon/autohvx/vector-align-store-mask.ll

; RUN: llc -march=hexagon -hexagon-hvx-widen=32 < %s | FileCheck %s ; RUN: llc -march=hexagon -hexagon-hvx-widen=32 < %s | FileCheck %s
target triple = "hexagon" target triple = "hexagon"
; Test the the store mask is adjusted for gaps between sections. The ; Test the the store mask is adjusted for gaps between sections. The
; Vector Combine pass generates masked stores for chunks of 128 bytes. ; Vector Combine pass generates masked stores for chunks of 128 bytes.
; The masked store must be shifted if the first store in a section ; The masked store must be shifted if the first store in a section
; is not a multiple of 128 bytes. This test checks that two masks ; is not a multiple of 128 bytes. This test checks that two masks
; are created, and the second mask is used in a masked store. ; are created, and the second mask is used in a masked store.
; CHECK: [[REG:r[0-9]+]] = ##.LCPI0_1 ; CHECK: [[REG:r[0-9]+]] = ##.LCPI0_1
; CHECK: [[VREG1:v[0-9]+]] = vmem([[REG]]+#0) ; CHECK: [[VREG1:v[0-9]+]] = vmem([[REG]]+#0)
; CHECK: [[VREG2:v[0-9]+]] = vlalign([[VREG1]],v{{[0-9]+}},r{{[0-9]+}}) ; CHECK: [[VREG2:v[0-9]+]] = vlalign([[VREG1]],v{{[0-9]+}},r{{[0-9]+}})
; CHECK: [[QREG:q[0-3]+]] = vand([[VREG2]],r{{[0-9]+}}) ; CHECK: [[QREG:q[0-3]+]] = vand([[VREG2]],r{{[0-9]+}})
; CHECK: if ([[QREG]]) vmem({{.*}}) = v{{[0-9]+}} ; CHECK: if ([[QREG]]) vmem({{.*}}) = v{{[0-9]+}}
define dllexport void @f0(ptr %a0) local_unnamed_addr #0 { define dllexport void @f0(ptr %a0, i1 %c0) local_unnamed_addr #0 {
b0: b0:
br label %b1 br label %b1
b1: ; preds = %b1, %b0 b1: ; preds = %b1, %b0
%v0 = or i32 -1, 40 %v0 = or i32 -1, 40
%v1 = getelementptr inbounds i32, ptr %a0, i32 %v0 %v1 = getelementptr inbounds i32, ptr %a0, i32 %v0
store <8 x i32> undef, ptr %v1, align 32 store <8 x i32> undef, ptr %v1, align 32
%v3 = or i32 0, 48 %v3 = or i32 0, 48
%v4 = getelementptr inbounds i32, ptr %a0, i32 %v3 %v4 = getelementptr inbounds i32, ptr %a0, i32 %v3
store <8 x i32> undef, ptr %v4, align 64 store <8 x i32> undef, ptr %v4, align 64
br i1 undef, label %b2, label %b1 br i1 %c0, label %b2, label %b1
b2: ; preds = %b1 b2: ; preds = %b1
ret void ret void
} }
attributes #0 = { "target-features"="+hvxv66,+hvx-length128b" } attributes #0 = { "target-features"="+hvxv66,+hvx-length128b" }

llvm/test/CodeGen/Hexagon/avoid-predspill-calleesaved.ll

; Check that a callee-saved register will be saved correctly if ; Check that a callee-saved register will be saved correctly if
; the predicate-to-GPR spilling code uses it. ; the predicate-to-GPR spilling code uses it.
; ;
; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s ; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s
; ;
; We expect to spill p0 into a general-purpose register and keep it there, ; We expect to spill p0 into a general-purpose register and keep it there,
; without adding an extra spill of that register. ; without adding an extra spill of that register.
; ;
; CHECK: PredSpill: ; CHECK: PredSpill:
; CHECK-DAG: r{{[0-9]+}} = p0 ; CHECK-DAG: r{{[0-9]+}} = p0
; CHECK-DAG: p0 = r{{[0-9]+}} ; CHECK-DAG: p0 = r{{[0-9]+}}
; CHECK-NOT: = memw(r29 ; CHECK-NOT: = memw(r29
; ;
define void @PredSpill() { define void @PredSpill(i1 %c0, i1 %c1, i1 %c2, i1 %c3) {
entry: entry:
br i1 undef, label %if.then, label %if.else.14 br i1 %c0, label %if.then, label %if.else.14
if.then: ; preds = %entry if.then: ; preds = %entry
br i1 undef, label %if.end.57, label %if.else br i1 %c1, label %if.end.57, label %if.else
if.else: ; preds = %if.then if.else: ; preds = %if.then
unreachable unreachable
if.else.14: ; preds = %entry if.else.14: ; preds = %entry
br i1 undef, label %if.then.17, label %if.end.57 br i1 %c2, label %if.then.17, label %if.end.57
if.then.17: ; preds = %if.else.14 if.then.17: ; preds = %if.else.14
br i1 undef, label %if.end.57, label %if.then.20 br i1 %c3, label %if.end.57, label %if.then.20
if.then.20: ; preds = %if.then.17 if.then.20: ; preds = %if.then.17
%call21 = tail call i32 @myfun() %call21 = tail call i32 @myfun()
%tobool22 = icmp eq i32 %call21, 0 %tobool22 = icmp eq i32 %call21, 0
%0 = tail call i32 @myfun() %0 = tail call i32 @myfun()
br i1 %tobool22, label %if.else.42, label %if.then.23 br i1 %tobool22, label %if.else.42, label %if.then.23
if.then.23: ; preds = %if.then.20 if.then.23: ; preds = %if.then.20
Show All 11 Lines

llvm/test/CodeGen/Hexagon/base-offset-stv4.ll

; RUN: llc -march=hexagon -enable-pipeliner < %s ; RUN: llc -march=hexagon -enable-pipeliner < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0() #0 { define void @f0(i1 %c0, i1 %c1) #0 {
b0: b0:
br i1 undef, label %b1, label %b4 br i1 %c0, label %b1, label %b4
b1: ; preds = %b0 b1: ; preds = %b0
%v0 = load ptr, ptr undef, align 4 %v0 = load ptr, ptr undef, align 4
br label %b2 br label %b2
b2: ; preds = %b2, %b1 b2: ; preds = %b2, %b1
%v1 = phi i32 [ 13, %b1 ], [ %v5, %b2 ] %v1 = phi i32 [ 13, %b1 ], [ %v5, %b2 ]
%v2 = getelementptr inbounds i16, ptr %v0, i32 %v1 %v2 = getelementptr inbounds i16, ptr %v0, i32 %v1
%v3 = add nsw i32 0, %v1 %v3 = add nsw i32 0, %v1
%v4 = getelementptr inbounds i16, ptr %v0, i32 %v3 %v4 = getelementptr inbounds i16, ptr %v0, i32 %v3
store i16 0, ptr %v4, align 2 store i16 0, ptr %v4, align 2
store i16 0, ptr %v2, align 2 store i16 0, ptr %v2, align 2
%v5 = add i32 %v1, 1 %v5 = add i32 %v1, 1
%v6 = icmp eq i32 %v5, 26 %v6 = icmp eq i32 %v5, 26
br i1 %v6, label %b3, label %b2 br i1 %v6, label %b3, label %b2
b3: ; preds = %b3, %b2 b3: ; preds = %b3, %b2
br i1 undef, label %b4, label %b3 br i1 %c1, label %b4, label %b3
b4: ; preds = %b3, %b0 b4: ; preds = %b3, %b0
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

llvm/test/CodeGen/Hexagon/bit-bitsplit-regclass.ll

; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 -hexagon-instsimplify=0 < %s | FileCheck %s ; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 -hexagon-instsimplify=0 < %s | FileCheck %s
; Check for successful compilation. ; Check for successful compilation.
; CHECK: r{{[0-9]+}} = insert(r{{[0-9]+}},#1,#31) ; CHECK: r{{[0-9]+}} = insert(r{{[0-9]+}},#1,#31)
; This cannot be a .mir test, because the failure depends on ordering of ; This cannot be a .mir test, because the failure depends on ordering of
; virtual registers, and the .mir loader renumbers them in a way that hides ; virtual registers, and the .mir loader renumbers them in a way that hides
; the problem. ; the problem.
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon" target triple = "hexagon"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0() #0 align 2 { define void @f0(i1 %c0) #0 align 2 {
b0: b0:
br label %b1 br label %b1
b1: ; preds = %b3, %b0 b1: ; preds = %b3, %b0
%v0 = phi i64 [ 0, %b0 ], [ %v6, %b3 ] %v0 = phi i64 [ 0, %b0 ], [ %v6, %b3 ]
br i1 undef, label %b2, label %b3 br i1 %c0, label %b2, label %b3
b2: ; preds = %b1 b2: ; preds = %b1
br label %b3 br label %b3
b3: ; preds = %b2, %b1 b3: ; preds = %b2, %b1
%v1 = phi i64 [ undef, %b2 ], [ %v0, %b1 ] %v1 = phi i64 [ undef, %b2 ], [ %v0, %b1 ]
%v2 = and i64 %v1, 1 %v2 = and i64 %v1, 1
%v3 = trunc i64 %v2 to i32 %v3 = trunc i64 %v2 to i32
Show All 12 Lines

llvm/test/CodeGen/Hexagon/bit-has.ll

; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s ; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s
; REQUIRES: asserts ; REQUIRES: asserts
; This used to crash. Check for some sane output. ; This used to crash. Check for some sane output.
; CHECK: sath ; CHECK: sath
target triple = "hexagon" target triple = "hexagon"
define void @fred() local_unnamed_addr #0 { define void @fred(i1 %c0) local_unnamed_addr #0 {
b0: b0:
%v1 = load i32, ptr undef, align 4 %v1 = load i32, ptr undef, align 4
%v2 = tail call i32 @llvm.hexagon.A2.sath(i32 undef) %v2 = tail call i32 @llvm.hexagon.A2.sath(i32 undef)
%v3 = and i32 %v1, 603979776 %v3 = and i32 %v1, 603979776
%v4 = trunc i32 %v3 to i30 %v4 = trunc i32 %v3 to i30
switch i30 %v4, label %b22 [ switch i30 %v4, label %b22 [
i30 -536870912, label %b5 i30 -536870912, label %b5
i30 -469762048, label %b6 i30 -469762048, label %b6
Show All 15 Linesb6: ; preds = %b0
%v16 = and i32 %v15, 2147483647 %v16 = and i32 %v15, 2147483647
store i32 %v16, ptr undef, align 4 store i32 %v16, ptr undef, align 4
%v17 = lshr i64 %v14, 31 %v17 = lshr i64 %v14, 31
%v18 = trunc i64 %v17 to i32 %v18 = trunc i64 %v17 to i32
store i32 %v18, ptr undef, align 4 store i32 %v18, ptr undef, align 4
br label %b19 br label %b19
b19: ; preds = %b6 b19: ; preds = %b6
br i1 undef, label %b20, label %b21 br i1 %c0, label %b20, label %b21
b20: ; preds = %b19 b20: ; preds = %b19
unreachable unreachable
b21: ; preds = %b19 b21: ; preds = %b19
br label %b23 br label %b23
b22: ; preds = %b0 b22: ; preds = %b0
Show All 15 Lines

llvm/test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll

; RUN: llc -march=hexagon < %s ; RUN: llc -march=hexagon < %s
; REQUIRES: asserts ; REQUIRES: asserts
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon" target triple = "hexagon"
define weak_odr hidden i32 @fred(ptr %this, ptr nocapture readonly dereferenceable(4) %__k) #0 align 2 { define weak_odr hidden i32 @fred(ptr %this, ptr nocapture readonly dereferenceable(4) %__k, i1 %c0) #0 align 2 {
entry: entry:
%call = tail call i64 @danny(ptr %this, ptr nonnull dereferenceable(4) %__k) #2 %call = tail call i64 @danny(ptr %this, ptr nonnull dereferenceable(4) %__k) #2
%__p.sroa.0.0.extract.trunc = trunc i64 %call to i32 %__p.sroa.0.0.extract.trunc = trunc i64 %call to i32
br i1 undef, label %for.end, label %for.body br i1 %c0, label %for.end, label %for.body
for.body: ; preds = %for.body, %entry for.body: ; preds = %for.body, %entry
%__p.sroa.0.018 = phi i32 [ %call8, %for.body ], [ %__p.sroa.0.0.extract.trunc, %entry ] %__p.sroa.0.018 = phi i32 [ %call8, %for.body ], [ %__p.sroa.0.0.extract.trunc, %entry ]
%call8 = tail call i32 @sammy(ptr %this, i32 %__p.sroa.0.018) #2 %call8 = tail call i32 @sammy(ptr %this, i32 %__p.sroa.0.018) #2
%0 = inttoptr i32 %call8 to ptr %0 = inttoptr i32 %call8 to ptr
%lnot.i = icmp eq ptr %0, undef %lnot.i = icmp eq ptr %0, undef
br i1 %lnot.i, label %for.end, label %for.body br i1 %lnot.i, label %for.end, label %for.body
Show All 11 Lines

llvm/test/CodeGen/Hexagon/bit-phi.ll

; RUN: llc -march=hexagon < %s ; RUN: llc -march=hexagon < %s
; RUN: llc -march=hexagon -disable-hcp < %s ; RUN: llc -march=hexagon -disable-hcp < %s
; REQUIRES: asserts ; REQUIRES: asserts
target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32" target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32"
target triple = "hexagon-unknown--elf" target triple = "hexagon-unknown--elf"
%struct.item = type { i32, ptr, ptr, i32, i8, i8, i16, i32, i8, i16, i32 } %struct.item = type { i32, ptr, ptr, i32, i8, i8, i16, i32, i8, i16, i32 }
declare ptr @foo(ptr, ptr, i32) #1 declare ptr @foo(ptr, ptr, i32) #1
; Function Attrs: nounwind ; Function Attrs: nounwind
define i32 @bar(ptr %ptr, ptr %buf, i32 %c, ptr %d, i32 %e) #1 { define i32 @bar(ptr %ptr, ptr %buf, i32 %c, ptr %d, i32 %e, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4) #1 {
entry: entry:
br i1 undef, label %return, label %if.end br i1 %c0, label %return, label %if.end
if.end: ; preds = %entry if.end: ; preds = %entry
br i1 undef, label %while.cond13.preheader, label %if.end3 br i1 %c1, label %while.cond13.preheader, label %if.end3
if.end3: ; preds = %if.end if.end3: ; preds = %if.end
br label %while.cond13.preheader br label %while.cond13.preheader
while.cond13.preheader: ; preds = %if.end3, %if.end while.cond13.preheader: ; preds = %if.end3, %if.end
br i1 undef, label %while.body20, label %return br i1 %c2, label %while.body20, label %return
while.body20: ; preds = %if.end38, %while.cond13.preheader while.body20: ; preds = %if.end38, %while.cond13.preheader
%addr.0100 = phi i32 [ undef, %if.end38 ], [ %c, %while.cond13.preheader ] %addr.0100 = phi i32 [ undef, %if.end38 ], [ %c, %while.cond13.preheader ]
%cond = select i1 undef, i32 %addr.0100, i32 undef %cond = select i1 undef, i32 %addr.0100, i32 undef
br i1 undef, label %while.body20.if.end38_crit_edge, label %if.then32 br i1 %c3, label %while.body20.if.end38_crit_edge, label %if.then32
while.body20.if.end38_crit_edge: ; preds = %while.body20 while.body20.if.end38_crit_edge: ; preds = %while.body20
%conv39.pre = and i32 %cond, 65535 %conv39.pre = and i32 %cond, 65535
br label %if.end38 br label %if.end38
if.then32: ; preds = %while.body20 if.then32: ; preds = %while.body20
%conv33 = and i32 %cond, 65535 %conv33 = and i32 %cond, 65535
%.pre = load ptr, ptr %ptr, align 4, !tbaa !1 %.pre = load ptr, ptr %ptr, align 4, !tbaa !1
br label %if.end38 br label %if.end38
if.end38: ; preds = %if.then32, %while.body20.if.end38_crit_edge if.end38: ; preds = %if.then32, %while.body20.if.end38_crit_edge
%conv39.pre-phi = phi i32 [ %conv39.pre, %while.body20.if.end38_crit_edge ], [ %conv33, %if.then32 ] %conv39.pre-phi = phi i32 [ %conv39.pre, %while.body20.if.end38_crit_edge ], [ %conv33, %if.then32 ]
%0 = phi ptr [ undef, %while.body20.if.end38_crit_edge ], [ %.pre, %if.then32 ] %0 = phi ptr [ undef, %while.body20.if.end38_crit_edge ], [ %.pre, %if.then32 ]
%add = add i32 %conv39.pre-phi, 0 %add = add i32 %conv39.pre-phi, 0
%call52 = tail call ptr @foo(ptr %0, ptr %d, i32 %e) #1 %call52 = tail call ptr @foo(ptr %0, ptr %d, i32 %e) #1
br i1 undef, label %while.body20, label %return br i1 %c4, label %while.body20, label %return
return: ; preds = %if.end38, %while.cond13.preheader, %entry return: ; preds = %if.end38, %while.cond13.preheader, %entry
%retval.0 = phi i32 [ 0, %entry ], [ 0, %while.cond13.preheader ], [ %add, %if.end38 ] %retval.0 = phi i32 [ 0, %entry ], [ 0, %while.cond13.preheader ], [ %add, %if.end38 ]
ret i32 %retval.0 ret i32 %retval.0
} }
attributes #0 = { nounwind readonly } attributes #0 = { nounwind readonly }
attributes #1 = { nounwind } attributes #1 = { nounwind }
!1 = !{!2, !2, i64 0} !1 = !{!2, !2, i64 0}
!2 = !{!"any pointer", !3, i64 0} !2 = !{!"any pointer", !3, i64 0}
!3 = !{!"omnipotent char", !4, i64 0} !3 = !{!"omnipotent char", !4, i64 0}
!4 = !{!"Simple C/C++ TBAA"} !4 = !{!"Simple C/C++ TBAA"}

llvm/test/CodeGen/Hexagon/bit-visit-flowq.ll

; RUN: llc -march=hexagon < %s | FileCheck %s ; RUN: llc -march=hexagon < %s | FileCheck %s
; REQUIRES: asserts ; REQUIRES: asserts
; Check that we don't crash. ; Check that we don't crash.
; CHECK: call bar ; CHECK: call bar
target triple = "hexagon" target triple = "hexagon"
@debug = external hidden unnamed_addr global i1, align 4 @debug = external hidden unnamed_addr global i1, align 4
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @foo(i1 %cond) local_unnamed_addr #0 { define void @foo(i1 %cond, i1 %c0) local_unnamed_addr #0 {
entry: entry:
br label %if.end5 br label %if.end5
if.end5: ; preds = %entry if.end5: ; preds = %entry
br i1 undef, label %if.then12, label %if.end13 br i1 %c0, label %if.then12, label %if.end13
if.then12: ; preds = %if.end5 if.then12: ; preds = %if.end5
ret void ret void
if.end13: ; preds = %if.end5 if.end13: ; preds = %if.end5
br label %for.cond br label %for.cond
for.cond: ; preds = %if.end13 for.cond: ; preds = %if.end13
Show All 22 Lines

llvm/test/CodeGen/Hexagon/block-ranges-nodef.ll

; RUN: llc -march=hexagon < %s ; RUN: llc -march=hexagon < %s
; REQUIRES: asserts ; REQUIRES: asserts
target triple = "hexagon" target triple = "hexagon"
declare void @foo() #0 declare void @foo() #0
define hidden fastcc void @fred(i32 %a, i64 %b, i64 %c) unnamed_addr #1 { define hidden fastcc void @fred(i32 %a, i64 %b, i64 %c, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4) unnamed_addr #1 {
entry: entry:
%cmp17 = icmp ne i64 %c, 0 %cmp17 = icmp ne i64 %c, 0
%conv19 = zext i1 %cmp17 to i64 %conv19 = zext i1 %cmp17 to i64
%or = or i64 %conv19, %b %or = or i64 %conv19, %b
store i64 %or, ptr undef, align 8 store i64 %or, ptr undef, align 8
br i1 undef, label %if.then44, label %if.end96 br i1 %c0, label %if.then44, label %if.end96
if.then44: ; preds = %entry if.then44: ; preds = %entry
br i1 undef, label %overflow, label %lor.lhs.false br i1 %c1, label %overflow, label %lor.lhs.false
lor.lhs.false: ; preds = %if.then44 lor.lhs.false: ; preds = %if.then44
br i1 undef, label %overflow, label %if.end52 br i1 %c2, label %overflow, label %if.end52
if.end52: ; preds = %lor.lhs.false if.end52: ; preds = %lor.lhs.false
br i1 undef, label %if.then55, label %if.end96 br i1 %c3, label %if.then55, label %if.end96
if.then55: ; preds = %if.end52 if.then55: ; preds = %if.end52
%cmp60 = icmp slt i32 %a, 0 %cmp60 = icmp slt i32 %a, 0
%or.cond = or i1 %cmp60, false %or.cond = or i1 %cmp60, false
%cmp63 = icmp ule i64 %or, undef %cmp63 = icmp ule i64 %or, undef
%.cmp63 = or i1 %cmp63, %or.cond %.cmp63 = or i1 %cmp63, %or.cond
call void @foo() call void @foo()
%or.cond299 = and i1 %.cmp63, undef %or.cond299 = and i1 %.cmp63, undef
br i1 %or.cond299, label %if.then72, label %if.end73 br i1 %or.cond299, label %if.then72, label %if.end73
if.then72: ; preds = %if.then55 if.then72: ; preds = %if.then55
unreachable unreachable
if.end73: ; preds = %if.then55 if.end73: ; preds = %if.then55
unreachable unreachable
if.end96: ; preds = %if.end52, %entry if.end96: ; preds = %if.end52, %entry
br i1 undef, label %if.end102, label %if.then98 br i1 %c4, label %if.end102, label %if.then98
if.then98: ; preds = %if.end96 if.then98: ; preds = %if.end96
br label %if.end102 br label %if.end102
if.end102: ; preds = %if.then98, %if.end96 if.end102: ; preds = %if.then98, %if.end96
unreachable unreachable
overflow: ; preds = %lor.lhs.false, %if.then44 overflow: ; preds = %lor.lhs.false, %if.then44
ret void ret void
} }
attributes #0 = { noinline norecurse nounwind } attributes #0 = { noinline norecurse nounwind }
attributes #1 = { noinline nounwind } attributes #1 = { noinline nounwind }

llvm/test/CodeGen/Hexagon/branchfolder-keep-impdef.ll

; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s
; ;
; Check that the testcase compiles successfully. Expect that if-conversion ; Check that the testcase compiles successfully. Expect that if-conversion
; took place. ; took place.
; CHECK-LABEL: fred: ; CHECK-LABEL: fred:
; CHECK: if (!p0) r{{[0-9]+}} = memw(r{{[0-9]+}}+#0) ; CHECK: if (!p0) r{{[0-9]+}} = memw(r{{[0-9]+}}+#0)
target triple = "hexagon" target triple = "hexagon"
define void @fred(i32 %p0) local_unnamed_addr align 2 { define void @fred(i32 %p0, i1 %c0) local_unnamed_addr align 2 {
b0: b0:
br i1 undef, label %b1, label %b2 br i1 %c0, label %b1, label %b2
b1: ; preds = %b0 b1: ; preds = %b0
%t0 = load ptr, ptr undef, align 4 %t0 = load ptr, ptr undef, align 4
br label %b2 br label %b2
b2: ; preds = %b1, %b0 b2: ; preds = %b1, %b0
%t1 = phi ptr [ %t0, %b1 ], [ undef, %b0 ] %t1 = phi ptr [ %t0, %b1 ], [ undef, %b0 ]
%t2 = getelementptr inbounds i8, ptr %t1, i32 %p0 %t2 = getelementptr inbounds i8, ptr %t1, i32 %p0
Show All 9 Lines

llvm/test/CodeGen/Hexagon/bug17386.ll

; RUN: llc -march=hexagon -O2 < %s ; RUN: llc -march=hexagon -O2 < %s
; REQUIRES: asserts ; REQUIRES: asserts
target triple = "hexagon" target triple = "hexagon"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0(ptr %a0, ...) #0 { define void @f0(ptr %a0, ..., i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8) #0 {
b0: b0:
br i1 undef, label %b1, label %b2 br i1 %c0, label %b1, label %b2
b1: ; preds = %b0 b1: ; preds = %b0
unreachable unreachable
b2: ; preds = %b2, %b0 b2: ; preds = %b2, %b0
br i1 undef, label %b2, label %b3 br i1 %c1, label %b2, label %b3
b3: ; preds = %b2 b3: ; preds = %b2
br i1 undef, label %b4, label %b5 br i1 %c2, label %b4, label %b5
b4: ; preds = %b3 b4: ; preds = %b3
br label %b5 br label %b5
b5: ; preds = %b4, %b3 b5: ; preds = %b4, %b3
br label %b6 br label %b6
b6: ; preds = %b12, %b5 b6: ; preds = %b12, %b5
br i1 undef, label %b9, label %b7 br i1 %c3, label %b9, label %b7
b7: ; preds = %b6 b7: ; preds = %b6
%v0 = load i8, ptr undef, align 1, !tbaa !0 %v0 = load i8, ptr undef, align 1, !tbaa !0
%v1 = zext i8 %v0 to i32 %v1 = zext i8 %v0 to i32
br i1 undef, label %b9, label %b8 br i1 %c4, label %b9, label %b8
b8: ; preds = %b7 b8: ; preds = %b7
br i1 undef, label %b9, label %b10 br i1 %c5, label %b9, label %b10
b9: ; preds = %b8, %b7, %b6 b9: ; preds = %b8, %b7, %b6
br label %b10 br label %b10
b10: ; preds = %b9, %b8 b10: ; preds = %b9, %b8
%v2 = phi i32 [ undef, %b9 ], [ %v1, %b8 ] %v2 = phi i32 [ undef, %b9 ], [ %v1, %b8 ]
%v3 = icmp eq i32 %v2, 37 %v3 = icmp eq i32 %v2, 37
%v4 = sext i1 %v3 to i32 %v4 = sext i1 %v3 to i32
%v5 = icmp slt i32 0, 1 %v5 = icmp slt i32 0, 1
br i1 %v5, label %b12, label %b11 br i1 %v5, label %b12, label %b11
b11: ; preds = %b10 b11: ; preds = %b10
unreachable unreachable
b12: ; preds = %b10 b12: ; preds = %b10
br i1 undef, label %b13, label %b6 br i1 %c6, label %b13, label %b6
b13: ; preds = %b12 b13: ; preds = %b12
br label %b14 br label %b14
b14: ; preds = %b15, %b13 b14: ; preds = %b15, %b13
br i1 undef, label %b16, label %b15 br i1 %c7, label %b16, label %b15
b15: ; preds = %b14 b15: ; preds = %b14
br i1 undef, label %b14, label %b16 br i1 %c8, label %b14, label %b16
b16: ; preds = %b15, %b14 b16: ; preds = %b15, %b14
br label %b17 br label %b17
b17: ; preds = %b18, %b16 b17: ; preds = %b18, %b16
%v6 = phi ptr [ undef, %b16 ], [ %v7, %b18 ] %v6 = phi ptr [ undef, %b16 ], [ %v7, %b18 ]
%v7 = getelementptr inbounds i8, ptr %v6, i32 1 %v7 = getelementptr inbounds i8, ptr %v6, i32 1
%v8 = load i8, ptr %v7, align 1, !tbaa !0 %v8 = load i8, ptr %v7, align 1, !tbaa !0
Show All 21 Lines

llvm/test/CodeGen/Hexagon/bug31839.ll

; RUN: llc -march=hexagon < %s ; RUN: llc -march=hexagon < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Check for successful compilation. ; Check for successful compilation.
define ptr @f0(i32 %a0, i32 %a1) { define ptr @f0(i32 %a0, i32 %a1, i1 %c0) {
b0: b0:
%v0 = call noalias ptr @f1(i32 undef, i32 undef) %v0 = call noalias ptr @f1(i32 undef, i32 undef)
br i1 undef, label %b2, label %b1 br i1 %c0, label %b2, label %b1
b1: ; preds = %b0 b1: ; preds = %b0
%v1 = ptrtoint ptr %v0 to i32 %v1 = ptrtoint ptr %v0 to i32
store volatile i32 %v1, ptr %v0, align 4 store volatile i32 %v1, ptr %v0, align 4
%v3 = getelementptr inbounds i8, ptr %v0, i32 4 %v3 = getelementptr inbounds i8, ptr %v0, i32 4
store ptr %v0, ptr %v3, align 4 store ptr %v0, ptr %v3, align 4
%v5 = getelementptr inbounds i8, ptr %v0, i32 16 %v5 = getelementptr inbounds i8, ptr %v0, i32 16
br label %b2 br label %b2
b2: ; preds = %b1, %b0 b2: ; preds = %b1, %b0
%v6 = phi ptr [ %v5, %b1 ], [ null, %b0 ] %v6 = phi ptr [ %v5, %b1 ], [ null, %b0 ]
ret ptr %v6 ret ptr %v6
} }
declare noalias ptr @f1(i32, i32) local_unnamed_addr declare noalias ptr @f1(i32, i32) local_unnamed_addr

llvm/test/CodeGen/Hexagon/call-ret-i1.ll

; RUN: llc -march=hexagon < %s ; RUN: llc -march=hexagon < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Test that the compiler does not assert because the DAG is not correct. ; Test that the compiler does not assert because the DAG is not correct.
; CHECK: call foo ; CHECK: call foo
%returntype = type { i1, i32 } %returntype = type { i1, i32 }
define i32 @test(ptr %a0, ptr %a1, ptr %a2) #0 { define i32 @test(ptr %a0, ptr %a1, ptr %a2, i1 %c0) #0 {
b3: b3:
br i1 undef, label %b6, label %b4 br i1 %c0, label %b6, label %b4
b4: ; preds = %b3 b4: ; preds = %b3
%v5 = call %returntype @foo(ptr nonnull undef, ptr %a2, ptr %a0) #0 %v5 = call %returntype @foo(ptr nonnull undef, ptr %a2, ptr %a0) #0
ret i32 1 ret i32 1
b6: ; preds = %b3 b6: ; preds = %b3
unreachable unreachable
} }
declare %returntype @foo(ptr, ptr, ptr) #0 declare %returntype @foo(ptr, ptr, ptr) #0
attributes #0 = { nounwind } attributes #0 = { nounwind }

llvm/test/CodeGen/Hexagon/callR_noreturn.ll

; RUN: llc -march=hexagon < %s | FileCheck %s ; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK: callr {{r[0-9]+}} ; CHECK: callr {{r[0-9]+}}
%s.0 = type { [1 x %s.1], [4 x ptr] } %s.0 = type { [1 x %s.1], [4 x ptr] }
%s.1 = type { [1 x %s.2], i32, [4 x i8] } %s.1 = type { [1 x %s.2], i32, [4 x i8] }
%s.2 = type { [16 x i32] } %s.2 = type { [16 x i32] }
define hidden void @f0(ptr %a0) #0 { define hidden void @f0(ptr %a0, i1 %c0) #0 {
b0: b0:
br i1 undef, label %b2, label %b1 br i1 %c0, label %b2, label %b1
b1: ; preds = %b0 b1: ; preds = %b0
ret void ret void
b2: ; preds = %b0 b2: ; preds = %b0
call void %a0(ptr null) #1 call void %a0(ptr null) #1
unreachable unreachable
} }
attributes #0 = { noreturn nounwind } attributes #0 = { noreturn nounwind }
attributes #1 = { noreturn } attributes #1 = { noreturn }

llvm/test/CodeGen/Hexagon/cfgopt-fall-through.ll

; RUN: llc -march=hexagon -verify-machineinstrs -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s ; RUN: llc -march=hexagon -verify-machineinstrs -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s
; REQUIRES: asserts ; REQUIRES: asserts
; Check for some sane output. This test used to crash. ; Check for some sane output. This test used to crash.
; CHECK: jumpr r31 ; CHECK: jumpr r31
define i32 @fred(i32 %a0, i8 zeroext %a1) local_unnamed_addr #0 { define i32 @fred(i32 %a0, i8 zeroext %a1, i1 %c0, i1 %c1, i1 %c2, i1 %c3) local_unnamed_addr #0 {
b2: b2:
br i1 undef, label %b4, label %b3 br i1 %c0, label %b4, label %b3
b3: ; preds = %b2 b3: ; preds = %b2
unreachable unreachable
b4: ; preds = %b2 b4: ; preds = %b2
br i1 undef, label %b19, label %b5 br i1 %c1, label %b19, label %b5
b5: ; preds = %b4 b5: ; preds = %b4
br i1 undef, label %b6, label %b12 br i1 %c2, label %b6, label %b12
b6: ; preds = %b5 b6: ; preds = %b5
switch i8 %a1, label %b17 [ switch i8 %a1, label %b17 [
i8 2, label %b7 i8 2, label %b7
i8 5, label %b7 i8 5, label %b7
i8 1, label %b7 i8 1, label %b7
i8 3, label %b8 i8 3, label %b8
] ]
b7: ; preds = %b6, %b6, %b6 b7: ; preds = %b6, %b6, %b6
unreachable unreachable
b8: ; preds = %b6 b8: ; preds = %b6
br i1 undef, label %b11, label %b9 br i1 %c3, label %b11, label %b9
b9: ; preds = %b8 b9: ; preds = %b8
%v10 = or i32 undef, 0 %v10 = or i32 undef, 0
br label %b15 br label %b15
b11: ; preds = %b8 b11: ; preds = %b8
unreachable unreachable
Show All 30 Lines

llvm/test/CodeGen/Hexagon/cmp-extend.ll

; RUN: llc -march=hexagon < %s | FileCheck %s ; RUN: llc -march=hexagon < %s | FileCheck %s
%struct.RESULTS_S.A = type { i16, i16, i16, [4 x ptr], i32, i32, i32, ptr, %struct.MAT_PARAMS_S.D, i16, i16, i16, i16, i16, %struct.CORE_PORTABLE_S.E } %struct.RESULTS_S.A = type { i16, i16, i16, [4 x ptr], i32, i32, i32, ptr, %struct.MAT_PARAMS_S.D, i16, i16, i16, i16, i16, %struct.CORE_PORTABLE_S.E }
%struct.list_head_s.B = type { ptr, ptr } %struct.list_head_s.B = type { ptr, ptr }
%struct.list_data_s.C = type { i16, i16 } %struct.list_data_s.C = type { i16, i16 }
%struct.MAT_PARAMS_S.D = type { i32, ptr, ptr, ptr } %struct.MAT_PARAMS_S.D = type { i32, ptr, ptr, ptr }
%struct.CORE_PORTABLE_S.E = type { i8 } %struct.CORE_PORTABLE_S.E = type { i8 }
; Test that we don't generate a zero extend in this case. Instead we generate ; Test that we don't generate a zero extend in this case. Instead we generate
; a single sign extend instead of two zero extends. ; a single sign extend instead of two zero extends.
; CHECK-NOT: zxth ; CHECK-NOT: zxth
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @core_bench_list(ptr %res) #0 { define void @core_bench_list(ptr %res, i1 %c0) #0 {
entry: entry:
%seed3 = getelementptr inbounds %struct.RESULTS_S.A, ptr %res, i32 0, i32 2 %seed3 = getelementptr inbounds %struct.RESULTS_S.A, ptr %res, i32 0, i32 2
%0 = load i16, ptr %seed3, align 2 %0 = load i16, ptr %seed3, align 2
%cmp364 = icmp sgt i16 %0, 0 %cmp364 = icmp sgt i16 %0, 0
br i1 %cmp364, label %for.body, label %while.body19.i160 br i1 %cmp364, label %for.body, label %while.body19.i160
for.body: for.body:
%i.0370 = phi i16 [ %inc50, %if.then ], [ 0, %entry ] %i.0370 = phi i16 [ %inc50, %if.then ], [ 0, %entry ]
br i1 undef, label %if.then, label %while.body.i273 br i1 %c0, label %if.then, label %while.body.i273
while.body.i273: while.body.i273:
%tobool.i272 = icmp eq ptr undef, null %tobool.i272 = icmp eq ptr undef, null
br i1 %tobool.i272, label %if.then, label %while.body.i273 br i1 %tobool.i272, label %if.then, label %while.body.i273
if.then: if.then:
%inc50 = add i16 %i.0370, 1 %inc50 = add i16 %i.0370, 1
%exitcond = icmp eq i16 %inc50, %0 %exitcond = icmp eq i16 %inc50, %0
br i1 %exitcond, label %while.body19.i160, label %for.body br i1 %exitcond, label %while.body19.i160, label %for.body
while.body19.i160: while.body19.i160:
br label %while.body19.i160 br label %while.body19.i160
} }
attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }

llvm/test/CodeGen/Hexagon/const-pool-tf.ll

; RUN: opt -relocation-model pic -march=hexagon -mcpu=hexagonv60 -O2 -S < %s | llc -march=hexagon -mcpu=hexagonv60 -relocation-model pic ; RUN: opt -relocation-model pic -march=hexagon -mcpu=hexagonv60 -O2 -S < %s | llc -march=hexagon -mcpu=hexagonv60 -relocation-model pic
; CHECK: jumpr ; CHECK: jumpr
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon-unknown--elf" target triple = "hexagon-unknown--elf"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @hex_h.s0.__outermost(i32 %h.stride.114) #0 { define void @hex_h.s0.__outermost(i32 %h.stride.114, i1 %c0) #0 {
entry: entry:
br i1 undef, label %"for h.s0.y.preheader", label %call_destructor.exit, !prof !1 br i1 %c0, label %"for h.s0.y.preheader", label %call_destructor.exit, !prof !1
call_destructor.exit: ; preds = %entry call_destructor.exit: ; preds = %entry
ret void ret void
"for h.s0.y.preheader": ; preds = %entry "for h.s0.y.preheader": ; preds = %entry
%tmp22.us = mul i32 undef, %h.stride.114 %tmp22.us = mul i32 undef, %h.stride.114
br label %"for h.s0.x.x.us" br label %"for h.s0.x.x.us"
Show All 21 Lines

llvm/test/CodeGen/Hexagon/convert-to-dot-old.ll

; RUN: llc -march=hexagon -mcpu=hexagonv55 -filetype=obj -o /dev/null ; RUN: llc -march=hexagon -mcpu=hexagonv55 -filetype=obj -o /dev/null
; REQUIRES: asserts ; REQUIRES: asserts
; There should be no output (nothing on stderr). ; There should be no output (nothing on stderr).
; Due to a bug in converting a dot-new branch into a dot-old one, opcodes ; Due to a bug in converting a dot-new branch into a dot-old one, opcodes
; with branch prediction bits were selected even if the architecture did ; with branch prediction bits were selected even if the architecture did
; not support them. On V55-, the dot-old branch opcodes are J2_jumpt and ; not support them. On V55-, the dot-old branch opcodes are J2_jumpt and
; J2_jumpf (and a pair of J2_jumpr*), whereas J2_jumptpt could have been ; J2_jumpf (and a pair of J2_jumpr*), whereas J2_jumptpt could have been
; a result of the conversion to dot-old. This would fail a verification ; a result of the conversion to dot-old. This would fail a verification
; check in the MC code emitter, so make sure it does not happen. ; check in the MC code emitter, so make sure it does not happen.
target triple = "hexagon" target triple = "hexagon"
define void @fred(ptr nocapture %a0, ptr nocapture %a1, ptr nocapture %a2, i16 signext %a3, ptr %a4, i16 signext %a5, i16 signext %a6, i16 signext %a7, i32 %a8, i16 signext %a9, i16 signext %a10) local_unnamed_addr #0 { define void @fred(ptr nocapture %a0, ptr nocapture %a1, ptr nocapture %a2, i16 signext %a3, ptr %a4, i16 signext %a5, i16 signext %a6, i16 signext %a7, i32 %a8, i16 signext %a9, i16 signext %a10, i1 %c0, i1 %c1) local_unnamed_addr #0 {
b11: b11:
%v12 = sext i16 %a5 to i32 %v12 = sext i16 %a5 to i32
%v13 = tail call i32 @llvm.hexagon.A2.sxth(i32 %v12) %v13 = tail call i32 @llvm.hexagon.A2.sxth(i32 %v12)
%v14 = tail call i32 @llvm.hexagon.A2.sxth(i32 2) %v14 = tail call i32 @llvm.hexagon.A2.sxth(i32 2)
%v15 = tail call i32 @llvm.hexagon.A2.sxth(i32 undef) %v15 = tail call i32 @llvm.hexagon.A2.sxth(i32 undef)
%v16 = tail call i32 @llvm.hexagon.A2.sath(i32 undef) %v16 = tail call i32 @llvm.hexagon.A2.sath(i32 undef)
%v17 = tail call i32 @llvm.hexagon.A2.sxth(i32 %v16) %v17 = tail call i32 @llvm.hexagon.A2.sxth(i32 %v16)
%v18 = tail call i32 @llvm.hexagon.A2.aslh(i32 undef) %v18 = tail call i32 @llvm.hexagon.A2.aslh(i32 undef)
Show All 38 Linesb11:
%v52 = call i32 @llvm.hexagon.A2.sxth(i32 %v51) %v52 = call i32 @llvm.hexagon.A2.sxth(i32 %v51)
%v53 = call i32 @llvm.hexagon.A2.add(i32 undef, i32 %v52) %v53 = call i32 @llvm.hexagon.A2.add(i32 undef, i32 %v52)
%v54 = call i32 @llvm.hexagon.A2.sath(i32 %v53) %v54 = call i32 @llvm.hexagon.A2.sath(i32 %v53)
%v55 = trunc i32 %v54 to i16 %v55 = trunc i32 %v54 to i16
store i16 %v55, ptr %a1, align 2 store i16 %v55, ptr %a1, align 2
store i16 %a7, ptr %a2, align 2 store i16 %a7, ptr %a2, align 2
%v56 = sext i16 %a9 to i32 %v56 = sext i16 %a9 to i32
%v57 = call i32 @llvm.hexagon.A2.sxth(i32 %v56) %v57 = call i32 @llvm.hexagon.A2.sxth(i32 %v56)
br i1 undef, label %b58, label %b62 br i1 %c0, label %b58, label %b62
b58: ; preds = %b11 b58: ; preds = %b11
%v59 = call i32 @llvm.hexagon.A2.add(i32 %v57, i32 %v52) %v59 = call i32 @llvm.hexagon.A2.add(i32 %v57, i32 %v52)
%v60 = call i32 @llvm.hexagon.A2.sath(i32 %v59) %v60 = call i32 @llvm.hexagon.A2.sath(i32 %v59)
%v61 = trunc i32 %v60 to i16 %v61 = trunc i32 %v60 to i16
store i16 %v61, ptr %a1, align 2 store i16 %v61, ptr %a1, align 2
br label %b63 br label %b63
b62: ; preds = %b11 b62: ; preds = %b11
br label %b63 br label %b63
b63: ; preds = %b62, %b58 b63: ; preds = %b62, %b58
%v64 = phi i16 [ undef, %b58 ], [ %a9, %b62 ] %v64 = phi i16 [ undef, %b58 ], [ %a9, %b62 ]
%v65 = icmp slt i16 undef, %v64 %v65 = icmp slt i16 undef, %v64
br i1 %v65, label %b66, label %b67 br i1 %v65, label %b66, label %b67
b66: ; preds = %b63 b66: ; preds = %b63
br i1 undef, label %b67, label %b68 br i1 %c1, label %b67, label %b68
b67: ; preds = %b66, %b63 b67: ; preds = %b66, %b63
store i16 0, ptr %a2, align 2 store i16 0, ptr %a2, align 2
br label %b68 br label %b68
b68: ; preds = %b67, %b66 b68: ; preds = %b67, %b66
ret void ret void
} }
Show All 15 Lines

llvm/test/CodeGen/Hexagon/csr-func-usedef.ll

; RUN: llc -march=hexagon < %s ; RUN: llc -march=hexagon < %s
; REQUIRES: asserts ; REQUIRES: asserts
target triple = "hexagon" target triple = "hexagon"
declare ptr @llvm.hexagon.circ.ldb(ptr, ptr, i32, i32) #1 declare ptr @llvm.hexagon.circ.ldb(ptr, ptr, i32, i32) #1
declare ptr @llvm.hexagon.circ.stb(ptr, i32, i32, i32) #1 declare ptr @llvm.hexagon.circ.stb(ptr, i32, i32, i32) #1
define zeroext i8 @circular_loop_test10(ptr %A, ptr %B, i32 %x, i32 %y, i32 %z, i32 %w) #0 { define zeroext i8 @circular_loop_test10(ptr %A, ptr %B, i32 %x, i32 %y, i32 %z, i32 %w, i1 %c0, i1 %c1) #0 {
entry: entry:
%element_load0 = alloca i8, align 1 %element_load0 = alloca i8, align 1
%element_load2 = alloca i8, align 1 %element_load2 = alloca i8, align 1
%element_load3 = alloca i8, align 1 %element_load3 = alloca i8, align 1
%element_load5 = alloca i8, align 1 %element_load5 = alloca i8, align 1
%or = or i32 %x, 100663296 %or = or i32 %x, 100663296
%or5 = or i32 %z, 100663296 %or5 = or i32 %z, 100663296
%or7 = or i32 %w, 100663296 %or7 = or i32 %w, 100663296
Show All 29 Linesfor.body: ; preds = %for.body, %entry
%add14 = add nuw nsw i32 %add12, %conv11 %add14 = add nuw nsw i32 %add12, %conv11
%add16 = add nuw nsw i32 %add14, %conv13 %add16 = add nuw nsw i32 %add14, %conv13
%add18 = add nuw nsw i32 %add16, %conv15 %add18 = add nuw nsw i32 %add16, %conv15
%exitcond84 = icmp eq i32 undef, 200 %exitcond84 = icmp eq i32 undef, 200
br i1 %exitcond84, label %for.body23, label %for.body br i1 %exitcond84, label %for.body23, label %for.body
for.body23: ; preds = %for.body23, %for.body for.body23: ; preds = %for.body23, %for.body
%11 = call ptr @llvm.hexagon.circ.stb(ptr undef, i32 undef, i32 %or, i32 3) %11 = call ptr @llvm.hexagon.circ.stb(ptr undef, i32 undef, i32 %or, i32 3)
br i1 undef, label %for.body34, label %for.body23 br i1 %c0, label %for.body34, label %for.body23
for.body34: ; preds = %for.body34, %for.body23 for.body34: ; preds = %for.body34, %for.body23
%element_load.173 = phi i32 [ %add38, %for.body34 ], [ %add18, %for.body23 ] %element_load.173 = phi i32 [ %add38, %for.body34 ], [ %add18, %for.body23 ]
%12 = load i8, ptr %B, align 1 %12 = load i8, ptr %B, align 1
%conv36 = zext i8 %12 to i32 %conv36 = zext i8 %12 to i32
%conv37 = and i32 %element_load.173, 255 %conv37 = and i32 %element_load.173, 255
%add38 = add nuw nsw i32 %conv36, %conv37 %add38 = add nuw nsw i32 %conv36, %conv37
br i1 undef, label %for.end42, label %for.body34 br i1 %c1, label %for.end42, label %for.body34
for.end42: ; preds = %for.body34 for.end42: ; preds = %for.body34
%conv39 = trunc i32 %add38 to i8 %conv39 = trunc i32 %add38 to i8
ret i8 %conv39 ret i8 %conv39
} }
attributes #0 = { nounwind optsize } attributes #0 = { nounwind optsize }
attributes #1 = { argmemonly nounwind } attributes #1 = { argmemonly nounwind }

llvm/test/CodeGen/Hexagon/dag-indexed.ll

; RUN: llc -march=hexagon < %s ; RUN: llc -march=hexagon < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Test that the DAG combiner doesn't assert because it attempts to replace ; Test that the DAG combiner doesn't assert because it attempts to replace
; the chain of a post-increment store based upon alias information. The code ; the chain of a post-increment store based upon alias information. The code
; in DAGCombiner is unable to convert indexed stores. ; in DAGCombiner is unable to convert indexed stores.
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0(i32 %a0, ptr %a1, ptr %a2) #0 { define void @f0(i32 %a0, ptr %a1, ptr %a2, i1 %c0, i1 %c1) #0 {
b0: b0:
switch i32 %a0, label %b5 [ switch i32 %a0, label %b5 [
i32 67830273, label %b1 i32 67830273, label %b1
i32 67502595, label %b3 i32 67502595, label %b3
] ]
b1: ; preds = %b0 b1: ; preds = %b0
br i1 undef, label %b2, label %b5 br i1 %c0, label %b2, label %b5
b2: ; preds = %b1 b2: ; preds = %b1
br label %b5 br label %b5
b3: ; preds = %b0 b3: ; preds = %b0
br i1 undef, label %b4, label %b5 br i1 %c1, label %b4, label %b5
b4: ; preds = %b3 b4: ; preds = %b3
store i32 0, ptr %a2, align 1, !tbaa !0 store i32 0, ptr %a2, align 1, !tbaa !0
%v1 = getelementptr inbounds i8, ptr %a1, i32 4 %v1 = getelementptr inbounds i8, ptr %a1, i32 4
%v3 = load i32, ptr %v1, align 4, !tbaa !5 %v3 = load i32, ptr %v1, align 4, !tbaa !5
%v4 = getelementptr inbounds i8, ptr %a2, i32 4 %v4 = getelementptr inbounds i8, ptr %a2, i32 4
store i32 %v3, ptr %v4, align 1, !tbaa !5 store i32 %v3, ptr %v4, align 1, !tbaa !5
br label %b5 br label %b5
Show All 13 Lines

llvm/test/CodeGen/Hexagon/def-undef-deps.ll

Show All 19 Lines
@g0 = external constant %0, align 1 @g0 = external constant %0, align 1
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare i32 @llvm.hexagon.M2.mpy.up(i32, i32) #1 declare i32 @llvm.hexagon.M2.mpy.up(i32, i32) #1
declare void @f0(ptr, i32, i32, i32, i32, i32) declare void @f0(ptr, i32, i32, i32, i32, i32)
define void @f1(i8 zeroext %a0, ptr nocapture %a1, i8 zeroext %a2, i8 zeroext %a3) #0 { define void @f1(i8 zeroext %a0, ptr nocapture %a1, i8 zeroext %a2, i8 zeroext %a3, i1 %c0, i1 %c1, i1 %c2) #0 {
b0: b0:
%v0 = getelementptr inbounds %1, ptr %a1, i32 0, i32 1, i32 9 %v0 = getelementptr inbounds %1, ptr %a1, i32 0, i32 1, i32 9
%v1 = load i8, ptr %v0, align 1 %v1 = load i8, ptr %v0, align 1
%v2 = zext i8 %v1 to i32 %v2 = zext i8 %v1 to i32
%v3 = getelementptr inbounds %1, ptr %a1, i32 0, i32 2, i32 %v2 %v3 = getelementptr inbounds %1, ptr %a1, i32 0, i32 2, i32 %v2
%v4 = tail call ptr @f2(i32 undef, i8 zeroext 0) %v4 = tail call ptr @f2(i32 undef, i8 zeroext 0)
br i1 undef, label %b1, label %b5 br i1 %c0, label %b1, label %b5
b1: ; preds = %b0 b1: ; preds = %b0
%v5 = tail call i32 @llvm.hexagon.M2.mpy.up(i32 undef, i32 undef) %v5 = tail call i32 @llvm.hexagon.M2.mpy.up(i32 undef, i32 undef)
%v6 = tail call i32 @llvm.hexagon.M2.mpy.up(i32 undef, i32 undef) %v6 = tail call i32 @llvm.hexagon.M2.mpy.up(i32 undef, i32 undef)
%v7 = zext i32 %v5 to i64 %v7 = zext i32 %v5 to i64
%v8 = zext i32 %v6 to i64 %v8 = zext i32 %v6 to i64
%v9 = add nuw nsw i64 %v8, %v7 %v9 = add nuw nsw i64 %v8, %v7
%v10 = lshr i64 %v9, 5 %v10 = lshr i64 %v9, 5
%v11 = trunc i64 %v10 to i32 %v11 = trunc i64 %v10 to i32
store i32 %v11, ptr undef, align 4 store i32 %v11, ptr undef, align 4
br i1 undef, label %b3, label %b2 br i1 %c1, label %b3, label %b2
b2: ; preds = %b1 b2: ; preds = %b1
store i32 0, ptr %v3, align 4 store i32 0, ptr %v3, align 4
tail call void @f0(ptr @g0, i32 undef, i32 0, i32 undef, i32 undef, i32 undef) tail call void @f0(ptr @g0, i32 undef, i32 0, i32 undef, i32 undef, i32 undef)
br label %b4 br label %b4
b3: ; preds = %b1 b3: ; preds = %b1
br label %b4 br label %b4
b4: ; preds = %b3, %b2 b4: ; preds = %b3, %b2
unreachable unreachable
b5: ; preds = %b0 b5: ; preds = %b0
br i1 undef, label %b6, label %b7 br i1 %c2, label %b6, label %b7
b6: ; preds = %b5 b6: ; preds = %b5
unreachable unreachable
b7: ; preds = %b5 b7: ; preds = %b5
unreachable unreachable
} }
declare ptr @f2(i32, i8 zeroext) declare ptr @f2(i32, i8 zeroext)
attributes #0 = { nounwind "target-cpu"="hexagonv55" } attributes #0 = { nounwind "target-cpu"="hexagonv55" }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }

llvm/test/CodeGen/Hexagon/early-if-vecpred.ll

; RUN: llc -march=hexagon < %s | FileCheck %s ; RUN: llc -march=hexagon < %s | FileCheck %s
; REQUIRES: asserts ; REQUIRES: asserts
; Hexagon early if-conversion used to crash on this testcase due to not ; Hexagon early if-conversion used to crash on this testcase due to not
; recognizing vector predicate registers. ; recognizing vector predicate registers.
target triple = "hexagon" target triple = "hexagon"
; Check that the early if-conversion has not happened. ; Check that the early if-conversion has not happened.
; CHECK-LABEL: fred ; CHECK-LABEL: fred
; CHECK: q{{[0-3]}} = not ; CHECK: q{{[0-3]}} = not
; CHECK: LBB ; CHECK: LBB
; CHECK: if (q{{[0-3]}}) vmem ; CHECK: if (q{{[0-3]}}) vmem
define void @fred(i32 %a0) #0 { define void @fred(i32 %a0, i1 %c0) #0 {
b1: b1:
%v2 = tail call <128 x i1> @llvm.hexagon.V6.pred.scalar2.128B(i32 %a0) #2 %v2 = tail call <128 x i1> @llvm.hexagon.V6.pred.scalar2.128B(i32 %a0) #2
br i1 undef, label %b3, label %b5 br i1 %c0, label %b3, label %b5
b3: ; preds = %b1 b3: ; preds = %b1
%v4 = tail call <128 x i1> @llvm.hexagon.V6.pred.not.128B(<128 x i1> %v2) #2 %v4 = tail call <128 x i1> @llvm.hexagon.V6.pred.not.128B(<128 x i1> %v2) #2
br label %b5 br label %b5
b5: ; preds = %b3, %b1 b5: ; preds = %b3, %b1
%v6 = phi <128 x i1> [ %v4, %b3 ], [ %v2, %b1 ] %v6 = phi <128 x i1> [ %v4, %b3 ], [ %v2, %b1 ]
tail call void asm sideeffect "if ($0) vmem($1) = $2;", "q,r,v,~{memory}"(<128 x i1> %v6, ptr undef, <32 x i32> undef) #2 tail call void asm sideeffect "if ($0) vmem($1) = $2;", "q,r,v,~{memory}"(<128 x i1> %v6, ptr undef, <32 x i32> undef) #2
Show All 10 Lines

llvm/test/CodeGen/Hexagon/expand-condsets-copy-lis.ll

; RUN: llc -march=hexagon < %s ; RUN: llc -march=hexagon < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Test that the compiler doesn't assert because the live interval information ; Test that the compiler doesn't assert because the live interval information
; isn't updated correctly during the Hexagon Expand Condsets pass. The pass ; isn't updated correctly during the Hexagon Expand Condsets pass. The pass
; wasn't updating the information when converting a mux with the same operands ; wasn't updating the information when converting a mux with the same operands
; into a copy. When this occurs, the pass needs to update the liveness ; into a copy. When this occurs, the pass needs to update the liveness
; information for the predicate register, which is removed. ; information for the predicate register, which is removed.
define void @f0(i32 %a0) unnamed_addr { define void @f0(i32 %a0, i1 %c0) unnamed_addr {
b0: b0:
%v0 = or i32 undef, %a0 %v0 = or i32 undef, %a0
%v1 = or i32 undef, %v0 %v1 = or i32 undef, %v0
br label %b1 br label %b1
b1: ; preds = %b3, %b0 b1: ; preds = %b3, %b0
%v2 = phi i32 [ %v9, %b3 ], [ 0, %b0 ] %v2 = phi i32 [ %v9, %b3 ], [ 0, %b0 ]
%v3 = phi i32 [ 0, %b3 ], [ %v1, %b0 ] %v3 = phi i32 [ 0, %b3 ], [ %v1, %b0 ]
%v4 = srem i32 %v2, 4 %v4 = srem i32 %v2, 4
%v5 = icmp eq i32 %v4, 0 %v5 = icmp eq i32 %v4, 0
%v6 = select i1 %v5, i32 %v1, i32 %v3 %v6 = select i1 %v5, i32 %v1, i32 %v3
%v7 = shl i32 %v6, 8 %v7 = shl i32 %v6, 8
%v8 = add i32 0, %v7 %v8 = add i32 0, %v7
br i1 undef, label %b2, label %b3 br i1 %c0, label %b2, label %b3
b2: ; preds = %b1 b2: ; preds = %b1
store i32 %v8, ptr undef, align 4 store i32 %v8, ptr undef, align 4
br label %b3 br label %b3
b3: ; preds = %b2, %b1 b3: ; preds = %b2, %b1
%v9 = add nuw nsw i32 %v2, 1 %v9 = add nuw nsw i32 %v2, 1
%v10 = icmp slt i32 %v9, undef %v10 = icmp slt i32 %v9, undef
br i1 %v10, label %b1, label %b4 br i1 %v10, label %b1, label %b4
b4: ; preds = %b3 b4: ; preds = %b3
unreachable unreachable
} }

llvm/test/CodeGen/Hexagon/expand-condsets-dead-bad.ll

; RUN: llc -march=hexagon -verify-machineinstrs -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s ; RUN: llc -march=hexagon -verify-machineinstrs -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s
; REQUIRES: asserts ; REQUIRES: asserts
; Check for some output other than crashing. ; Check for some output other than crashing.
; CHECK: bitsset ; CHECK: bitsset
target triple = "hexagon" target triple = "hexagon"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @fred() local_unnamed_addr #0 { define void @fred(i1 %c0) local_unnamed_addr #0 {
b0: b0:
%v1 = load i32, ptr undef, align 4 %v1 = load i32, ptr undef, align 4
%v2 = and i32 %v1, 603979776 %v2 = and i32 %v1, 603979776
%v3 = trunc i32 %v2 to i30 %v3 = trunc i32 %v2 to i30
switch i30 %v3, label %b23 [ switch i30 %v3, label %b23 [
i30 -536870912, label %b4 i30 -536870912, label %b4
i30 -469762048, label %b5 i30 -469762048, label %b5
] ]
b4: ; preds = %b0 b4: ; preds = %b0
unreachable unreachable
b5: ; preds = %b0 b5: ; preds = %b0
%v6 = load i32, ptr undef, align 4 %v6 = load i32, ptr undef, align 4
br i1 undef, label %b7, label %b8 br i1 %c0, label %b7, label %b8
b7: ; preds = %b5 b7: ; preds = %b5
br label %b9 br label %b9
b8: ; preds = %b5 b8: ; preds = %b5
br label %b9 br label %b9
b9: ; preds = %b8, %b7 b9: ; preds = %b8, %b7
Show All 21 Lines

llvm/test/CodeGen/Hexagon/expand-condsets-dead.ll

; RUN: llc -march=hexagon -O2 < %s ; RUN: llc -march=hexagon -O2 < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Test that the dead and kill flags are not added incorrectly during the ; Test that the dead and kill flags are not added incorrectly during the
; Hexagon Expand Condsets pass. The pass shouldn't add a kill flag to a use that ; Hexagon Expand Condsets pass. The pass shouldn't add a kill flag to a use that
; is tied to a definition, and the pass shouldn't remove the dead flag for a ; is tied to a definition, and the pass shouldn't remove the dead flag for a
; definition that is really dead. The removal of the dead flag causes an assert ; definition that is really dead. The removal of the dead flag causes an assert
; in the Machine Scheduler when querying live interval information. ; in the Machine Scheduler when querying live interval information.
define void @f0() #0 { define void @f0(i1 %c0) #0 {
b0: b0:
br label %b1 br label %b1
b1: ; preds = %b3, %b0 b1: ; preds = %b3, %b0
%v0 = load i16, ptr undef, align 4 %v0 = load i16, ptr undef, align 4
%v1 = sext i16 %v0 to i32 %v1 = sext i16 %v0 to i32
%v2 = and i32 %v1, 7 %v2 = and i32 %v1, 7
%v3 = sub nsw i32 8, %v2 %v3 = sub nsw i32 8, %v2
Show All 14 Linesb2: ; preds = %b2, %b1
store i8 %v14, ptr %v5, align 1 store i8 %v14, ptr %v5, align 1
%v15 = getelementptr inbounds i8, ptr %v5, i32 1 %v15 = getelementptr inbounds i8, ptr %v5, i32 1
%v16 = select i1 undef, ptr undef, ptr %v15 %v16 = select i1 undef, ptr undef, ptr %v15
%v17 = add nsw i32 %v6, -1 %v17 = add nsw i32 %v6, -1
%v18 = icmp eq i32 %v17, 0 %v18 = icmp eq i32 %v17, 0
br i1 %v18, label %b3, label %b2 br i1 %v18, label %b3, label %b2
b3: ; preds = %b2 b3: ; preds = %b2
br i1 undef, label %b1, label %b4 br i1 %c0, label %b1, label %b4
b4: ; preds = %b3 b4: ; preds = %b3
ret void ret void
} }
attributes #0 = { nounwind "target-cpu"="hexagonv65" } attributes #0 = { nounwind "target-cpu"="hexagonv65" }

llvm/test/CodeGen/Hexagon/expand-condsets-extend.ll

; RUN: llc -march=hexagon < %s | FileCheck %s ; RUN: llc -march=hexagon < %s | FileCheck %s
; REQUIRES: asserts ; REQUIRES: asserts
; Check for a reasonable output. This testcase used to crash. ; Check for a reasonable output. This testcase used to crash.
; CHECK: .size fred ; CHECK: .size fred
target triple = "hexagon" target triple = "hexagon"
define void @fred() local_unnamed_addr #0 { define void @fred(i1 %c0, i1 %c1, i1 %c2, i1 %c3) local_unnamed_addr #0 {
entry: entry:
%0 = load i64, ptr undef, align 8 %0 = load i64, ptr undef, align 8
%shr.i465 = lshr i64 %0, 48 %shr.i465 = lshr i64 %0, 48
%trunc = trunc i64 %shr.i465 to i15 %trunc = trunc i64 %shr.i465 to i15
switch i15 %trunc, label %if.end26 [ switch i15 %trunc, label %if.end26 [
i15 -1, label %if.then14 i15 -1, label %if.then14
i15 0, label %if.then21 i15 0, label %if.then21
] ]
if.then14: ; preds = %entry if.then14: ; preds = %entry
unreachable unreachable
if.then21: ; preds = %entry if.then21: ; preds = %entry
unreachable unreachable
if.end26: ; preds = %entry if.end26: ; preds = %entry
br label %if.end36 br label %if.end36
if.end36: ; preds = %if.end26 if.end36: ; preds = %if.end26
%or.i335 = or i64 undef, undef %or.i335 = or i64 undef, undef
%shl2.i322 = or i64 undef, -9223372036854775808 %shl2.i322 = or i64 undef, -9223372036854775808
br i1 undef, label %if.then44, label %lor.rhs.i br i1 %c0, label %if.then44, label %lor.rhs.i
lor.rhs.i: ; preds = %if.end36 lor.rhs.i: ; preds = %if.end36
br label %le128.exit br label %le128.exit
le128.exit: ; preds = %lor.rhs.i le128.exit: ; preds = %lor.rhs.i
br i1 undef, label %if.then44, label %while.cond.preheader br i1 %c1, label %if.then44, label %while.cond.preheader
if.then44: ; preds = %le128.exit, %if.end36 if.then44: ; preds = %le128.exit, %if.end36
%conv42544 = phi i64 [ 0, %le128.exit ], [ 1, %if.end36 ] %conv42544 = phi i64 [ 0, %le128.exit ], [ 1, %if.end36 ]
br label %while.cond.preheader br label %while.cond.preheader
while.cond.preheader: ; preds = %if.then44, %le128.exit while.cond.preheader: ; preds = %if.then44, %le128.exit
%aSig0.3.ph = phi i64 [ undef, %if.then44 ], [ %or.i335, %le128.exit ] %aSig0.3.ph = phi i64 [ undef, %if.then44 ], [ %or.i335, %le128.exit ]
%q.0.ph = phi i64 [ %conv42544, %if.then44 ], [ 0, %le128.exit ] %q.0.ph = phi i64 [ %conv42544, %if.then44 ], [ 0, %le128.exit ]
br i1 undef, label %while.body.lr.ph, label %while.end br i1 %c2, label %while.body.lr.ph, label %while.end
while.body.lr.ph: ; preds = %while.cond.preheader while.body.lr.ph: ; preds = %while.cond.preheader
%shr.i263 = lshr i64 %shl2.i322, 32 %shr.i263 = lshr i64 %shl2.i322, 32
br label %while.body br label %while.body
while.body: ; preds = %exit312, %while.body.lr.ph while.body: ; preds = %exit312, %while.body.lr.ph
%aSig0.3554 = phi i64 [ %aSig0.3.ph, %while.body.lr.ph ], [ %sub3.i205, %exit312 ] %aSig0.3554 = phi i64 [ %aSig0.3.ph, %while.body.lr.ph ], [ %sub3.i205, %exit312 ]
br label %while.body.i297 br label %while.body.i297
Show All 26 Linesexit312: ; preds = %while.end.i305.loopexit
br i1 %cmp47, label %while.body, label %while.end.loopexit br i1 %cmp47, label %while.body, label %while.end.loopexit
while.end.loopexit: ; preds = %exit312 while.end.loopexit: ; preds = %exit312
br label %while.end br label %while.end
while.end: ; preds = %while.end.loopexit, %while.cond.preheader while.end: ; preds = %while.end.loopexit, %while.cond.preheader
%aSig0.3.lcssa = phi i64 [ %aSig0.3.ph, %while.cond.preheader ], [ %sub3.i205, %while.end.loopexit ] %aSig0.3.lcssa = phi i64 [ %aSig0.3.ph, %while.cond.preheader ], [ %sub3.i205, %while.end.loopexit ]
%q.0.lcssa = phi i64 [ %q.0.ph, %while.cond.preheader ], [ %cond, %while.end.loopexit ] %q.0.lcssa = phi i64 [ %q.0.ph, %while.cond.preheader ], [ %cond, %while.end.loopexit ]
br i1 undef, label %if.then56, label %if.else71 br i1 %c3, label %if.then56, label %if.else71
if.then56: ; preds = %while.end if.then56: ; preds = %while.end
unreachable unreachable
if.else71: ; preds = %while.end if.else71: ; preds = %while.end
%shr8.i155 = lshr i64 %aSig0.3.lcssa, 12 %shr8.i155 = lshr i64 %aSig0.3.lcssa, 12
br label %do.body br label %do.body
Show All 15 Lines

llvm/test/CodeGen/Hexagon/expand-condsets-undef.ll

; RUN: llc -O2 < %s ; RUN: llc -O2 < %s
; REQUIRES: asserts ; REQUIRES: asserts
target datalayout = "e-m:e-p:32:32-i64:64-a:0-v32:32-n16:32" target datalayout = "e-m:e-p:32:32-i64:64-a:0-v32:32-n16:32"
target triple = "hexagon" target triple = "hexagon"
; Function Attrs: nounwind optsize ssp ; Function Attrs: nounwind optsize ssp
define internal fastcc void @foo() nounwind { define internal fastcc void @foo(i1 %c0) nounwind {
if.else473: if.else473:
%0 = load i64, ptr undef, align 8 %0 = load i64, ptr undef, align 8
%sub = sub nsw i64 undef, %0 %sub = sub nsw i64 undef, %0
%conv476 = sitofp i64 %sub to double %conv476 = sitofp i64 %sub to double
%mul477 = fmul double %conv476, 0x3F50624DE0000000 %mul477 = fmul double %conv476, 0x3F50624DE0000000
br i1 undef, label %cond.true540, label %cond.end548 br i1 %c0, label %cond.true540, label %cond.end548
cond.true540: cond.true540:
%1 = fptrunc double %mul477 to float %1 = fptrunc double %mul477 to float
%2 = fptosi float %1 to i32 %2 = fptosi float %1 to i32
br label %cond.end548 br label %cond.end548
cond.end548: cond.end548:
%cond549 = phi i32 [ %2, %cond.true540 ], [ undef, %if.else473 ] %cond549 = phi i32 [ %2, %cond.true540 ], [ undef, %if.else473 ]
call void @bar(i32 %cond549) nounwind call void @bar(i32 %cond549) nounwind
unreachable unreachable
} }
declare void @bar(i32) nounwind declare void @bar(i32) nounwind

llvm/test/CodeGen/Hexagon/expand-condsets-undef2.ll

; RUN: llc -march=hexagon < %s ; RUN: llc -march=hexagon < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Test that the HexagonExpandCondsets pass does not assert due to ; Test that the HexagonExpandCondsets pass does not assert due to
; attempting to shrink a live interval incorrectly. ; attempting to shrink a live interval incorrectly.
define void @test() #0 { define void @test(i1 %c0, i1 %c1, i1 %c2, i1 %c3) #0 {
entry: entry:
br i1 undef, label %cleanup, label %if.end br i1 %c0, label %cleanup, label %if.end
if.end: if.end:
%0 = load i32, ptr undef, align 4 %0 = load i32, ptr undef, align 4
%sext = shl i32 %0, 16 %sext = shl i32 %0, 16
%conv19 = ashr exact i32 %sext, 16 %conv19 = ashr exact i32 %sext, 16
br i1 undef, label %cleanup, label %for.body.lr.ph br i1 %c1, label %cleanup, label %for.body.lr.ph
for.body.lr.ph: for.body.lr.ph:
br label %for.body br label %for.body
for.body: for.body:
%bestScoreL16Q4.0278 = phi i16 [ 32767, %for.body.lr.ph ], [ %.sink, %early_termination ] %bestScoreL16Q4.0278 = phi i16 [ 32767, %for.body.lr.ph ], [ %.sink, %early_termination ]
br i1 false, label %for.body44.lr.ph, label %for.cond90.preheader br i1 false, label %for.body44.lr.ph, label %for.cond90.preheader
for.body44.lr.ph: for.body44.lr.ph:
%conv77 = sext i16 %bestScoreL16Q4.0278 to i32 %conv77 = sext i16 %bestScoreL16Q4.0278 to i32
unreachable unreachable
for.cond90.preheader: for.cond90.preheader:
br i1 undef, label %early_termination, label %for.body97 br i1 %c2, label %early_termination, label %for.body97
for.body97: for.body97:
br i1 undef, label %for.body97, label %early_termination br i1 %c3, label %for.body97, label %early_termination
early_termination: early_termination:
%.sink = select i1 undef, i16 undef, i16 %bestScoreL16Q4.0278 %.sink = select i1 undef, i16 undef, i16 %bestScoreL16Q4.0278
%cmp27 = icmp slt i32 undef, %conv19 %cmp27 = icmp slt i32 undef, %conv19
br i1 %cmp27, label %for.body, label %for.end124 br i1 %cmp27, label %for.body, label %for.end124
for.end124: for.end124:
unreachable unreachable
cleanup: cleanup:
ret void ret void
} }
attributes #0 = { nounwind "target-cpu"="hexagonv60" } attributes #0 = { nounwind "target-cpu"="hexagonv60" }

llvm/test/CodeGen/Hexagon/expand-condsets-undefvni.ll

; RUN: llc -march=hexagon < %s | FileCheck %s ; RUN: llc -march=hexagon < %s | FileCheck %s
; ;
; Check that this compiles successfully. ; Check that this compiles successfully.
; CHECK: jumpr r31 ; CHECK: jumpr r31
target triple = "hexagon" target triple = "hexagon"
define i64 @fred(i64 %a0, i64 %a1) local_unnamed_addr #0 { define i64 @fred(i64 %a0, i64 %a1, i1 %c0, i1 %c1, i1 %c2) local_unnamed_addr #0 {
b2: b2:
%v3 = lshr i64 %a1, 52 %v3 = lshr i64 %a1, 52
%v4 = trunc i64 %v3 to i11 %v4 = trunc i64 %v3 to i11
switch i11 %v4, label %b15 [ switch i11 %v4, label %b15 [
i11 -1, label %b5 i11 -1, label %b5
i11 0, label %b14 i11 0, label %b14
] ]
b5: ; preds = %b2 b5: ; preds = %b2
br i1 undef, label %b13, label %b6 br i1 %c0, label %b13, label %b6
b6: ; preds = %b5 b6: ; preds = %b5
%v7 = or i64 %a1, 2251799813685248 %v7 = or i64 %a1, 2251799813685248
br i1 undef, label %b8, label %b10 br i1 %c1, label %b8, label %b10
b8: ; preds = %b6 b8: ; preds = %b6
%v9 = select i1 undef, i64 %v7, i64 undef %v9 = select i1 undef, i64 %v7, i64 undef
br label %b16 br label %b16
b10: ; preds = %b6 b10: ; preds = %b6
br i1 undef, label %b16, label %b11 br i1 %c2, label %b16, label %b11
b11: ; preds = %b10 b11: ; preds = %b10
%v12 = select i1 undef, i64 undef, i64 %v7 %v12 = select i1 undef, i64 undef, i64 %v7
br label %b16 br label %b16
b13: ; preds = %b5 b13: ; preds = %b5
br label %b16 br label %b16
Show All 12 Lines

llvm/test/CodeGen/Hexagon/expand-vstorerw-undef2.ll

; RUN: llc -march=hexagon < %s ; RUN: llc -march=hexagon < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Dead defs may still appear live in LivePhysRegs, leading to an expansion ; Dead defs may still appear live in LivePhysRegs, leading to an expansion
; of a double-vector store that uses an undefined source register.
target triple = "hexagon-unknown--elf" target triple = "hexagon-unknown--elf"
declare noalias ptr @halide_malloc() local_unnamed_addr #0 declare noalias ptr @halide_malloc() local_unnamed_addr #0
declare void @halide_free() local_unnamed_addr #0 declare void @halide_free() local_unnamed_addr #0
declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #1 declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #1
declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #1 declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #1
Show All 10 Lines
declare <32 x i32> @llvm.hexagon.V6.vsubhsat.128B(<32 x i32>, <32 x i32>) #1 declare <32 x i32> @llvm.hexagon.V6.vsubhsat.128B(<32 x i32>, <32 x i32>) #1
declare <64 x i32> @llvm.hexagon.V6.vaddhw.128B(<32 x i32>, <32 x i32>) #1 declare <64 x i32> @llvm.hexagon.V6.vaddhw.128B(<32 x i32>, <32 x i32>) #1
declare <64 x i32> @llvm.hexagon.V6.vaddw.dv.128B(<64 x i32>, <64 x i32>) #1 declare <64 x i32> @llvm.hexagon.V6.vaddw.dv.128B(<64 x i32>, <64 x i32>) #1
declare <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32>, <32 x i32>) #1 declare <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32>, <32 x i32>) #1
declare <64 x i32> @llvm.hexagon.V6.vmpyuh.128B(<32 x i32>, i32) #1 declare <64 x i32> @llvm.hexagon.V6.vmpyuh.128B(<32 x i32>, i32) #1
declare <64 x i32> @llvm.hexagon.V6.vmpyuh.acc.128B(<64 x i32>, <32 x i32>, i32) #1 declare <64 x i32> @llvm.hexagon.V6.vmpyuh.acc.128B(<64 x i32>, <32 x i32>, i32) #1
declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x i32>, i32) #1 declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x i32>, i32) #1
define hidden void @fred() #0 { define hidden void @fred(i1 %c0, i1 %c1, i1 %c2, i1 %c3) #0 {
b0: b0:
br i1 undef, label %b1, label %b2 br i1 %c0, label %b1, label %b2
b1: ; preds = %b0 b1: ; preds = %b0
ret void ret void
b2: ; preds = %b0 b2: ; preds = %b0
%v3 = tail call ptr @halide_malloc() %v3 = tail call ptr @halide_malloc()
%v5 = tail call ptr @halide_malloc() %v5 = tail call ptr @halide_malloc()
%v7 = tail call ptr @halide_malloc() %v7 = tail call ptr @halide_malloc()
%v9 = tail call ptr @halide_malloc() %v9 = tail call ptr @halide_malloc()
br label %b11 br label %b11
b11: ; preds = %b11, %b2 b11: ; preds = %b11, %b2
br i1 undef, label %b12, label %b11 br i1 %c1, label %b12, label %b11
b12: ; preds = %b11 b12: ; preds = %b11
br i1 undef, label %b16, label %b13 br i1 %c2, label %b16, label %b13
b13: ; preds = %b12 b13: ; preds = %b12
%v14 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> zeroinitializer) #2 %v14 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> zeroinitializer) #2
%v15 = tail call <32 x i32> @llvm.hexagon.V6.vasrwh.128B(<32 x i32> undef, <32 x i32> %v14, i32 1) #2 %v15 = tail call <32 x i32> @llvm.hexagon.V6.vasrwh.128B(<32 x i32> undef, <32 x i32> %v14, i32 1) #2
br i1 undef, label %b19, label %b17 br i1 %c3, label %b19, label %b17
b16: ; preds = %b12 b16: ; preds = %b12
unreachable unreachable
b17: ; preds = %b13 b17: ; preds = %b13
%v18 = tail call <32 x i32> @llvm.hexagon.V6.vavghrnd.128B(<32 x i32> %v15, <32 x i32> undef) #2 %v18 = tail call <32 x i32> @llvm.hexagon.V6.vavghrnd.128B(<32 x i32> %v15, <32 x i32> undef) #2
br label %b19 br label %b19
▲ Show 20 Lines • Show All 138 Lines • Show Last 20 Lines

llvm/test/CodeGen/Hexagon/find-loop-instr.ll

; RUN: llc -march=hexagon < %s ; RUN: llc -march=hexagon < %s
; REQUIRES: asserts ; REQUIRES: asserts
; This code causes multiple endloop instructions to be generated for the ; This code causes multiple endloop instructions to be generated for the
; same loop. The findLoopInstr would encounter for one endloop would encounter ; same loop. The findLoopInstr would encounter for one endloop would encounter
; the other endloop, and return null in response. This resulted in a crash. ; the other endloop, and return null in response. This resulted in a crash.
; ;
; Check that with the fix we are able to compile this code successfully. ; Check that with the fix we are able to compile this code successfully.
target triple = "hexagon" target triple = "hexagon"
; Function Attrs: norecurse ; Function Attrs: norecurse
define void @fred() local_unnamed_addr #0 align 2 { define void @fred(i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5) local_unnamed_addr #0 align 2 {
b0: b0:
br label %b7 br label %b7
b1: ; preds = %b9 b1: ; preds = %b9
br i1 undef, label %b4, label %b2 br i1 %c0, label %b4, label %b2
b2: ; preds = %b1 b2: ; preds = %b1
%v3 = sub i32 undef, undef %v3 = sub i32 undef, undef
br label %b4 br label %b4
b4: ; preds = %b2, %b1 b4: ; preds = %b2, %b1
%v5 = phi i32 [ undef, %b1 ], [ %v3, %b2 ] %v5 = phi i32 [ undef, %b1 ], [ %v3, %b2 ]
br i1 undef, label %b14, label %b6 br i1 %c1, label %b14, label %b6
b6: ; preds = %b4 b6: ; preds = %b4
br label %b10 br label %b10
b7: ; preds = %b0 b7: ; preds = %b0
br i1 undef, label %b9, label %b8 br i1 %c2, label %b9, label %b8
b8: ; preds = %b7 b8: ; preds = %b7
unreachable unreachable
b9: ; preds = %b7 b9: ; preds = %b7
br label %b1 br label %b1
b10: ; preds = %b21, %b6 b10: ; preds = %b21, %b6
%v11 = phi i32 [ %v22, %b21 ], [ %v5, %b6 ] %v11 = phi i32 [ %v22, %b21 ], [ %v5, %b6 ]
br i1 undef, label %b21, label %b12 br i1 %c3, label %b21, label %b12
b12: ; preds = %b10 b12: ; preds = %b10
br label %b15 br label %b15
b13: ; preds = %b21 b13: ; preds = %b21
br label %b14 br label %b14
b14: ; preds = %b13, %b4 b14: ; preds = %b13, %b4
ret void ret void
b15: ; preds = %b12 b15: ; preds = %b12
br i1 undef, label %b16, label %b17 br i1 %c4, label %b16, label %b17
b16: ; preds = %b15 b16: ; preds = %b15
store i32 0, ptr undef, align 4 store i32 0, ptr undef, align 4
br label %b21 br label %b21
b17: ; preds = %b15 b17: ; preds = %b15
br label %b18 br label %b18
b18: ; preds = %b17 b18: ; preds = %b17
br i1 undef, label %b19, label %b20 br i1 %c5, label %b19, label %b20
b19: ; preds = %b18 b19: ; preds = %b18
br label %b21 br label %b21
b20: ; preds = %b18 b20: ; preds = %b18
store i32 0, ptr undef, align 4 store i32 0, ptr undef, align 4
br label %b21 br label %b21
b21: ; preds = %b20, %b19, %b16, %b10 b21: ; preds = %b20, %b19, %b16, %b10
%v22 = add i32 %v11, -8 %v22 = add i32 %v11, -8
%v23 = icmp eq i32 %v22, 0 %v23 = icmp eq i32 %v22, 0
br i1 %v23, label %b13, label %b10 br i1 %v23, label %b13, label %b10
} }
attributes #0 = { norecurse "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" } attributes #0 = { norecurse "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }

llvm/test/CodeGen/Hexagon/find-loop.ll

; RUN: llc -march=hexagon -O3 < %s ; RUN: llc -march=hexagon -O3 < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Test that the compiler doesn't assert when attempting to find a ; Test that the compiler doesn't assert when attempting to find a
; loop instruction that has been deleted, so FindLoopInstr returns ; loop instruction that has been deleted, so FindLoopInstr returns
; the loop instruction from a different loop. ; the loop instruction from a different loop.
@g0 = external global i32 @g0 = external global i32
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0() #0 { define void @f0(i1 %c0, i1 %c1) #0 {
b0: b0:
%v0 = alloca i64, align 8 %v0 = alloca i64, align 8
%v2 = load i32, ptr @g0, align 4 %v2 = load i32, ptr @g0, align 4
br i1 undef, label %b1, label %b2 br i1 %c0, label %b1, label %b2
b1: ; preds = %b1, %b0 b1: ; preds = %b1, %b0
%v3 = phi i32 [ %v4, %b1 ], [ 64, %b0 ] %v3 = phi i32 [ %v4, %b1 ], [ 64, %b0 ]
%v4 = add nsw i32 %v3, 1 %v4 = add nsw i32 %v3, 1
%v5 = icmp slt i32 %v4, %v2 %v5 = icmp slt i32 %v4, %v2
br i1 %v5, label %b1, label %b2 br i1 %v5, label %b1, label %b2
b2: ; preds = %b6, %b3, %b1, %b0 b2: ; preds = %b6, %b3, %b1, %b0
br label %b4 br label %b4
b3: ; preds = %b4 b3: ; preds = %b4
br i1 undef, label %b4, label %b2 br i1 %c1, label %b4, label %b2
b4: ; preds = %b3, %b2 b4: ; preds = %b3, %b2
%v6 = icmp slt i32 undef, 1 %v6 = icmp slt i32 undef, 1
br i1 %v6, label %b3, label %b5 br i1 %v6, label %b3, label %b5
b5: ; preds = %b5, %b4 b5: ; preds = %b5, %b4
%v7 = phi i32 [ %v18, %b5 ], [ 1, %b4 ] %v7 = phi i32 [ %v18, %b5 ], [ 1, %b4 ]
%v8 = phi i32 [ %v19, %b5 ], [ 0, %b4 ] %v8 = phi i32 [ %v19, %b5 ], [ 0, %b4 ]
Show All 28 Lines

llvm/test/CodeGen/Hexagon/frame-offset-overflow.ll

; REQUIRES: asserts ; REQUIRES: asserts
; RUN: llc -march=hexagon --stats -o - 2>&1 < %s | FileCheck %s ; RUN: llc -march=hexagon --stats -o - 2>&1 < %s | FileCheck %s
; Check that the compilation succeeded and that some code was generated. ; Check that the compilation succeeded and that some code was generated.
; CHECK: vadd ; CHECK: vadd
; Check that the loop is pipelined and that a valid node order is used. ; Check that the loop is pipelined and that a valid node order is used.
; CHECK-NOT: Number of node order issues found ; CHECK-NOT: Number of node order issues found
; CHECK: Number of loops software pipelined ; CHECK: Number of loops software pipelined
; CHECK-NOT: Number of node order issues found ; CHECK-NOT: Number of node order issues found
target triple = "hexagon" target triple = "hexagon"
define void @fred(ptr noalias nocapture readonly %p0, i32 %p1, i32 %p2, ptr noalias nocapture %p3, i32 %p4) local_unnamed_addr #1 { define void @fred(ptr noalias nocapture readonly %p0, i32 %p1, i32 %p2, ptr noalias nocapture %p3, i32 %p4, i1 %c0) local_unnamed_addr #1 {
entry: entry:
%mul = mul i32 %p4, %p1 %mul = mul i32 %p4, %p1
%add.ptr = getelementptr inbounds i16, ptr %p0, i32 %mul %add.ptr = getelementptr inbounds i16, ptr %p0, i32 %mul
%add = add nsw i32 %p4, 1 %add = add nsw i32 %p4, 1
%rem = srem i32 %add, 5 %rem = srem i32 %add, 5
%mul1 = mul i32 %rem, %p1 %mul1 = mul i32 %rem, %p1
%add.ptr2 = getelementptr inbounds i16, ptr %p0, i32 %mul1 %add.ptr2 = getelementptr inbounds i16, ptr %p0, i32 %mul1
%add7 = add nsw i32 %p4, 3 %add7 = add nsw i32 %p4, 3
%rem8 = srem i32 %add7, 5 %rem8 = srem i32 %add7, 5
%mul9 = mul i32 %rem8, %p1 %mul9 = mul i32 %rem8, %p1
%add.ptr10 = getelementptr inbounds i16, ptr %p0, i32 %mul9 %add.ptr10 = getelementptr inbounds i16, ptr %p0, i32 %mul9
%incdec.ptr18 = getelementptr inbounds i16, ptr %p0, i32 32 %incdec.ptr18 = getelementptr inbounds i16, ptr %p0, i32 32
%incdec.ptr17 = getelementptr inbounds i16, ptr %add.ptr10, i32 32 %incdec.ptr17 = getelementptr inbounds i16, ptr %add.ptr10, i32 32
%incdec.ptr16 = getelementptr inbounds i16, ptr %p0, i32 32 %incdec.ptr16 = getelementptr inbounds i16, ptr %p0, i32 32
%incdec.ptr15 = getelementptr inbounds i16, ptr %add.ptr2, i32 32 %incdec.ptr15 = getelementptr inbounds i16, ptr %add.ptr2, i32 32
%incdec.ptr = getelementptr inbounds i16, ptr %add.ptr, i32 32 %incdec.ptr = getelementptr inbounds i16, ptr %add.ptr, i32 32
br i1 undef, label %for.end.loopexit.unr-lcssa, label %for.body br i1 %c0, label %for.end.loopexit.unr-lcssa, label %for.body
for.body: ; preds = %for.body, %entry for.body: ; preds = %for.body, %entry
%optr.0102 = phi ptr [ %incdec.ptr24.3, %for.body ], [ %p3, %entry ] %optr.0102 = phi ptr [ %incdec.ptr24.3, %for.body ], [ %p3, %entry ]
%iptr4.0101 = phi ptr [ %incdec.ptr23.3, %for.body ], [ %incdec.ptr18, %entry ] %iptr4.0101 = phi ptr [ %incdec.ptr23.3, %for.body ], [ %incdec.ptr18, %entry ]
%iptr3.0100 = phi ptr [ %incdec.ptr22.3, %for.body ], [ %incdec.ptr17, %entry ] %iptr3.0100 = phi ptr [ %incdec.ptr22.3, %for.body ], [ %incdec.ptr17, %entry ]
%iptr2.099 = phi ptr [ undef, %for.body ], [ %incdec.ptr16, %entry ] %iptr2.099 = phi ptr [ undef, %for.body ], [ %incdec.ptr16, %entry ]
%iptr1.098 = phi ptr [ %incdec.ptr20.3, %for.body ], [ %incdec.ptr15, %entry ] %iptr1.098 = phi ptr [ %incdec.ptr20.3, %for.body ], [ %incdec.ptr15, %entry ]
%iptr0.097 = phi ptr [ %incdec.ptr19.3, %for.body ], [ %incdec.ptr, %entry ] %iptr0.097 = phi ptr [ %incdec.ptr19.3, %for.body ], [ %incdec.ptr, %entry ]
▲ Show 20 Lines • Show All 121 Lines • Show Last 20 Lines

llvm/test/CodeGen/Hexagon/getBlockAddress.ll

; RUN: llc -march=hexagon < %s ; RUN: llc -march=hexagon < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0() #0 { define void @f0(i1 %c0) #0 {
b0: b0:
call void @f1(ptr blockaddress(@f0, %b1)) call void @f1(ptr blockaddress(@f0, %b1))
br label %b1 br label %b1
b1: ; preds = %b2, %b0 b1: ; preds = %b2, %b0
ret void ret void
b2: ; No predecessors! b2: ; No predecessors!
indirectbr ptr undef, [label %b1] indirectbr ptr %c0, [label %b1]
} }
declare void @f1(...) declare void @f1(...)
attributes #0 = { nounwind } attributes #0 = { nounwind }

llvm/test/CodeGen/Hexagon/hexagon-tfr-add.ll

Show First 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
; Function Attrs: nounwind optsize ; Function Attrs: nounwind optsize
declare void @f2(i32) #1 declare void @f2(i32) #1
; The pass that used to crash doesn't do anything on this testcase anymore, ; The pass that used to crash doesn't do anything on this testcase anymore,
; but check for sane output anyway. ; but check for sane output anyway.
; CHECK-ADDI: ##g0 ; CHECK-ADDI: ##g0
; Function Attrs: nounwind optsize ssp ; Function Attrs: nounwind optsize ssp
define zeroext i8 @f3() #2 { define zeroext i8 @f3(i1 %c0, i1 %c1, i1 %c2) #2 {
b0: b0:
%v0 = load i8, ptr getelementptr inbounds (%s.0, ptr @g0, i32 0, i32 57), align 2 %v0 = load i8, ptr getelementptr inbounds (%s.0, ptr @g0, i32 0, i32 57), align 2
%v1 = icmp eq i8 %v0, 0 %v1 = icmp eq i8 %v0, 0
br i1 %v1, label %b2, label %b1 br i1 %v1, label %b2, label %b1
b1: ; preds = %b0 b1: ; preds = %b0
tail call void @f0(ptr nonnull @g1) #3 tail call void @f0(ptr nonnull @g1) #3
unreachable unreachable
b2: ; preds = %b0 b2: ; preds = %b0
%v2 = call zeroext i8 @f1(ptr nonnull undef) #4 %v2 = call zeroext i8 @f1(ptr nonnull undef) #4
br i1 undef, label %b3, label %b8 br i1 %c0, label %b3, label %b8
b3: ; preds = %b2 b3: ; preds = %b2
%v3 = load i8, ptr getelementptr inbounds (%s.0, ptr @g0, i32 0, i32 1), align 1 %v3 = load i8, ptr getelementptr inbounds (%s.0, ptr @g0, i32 0, i32 1), align 1
%v4 = add i8 %v3, -17 %v4 = add i8 %v3, -17
%v5 = icmp ult i8 %v4, 2 %v5 = icmp ult i8 %v4, 2
br i1 %v5, label %b4, label %b7 br i1 %v5, label %b4, label %b7
b4: ; preds = %b3 b4: ; preds = %b3
Show All 10 Lines
b6: ; preds = %b4 b6: ; preds = %b4
unreachable unreachable
b7: ; preds = %b3 b7: ; preds = %b3
unreachable unreachable
b8: ; preds = %b2 b8: ; preds = %b2
br i1 undef, label %b9, label %b10 br i1 %c1, label %b9, label %b10
b9: ; preds = %b8 b9: ; preds = %b8
unreachable unreachable
b10: ; preds = %b8 b10: ; preds = %b8
br i1 undef, label %b12, label %b11 br i1 %c2, label %b12, label %b11
b11: ; preds = %b10 b11: ; preds = %b10
unreachable unreachable
b12: ; preds = %b10 b12: ; preds = %b10
%v12 = load i8, ptr getelementptr inbounds (%s.0, ptr @g0, i32 0, i32 1), align 1 %v12 = load i8, ptr getelementptr inbounds (%s.0, ptr @g0, i32 0, i32 1), align 1
%v13 = zext i8 %v12 to i32 %v13 = zext i8 %v12 to i32
switch i32 %v13, label %b14 [ switch i32 %v13, label %b14 [
Show All 29 Lines

llvm/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse_invalid.ll

; RUN: opt -hexagon-vlcr < %s -S | FileCheck %s ; RUN: opt -hexagon-vlcr < %s -S | FileCheck %s
; Test that reuse doesn't occur due to two shufflevectors with different masks. ; Test that reuse doesn't occur due to two shufflevectors with different masks.
; CHECK-NOT: extract.h.hexagon.vlcr ; CHECK-NOT: extract.h.hexagon.vlcr
define dso_local void @test() local_unnamed_addr #0 { define dso_local void @test(i1 %c0) local_unnamed_addr #0 {
entry: entry:
%0 = tail call <64 x i32> @llvm.hexagon.V6.vunpackuh.128B(<32 x i32> undef) %0 = tail call <64 x i32> @llvm.hexagon.V6.vunpackuh.128B(<32 x i32> undef)
br i1 undef, label %for.end, label %for.body br i1 %c0, label %for.end, label %for.body
for.body: for.body:
%a = phi <64 x i32> [ %1, %for.body ], [ %0, %entry ] %a = phi <64 x i32> [ %1, %for.body ], [ %0, %entry ]
%extract.h = shufflevector <64 x i32> %a, <64 x i32> undef, <32 x i32> <i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63> %extract.h = shufflevector <64 x i32> %a, <64 x i32> undef, <32 x i32> <i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
%1 = tail call <64 x i32> @llvm.hexagon.V6.vaddw.dv.128B(<64 x i32> undef, <64 x i32> undef) %1 = tail call <64 x i32> @llvm.hexagon.V6.vaddw.dv.128B(<64 x i32> undef, <64 x i32> undef)
%extract.l = shufflevector <64 x i32> %1, <64 x i32> undef, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> %extract.l = shufflevector <64 x i32> %1, <64 x i32> undef, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
br label %for.body br label %for.body
Show All 9 Lines

llvm/test/CodeGen/Hexagon/hvx-bitcast-v64i1.ll

; RUN: llc -march=hexagon -hexagon-instsimplify=0 -hexagon-masked-vmem=0 < %s | FileCheck %s ; RUN: llc -march=hexagon -hexagon-instsimplify=0 -hexagon-masked-vmem=0 < %s | FileCheck %s
; Test that LLVM does not assert and bitcast v64i1 to i64 is lowered ; Test that LLVM does not assert and bitcast v64i1 to i64 is lowered
; without crashing. ; without crashing.
; CHECK: valign ; CHECK: valign
target triple = "hexagon" target triple = "hexagon"
define dso_local void @f0() local_unnamed_addr #0 { define dso_local void @f0(i1 %c0) local_unnamed_addr #0 {
b0: b0:
br i1 undef, label %b2, label %b1 br i1 %c0, label %b2, label %b1
b1: ; preds = %b0 b1: ; preds = %b0
%v0 = load i8, ptr undef, align 1 %v0 = load i8, ptr undef, align 1
%v1 = zext i8 %v0 to i32 %v1 = zext i8 %v0 to i32
%v2 = add nsw i32 %v1, -1 %v2 = add nsw i32 %v1, -1
%v3 = insertelement <64 x i32> undef, i32 %v2, i32 0 %v3 = insertelement <64 x i32> undef, i32 %v2, i32 0
%v4 = shufflevector <64 x i32> %v3, <64 x i32> undef, <64 x i32> zeroinitializer %v4 = shufflevector <64 x i32> %v3, <64 x i32> undef, <64 x i32> zeroinitializer
%v5 = icmp ule <64 x i32> undef, %v4 %v5 = icmp ule <64 x i32> undef, %v4
Show All 27 Lines

llvm/test/CodeGen/Hexagon/hvx-loopidiom-memcpy.ll

; RUN: opt -march=hexagon -hexagon-loop-idiom -S < %s | FileCheck %s ; RUN: opt -march=hexagon -hexagon-loop-idiom -S < %s | FileCheck %s
; Make sure we don't convert load/store loops into memcpy if the access type ; Make sure we don't convert load/store loops into memcpy if the access type
; is a vector. Using vector instructions is generally better in such cases. ; is a vector. Using vector instructions is generally better in such cases.
; CHECK-NOT: @llvm.memcpy ; CHECK-NOT: @llvm.memcpy
%s.0 = type { i32 } %s.0 = type { i32 }
define void @f0(ptr noalias %a0, ptr noalias %a1) #0 align 2 { define void @f0(ptr noalias %a0, ptr noalias %a1, i1 %c0, i1 %c1) #0 align 2 {
b0: b0:
br i1 undef, label %b1, label %b2 br i1 %c0, label %b1, label %b2
b1: ; preds = %b1, %b0 b1: ; preds = %b1, %b0
%v0 = phi i32 [ %v7, %b1 ], [ 0, %b0 ] %v0 = phi i32 [ %v7, %b1 ], [ 0, %b0 ]
%v1 = mul nuw nsw i32 %v0, 64 %v1 = mul nuw nsw i32 %v0, 64
%v2 = getelementptr %s.0, ptr %a0, i32 %v1 %v2 = getelementptr %s.0, ptr %a0, i32 %v1
%v3 = getelementptr %s.0, ptr %a1, i32 %v1 %v3 = getelementptr %s.0, ptr %a1, i32 %v1
%v5 = load <64 x i32>, ptr %v2, align 256 %v5 = load <64 x i32>, ptr %v2, align 256
store <64 x i32> %v5, ptr %v3, align 256 store <64 x i32> %v5, ptr %v3, align 256
%v7 = add nuw nsw i32 %v0, 1 %v7 = add nuw nsw i32 %v0, 1
br i1 undef, label %b1, label %b2 br i1 %c1, label %b1, label %b2
b2: ; preds = %b1, %b0 b2: ; preds = %b1, %b0
ret void ret void
} }
attributes #0 = { "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" } attributes #0 = { "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }

llvm/test/CodeGen/Hexagon/hwloop-ph-deadcode.ll

; RUN: llc -march=hexagon -mcpu=hexagonv5 -O2 -disable-block-placement=0 < %s | FileCheck %s ; RUN: llc -march=hexagon -mcpu=hexagonv5 -O2 -disable-block-placement=0 < %s | FileCheck %s
; Test that there is no redundant register assignment in the hardware loop ; Test that there is no redundant register assignment in the hardware loop
; preheader. ; preheader.
; CHECK-NOT: r{{.*}} = #5 ; CHECK-NOT: r{{.*}} = #5
@g = external global i32 @g = external global i32
define void @foo() #0 { define void @foo(i1 %c0) #0 {
entry: entry:
br i1 undef, label %if.end38, label %for.body br i1 %c0, label %if.end38, label %for.body
for.body: for.body:
%loopIdx.051 = phi i32 [ %inc, %for.body ], [ 0, %entry ] %loopIdx.051 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
store i32 1, ptr @g, align 4 store i32 1, ptr @g, align 4
%inc = add i32 %loopIdx.051, 1 %inc = add i32 %loopIdx.051, 1
%cmp9 = icmp ult i32 %inc, 5 %cmp9 = icmp ult i32 %inc, 5
br i1 %cmp9, label %for.body, label %if.end38 br i1 %cmp9, label %for.body, label %if.end38
if.end38: if.end38:
ret void ret void
} }

llvm/test/CodeGen/Hexagon/hwloop-phi-subreg.ll

; RUN: llc -march=hexagon -hexagon-hwloop-preheader < %s ; RUN: llc -march=hexagon -hexagon-hwloop-preheader < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Checks that a subreg in a Phi is propagated correctly when a ; Checks that a subreg in a Phi is propagated correctly when a
; new preheader is created in the Hardware Loop pass. ; new preheader is created in the Hardware Loop pass.
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0() #0 { define void @f0(i1 %c0, i1 %c1) #0 {
b0: b0:
br label %b2 br label %b2
b1: ; preds = %b2, %b1 b1: ; preds = %b2, %b1
%v0 = or i64 0, undef %v0 = or i64 0, undef
%v1 = add nsw i64 0, %v0 %v1 = add nsw i64 0, %v0
%v2 = add nsw i64 %v1, 0 %v2 = add nsw i64 %v1, 0
%v3 = add nsw i64 %v2, 0 %v3 = add nsw i64 %v2, 0
Show All 11 Linesb1: ; preds = %b2, %b1
%v15 = add nsw i64 %v14, 0 %v15 = add nsw i64 %v14, 0
%v16 = add nsw i64 %v15, 0 %v16 = add nsw i64 %v15, 0
%v17 = add nsw i64 %v16, 0 %v17 = add nsw i64 %v16, 0
%v18 = add nsw i64 %v17, 0 %v18 = add nsw i64 %v17, 0
%v19 = add nsw i64 %v18, 0 %v19 = add nsw i64 %v18, 0
%v20 = add nsw i64 %v19, 0 %v20 = add nsw i64 %v19, 0
%v21 = lshr i64 %v20, 32 %v21 = lshr i64 %v20, 32
%v22 = trunc i64 %v21 to i32 %v22 = trunc i64 %v21 to i32
br i1 undef, label %b1, label %b3 br i1 %c0, label %b1, label %b3
b2: ; preds = %b5, %b0 b2: ; preds = %b5, %b0
br i1 undef, label %b1, label %b4 br i1 %c1, label %b1, label %b4
b3: ; preds = %b1 b3: ; preds = %b1
br i1 false, label %b5, label %b4 br i1 false, label %b5, label %b4
b4: ; preds = %b4, %b3, %b2 b4: ; preds = %b4, %b3, %b2
%v23 = phi i32 [ %v37, %b4 ], [ undef, %b2 ], [ %v22, %b3 ] %v23 = phi i32 [ %v37, %b4 ], [ undef, %b2 ], [ %v22, %b3 ]
%v24 = zext i32 %v23 to i64 %v24 = zext i32 %v23 to i64
%v25 = shl nuw i64 %v24, 32 %v25 = shl nuw i64 %v24, 32
Show All 20 Lines

llvm/test/CodeGen/Hexagon/hwloop-preheader.ll

; RUN: llc -march=hexagon -mcpu=hexagonv5 -hexagon-hwloop-preheader < %s ; RUN: llc -march=hexagon -mcpu=hexagonv5 -hexagon-hwloop-preheader < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Test that the preheader is added to the parent loop, otherwise ; Test that the preheader is added to the parent loop, otherwise
; we generate an invalid hardware loop. ; we generate an invalid hardware loop.
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
define void @test(i16 signext %n) #0 { define void @test(i16 signext %n, i1 %c0, i1 %c1) #0 {
entry: entry:
br i1 undef, label %for.cond4.preheader.preheader.split.us, label %for.end22 br i1 %c0, label %for.cond4.preheader.preheader.split.us, label %for.end22
for.cond4.preheader.preheader.split.us: for.cond4.preheader.preheader.split.us:
%0 = sext i16 %n to i32 %0 = sext i16 %n to i32
br label %for.body9.preheader.us br label %for.body9.preheader.us
for.body9.us: for.body9.us:
%indvars.iv = phi i32 [ %indvars.iv.next.7, %for.body9.us ], [ 0, %for.body9.preheader.us ] %indvars.iv = phi i32 [ %indvars.iv.next.7, %for.body9.us ], [ 0, %for.body9.preheader.us ]
%indvars.iv.next.7 = add i32 %indvars.iv, 8 %indvars.iv.next.7 = add i32 %indvars.iv, 8
%lftr.wideiv.7 = trunc i32 %indvars.iv.next.7 to i16 %lftr.wideiv.7 = trunc i32 %indvars.iv.next.7 to i16
%exitcond.7 = icmp slt i16 %lftr.wideiv.7, 0 %exitcond.7 = icmp slt i16 %lftr.wideiv.7, 0
br i1 %exitcond.7, label %for.body9.us, label %for.body9.us.ur br i1 %exitcond.7, label %for.body9.us, label %for.body9.us.ur
for.body9.preheader.us: for.body9.preheader.us:
%i.030.us.pmt = phi i32 [ %inc21.us.pmt, %for.end.loopexit.us ], [ 0, %for.cond4.preheader.preheader.split.us ] %i.030.us.pmt = phi i32 [ %inc21.us.pmt, %for.end.loopexit.us ], [ 0, %for.cond4.preheader.preheader.split.us ]
br i1 undef, label %for.body9.us, label %for.body9.us.ur br i1 %c1, label %for.body9.us, label %for.body9.us.ur
for.body9.us.ur: for.body9.us.ur:
%exitcond.ur.old = icmp eq i16 undef, %n %exitcond.ur.old = icmp eq i16 undef, %n
br i1 %exitcond.ur.old, label %for.end.loopexit.us, label %for.body9.us.ur br i1 %exitcond.ur.old, label %for.end.loopexit.us, label %for.body9.us.ur
for.end.loopexit.us: for.end.loopexit.us:
%inc21.us.pmt = add i32 %i.030.us.pmt, 1 %inc21.us.pmt = add i32 %i.030.us.pmt, 1
%exitcond33 = icmp eq i32 %inc21.us.pmt, %0 %exitcond33 = icmp eq i32 %inc21.us.pmt, %0
br i1 %exitcond33, label %for.end22, label %for.body9.preheader.us br i1 %exitcond33, label %for.end22, label %for.body9.preheader.us
for.end22: for.end22:
ret void ret void
} }
attributes #0 = { nounwind readonly "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #0 = { nounwind readonly "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }

llvm/test/CodeGen/Hexagon/hwloop-subreg.ll

; RUN: llc -march=hexagon < %s ; RUN: llc -march=hexagon < %s
; REQUIRES: asserts ; REQUIRES: asserts
target triple = "hexagon" target triple = "hexagon"
; Function Attrs: nounwind optsize readonly ; Function Attrs: nounwind optsize readonly
define void @f0() #0 align 2 { define void @f0(i1 %c0) #0 align 2 {
b0: b0:
%v0 = load i32, ptr undef, align 8 %v0 = load i32, ptr undef, align 8
%v1 = zext i32 %v0 to i64 %v1 = zext i32 %v0 to i64
%v2 = add nuw nsw i64 %v1, 63 %v2 = add nuw nsw i64 %v1, 63
%v3 = lshr i64 %v2, 6 %v3 = lshr i64 %v2, 6
%v4 = trunc i64 %v3 to i32 %v4 = trunc i64 %v3 to i32
br i1 undef, label %b3, label %b1 br i1 %c0, label %b3, label %b1
b1: ; preds = %b0 b1: ; preds = %b0
%v5 = add nsw i32 %v4, -1 %v5 = add nsw i32 %v4, -1
br label %b2 br label %b2
b2: ; preds = %b2, %b1 b2: ; preds = %b2, %b1
%v6 = phi i32 [ %v5, %b1 ], [ %v7, %b2 ] %v6 = phi i32 [ %v5, %b1 ], [ %v7, %b2 ]
%v7 = add i32 %v6, -1 %v7 = add i32 %v6, -1
%v8 = icmp sgt i32 %v7, -1 %v8 = icmp sgt i32 %v7, -1
br i1 %v8, label %b2, label %b3 br i1 %v8, label %b2, label %b3
b3: ; preds = %b2, %b0 b3: ; preds = %b2, %b0
ret void ret void
} }
attributes #0 = { nounwind optsize readonly } attributes #0 = { nounwind optsize readonly }

llvm/test/CodeGen/Hexagon/hwloop-swap.ll

; RUN: llc -march=hexagon < %s | FileCheck %s ; RUN: llc -march=hexagon < %s | FileCheck %s
; Test that the hardware loop pass does not alter the comparison ; Test that the hardware loop pass does not alter the comparison
; to use the result from the induction expression instead of ; to use the result from the induction expression instead of
; from the Phi. ; from the Phi.
; CHECK: cmpb.gtu([[REG0:r[0-9]+]] ; CHECK: cmpb.gtu([[REG0:r[0-9]+]]
; CHECK: [[REG0]] = add([[REG0]], ; CHECK: [[REG0]] = add([[REG0]],
define void @f0() #0 { define void @f0(i1 %c0) #0 {
b0: b0:
br label %b1 br label %b1
b1: ; preds = %b1, %b0 b1: ; preds = %b1, %b0
br i1 undef, label %b1, label %b2 br i1 %c0, label %b1, label %b2
b2: ; preds = %b2, %b1 b2: ; preds = %b2, %b1
%v0 = phi i32 [ %v3, %b2 ], [ undef, %b1 ] %v0 = phi i32 [ %v3, %b2 ], [ undef, %b1 ]
%v1 = trunc i32 %v0 to i8 %v1 = trunc i32 %v0 to i8
%v2 = icmp ugt i8 %v1, 44 %v2 = icmp ugt i8 %v1, 44
%v3 = add i32 %v0, -30 %v3 = add i32 %v0, -30
br i1 %v2, label %b2, label %b3 br i1 %v2, label %b2, label %b3
b3: ; preds = %b2 b3: ; preds = %b2
ret void ret void
} }
attributes #0 = { nounwind "target-cpu"="hexagonv55" } attributes #0 = { nounwind "target-cpu"="hexagonv55" }

llvm/test/CodeGen/Hexagon/hwloop-wrap2.ll

; RUN: llc -march=hexagon -mcpu=hexagonv5 -O3 < %s | FileCheck %s ; RUN: llc -march=hexagon -mcpu=hexagonv5 -O3 < %s | FileCheck %s
; Test that we do not generate a hardware loop due to a potential underflow. ; Test that we do not generate a hardware loop due to a potential underflow.
; CHECK-NOT: loop0 ; CHECK-NOT: loop0
%struct.3 = type { ptr, i8, i8, i32, i32, i16, i16, i16, i16, i16, i16, i16, ptr } %struct.3 = type { ptr, i8, i8, i32, i32, i16, i16, i16, i16, i16, i16, i16, ptr }
%struct.2 = type { i16, i16, i16, i16, ptr } %struct.2 = type { i16, i16, i16, i16, ptr }
%struct.1 = type { ptr, ptr, i32, i32, i16, [2 x i16], [2 x i16], i16 } %struct.1 = type { ptr, ptr, i32, i32, i16, [2 x i16], [2 x i16], i16 }
%struct.0 = type { ptr, i32, i32, i32, i32, i32, i32, i16, i16, i16, i8, i8, i8, i8 } %struct.0 = type { ptr, i32, i32, i32, i32, i32, i32, i16, i16, i16, i8, i8, i8, i8 }
@pairArray = external global ptr @pairArray = external global ptr
@carray = external global ptr @carray = external global ptr
define void @test() #0 { define void @test(i1 %c0, i1 %c1, i1 %c2) #0 {
entry: entry:
%0 = load ptr, ptr @pairArray, align 4 %0 = load ptr, ptr @pairArray, align 4
%1 = load ptr, ptr @carray, align 4 %1 = load ptr, ptr @carray, align 4
br i1 undef, label %for.end110, label %for.body br i1 %c0, label %for.end110, label %for.body
for.body: for.body:
%row.0199 = phi i32 [ %inc109, %for.inc108 ], [ 1, %entry ] %row.0199 = phi i32 [ %inc109, %for.inc108 ], [ 1, %entry ]
%arrayidx = getelementptr inbounds ptr, ptr %0, i32 %row.0199 %arrayidx = getelementptr inbounds ptr, ptr %0, i32 %row.0199
%2 = load ptr, ptr %arrayidx, align 4 %2 = load ptr, ptr %arrayidx, align 4
br i1 undef, label %for.body48, label %for.inc108 br i1 %c1, label %for.body48, label %for.inc108
for.cond45: for.cond45:
%cmp46 = icmp sgt i32 %dec58, 0 %cmp46 = icmp sgt i32 %dec58, 0
br i1 %cmp46, label %for.body48, label %for.inc108 br i1 %cmp46, label %for.body48, label %for.inc108
for.body48: for.body48:
%i.1190 = phi i32 [ %dec58, %for.cond45 ], [ 0, %for.body ] %i.1190 = phi i32 [ %dec58, %for.cond45 ], [ 0, %for.body ]
%arrayidx50 = getelementptr inbounds i32, ptr %2, i32 %i.1190 %arrayidx50 = getelementptr inbounds i32, ptr %2, i32 %i.1190
Show All 21 Linesfor.body80:
%6 = load i32, ptr %arrayidx81, align 4 %6 = load i32, ptr %arrayidx81, align 4
%arrayidx87 = getelementptr inbounds i32, ptr %2, i32 %j.1196.in %arrayidx87 = getelementptr inbounds i32, ptr %2, i32 %j.1196.in
store i32 %6, ptr %arrayidx87, align 4 store i32 %6, ptr %arrayidx87, align 4
%exitcond = icmp eq i32 %j.1196, 0 %exitcond = icmp eq i32 %j.1196, 0
br i1 %exitcond, label %for.inc108, label %for.body80 br i1 %exitcond, label %for.inc108, label %for.body80
for.inc108: for.inc108:
%inc109 = add nsw i32 %row.0199, 1 %inc109 = add nsw i32 %row.0199, 1
br i1 undef, label %for.body, label %for.end110 br i1 %c2, label %for.body, label %for.end110
for.end110: for.end110:
ret void ret void
} }

llvm/test/CodeGen/Hexagon/ignore-terminal-mbb.ll

; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s ; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s
; CHECK-NOT: if{{.*}}jump{{.*}}-1 ; CHECK-NOT: if{{.*}}jump{{.*}}-1
; CHECK: memw ; CHECK: memw
target triple = "hexagon" target triple = "hexagon"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0() #0 { define void @f0(i1 %c0, i1 %c1) #0 {
b0: b0:
br i1 undef, label %b2, label %b1 br i1 %c0, label %b2, label %b1
b1: ; preds = %b0 b1: ; preds = %b0
store i32 0, ptr undef, align 4, !tbaa !0 store i32 0, ptr undef, align 4, !tbaa !0
unreachable unreachable
b2: ; preds = %b0 b2: ; preds = %b0
br i1 undef, label %b4, label %b3 br i1 %c1, label %b4, label %b3
b3: ; preds = %b2 b3: ; preds = %b2
%v0 = or i32 undef, 2048 %v0 = or i32 undef, 2048
br label %b4 br label %b4
b4: ; preds = %b3, %b2 b4: ; preds = %b3, %b2
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }
!0 = !{!1, !1, i64 0} !0 = !{!1, !1, i64 0}
!1 = !{!"int", !2, i64 0} !1 = !{!"int", !2, i64 0}
!2 = !{!"omnipotent char", !3, i64 0} !2 = !{!"omnipotent char", !3, i64 0}
!3 = !{!"Simple C/C++ TBAA"} !3 = !{!"Simple C/C++ TBAA"}

llvm/test/CodeGen/Hexagon/invalid-memrefs.ll

; RUN: llc -O2 -march=hexagon -hexagon-expand-condsets=0 < %s ; RUN: llc -O2 -march=hexagon -hexagon-expand-condsets=0 < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Disable expand-condsets because it will assert on undefined registers.
target triple = "hexagon-unknown--elf" target triple = "hexagon-unknown--elf"
%s.0 = type { ptr, ptr } %s.0 = type { ptr, ptr }
%s.1 = type { ptr, ptr } %s.1 = type { ptr, ptr }
@g0 = external global %s.0, align 4 @g0 = external global %s.0, align 4
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0() #0 { define void @f0(i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, i1 %c10, i1 %c11, i1 %c12) #0 {
b0: b0:
br i1 undef, label %b2, label %b1 br i1 %c0, label %b2, label %b1
b1: ; preds = %b0 b1: ; preds = %b0
unreachable unreachable
b2: ; preds = %b0 b2: ; preds = %b0
br i1 undef, label %b26, label %b3 br i1 %c1, label %b26, label %b3
b3: ; preds = %b2 b3: ; preds = %b2
br i1 undef, label %b6, label %b4 br i1 %c2, label %b6, label %b4
b4: ; preds = %b3 b4: ; preds = %b3
br i1 undef, label %b5, label %b26 br i1 %c3, label %b5, label %b26
b5: ; preds = %b4 b5: ; preds = %b4
br i1 undef, label %b7, label %b26 br i1 %c4, label %b7, label %b26
b6: ; preds = %b3 b6: ; preds = %b3
br label %b7 br label %b7
b7: ; preds = %b6, %b5 b7: ; preds = %b6, %b5
br i1 undef, label %b11, label %b8 br i1 %c5, label %b11, label %b8
b8: ; preds = %b7 b8: ; preds = %b7
br i1 undef, label %b10, label %b9 br i1 %c6, label %b10, label %b9
b9: ; preds = %b8 b9: ; preds = %b8
unreachable unreachable
b10: ; preds = %b8 b10: ; preds = %b8
unreachable unreachable
b11: ; preds = %b7 b11: ; preds = %b7
br i1 undef, label %b25, label %b12 br i1 %c7, label %b25, label %b12
b12: ; preds = %b11 b12: ; preds = %b11
br i1 undef, label %b14, label %b13 br i1 %c8, label %b14, label %b13
b13: ; preds = %b12 b13: ; preds = %b12
br label %b14 br label %b14
b14: ; preds = %b13, %b12 b14: ; preds = %b13, %b12
br i1 undef, label %b15, label %b16 br i1 %c9, label %b15, label %b16
b15: ; preds = %b14 b15: ; preds = %b14
br label %b16 br label %b16
b16: ; preds = %b15, %b14 b16: ; preds = %b15, %b14
br i1 undef, label %b18, label %b17 br i1 %c10, label %b18, label %b17
b17: ; preds = %b16 b17: ; preds = %b16
unreachable unreachable
b18: ; preds = %b16 b18: ; preds = %b16
%v0 = load ptr, ptr getelementptr inbounds (%s.0, ptr @g0, i32 0, i32 1), align 4 %v0 = load ptr, ptr getelementptr inbounds (%s.0, ptr @g0, i32 0, i32 1), align 4
%v1 = load ptr, ptr @g0, align 4 %v1 = load ptr, ptr @g0, align 4
%v2 = select i1 undef, ptr %v0, ptr %v1 %v2 = select i1 undef, ptr %v0, ptr %v1
br i1 undef, label %b22, label %b19 br i1 %c11, label %b22, label %b19
b19: ; preds = %b18 b19: ; preds = %b18
%v3 = load ptr, ptr undef, align 4 %v3 = load ptr, ptr undef, align 4
%v4 = icmp eq ptr %v3, null %v4 = icmp eq ptr %v3, null
br i1 %v4, label %b21, label %b20 br i1 %v4, label %b21, label %b20
b20: ; preds = %b19 b20: ; preds = %b19
store ptr undef, ptr undef, align 4 store ptr undef, ptr undef, align 4
br label %b21 br label %b21
b21: ; preds = %b20, %b19 b21: ; preds = %b20, %b19
br label %b22 br label %b22
b22: ; preds = %b21, %b18 b22: ; preds = %b21, %b18
br i1 undef, label %b24, label %b23 br i1 %c12, label %b24, label %b23
b23: ; preds = %b22 b23: ; preds = %b22
store ptr %v2, ptr undef, align 4 store ptr %v2, ptr undef, align 4
br label %b24 br label %b24
b24: ; preds = %b23, %b22 b24: ; preds = %b23, %b22
unreachable unreachable
b25: ; preds = %b11 b25: ; preds = %b11
unreachable unreachable
b26: ; preds = %b5, %b4, %b2 b26: ; preds = %b5, %b4, %b2
ret void ret void
} }
attributes #0 = { nounwind "target-cpu"="hexagonv55" } attributes #0 = { nounwind "target-cpu"="hexagonv55" }

llvm/test/CodeGen/Hexagon/is-legal-void.ll

; RUN: llc -march=hexagon < %s ; RUN: llc -march=hexagon < %s
; REQUIRES: asserts ; REQUIRES: asserts
; The two loads based on %struct.0, loading two different data types ; The two loads based on %struct.0, loading two different data types
; cause LSR to assume type "void" for the memory type. This would then ; cause LSR to assume type "void" for the memory type. This would then
; cause an assert in isLegalAddressingMode. Make sure we no longer crash. ; cause an assert in isLegalAddressingMode. Make sure we no longer crash.
target triple = "hexagon" target triple = "hexagon"
%struct.0 = type { ptr, i8, %union.anon.0 } %struct.0 = type { ptr, i8, %union.anon.0 }
%union.anon.0 = type { ptr } %union.anon.0 = type { ptr }
define hidden fastcc void @fred() unnamed_addr #0 { define hidden fastcc void @fred(i1 %c0) unnamed_addr #0 {
entry: entry:
br i1 undef, label %while.end, label %while.body.lr.ph br i1 %c0, label %while.end, label %while.body.lr.ph
while.body.lr.ph: ; preds = %entry while.body.lr.ph: ; preds = %entry
br label %while.body br label %while.body
while.body: ; preds = %exit.2, %while.body.lr.ph while.body: ; preds = %exit.2, %while.body.lr.ph
%lsr.iv = phi ptr [ %cgep22, %exit.2 ], [ undef, %while.body.lr.ph ] %lsr.iv = phi ptr [ %cgep22, %exit.2 ], [ undef, %while.body.lr.ph ]
switch i32 undef, label %exit [ switch i32 undef, label %exit [
i32 1, label %sw.bb.i i32 1, label %sw.bb.i
Show All 33 Lines

llvm/test/CodeGen/Hexagon/isel-simplify-crash.ll

; RUN: llc -march=hexagon -hexagon-instsimplify=0 < %s | FileCheck %s ; RUN: llc -march=hexagon -hexagon-instsimplify=0 < %s | FileCheck %s
; This used to crash in SimplifyDemandedBits due to a type mismatch ; This used to crash in SimplifyDemandedBits due to a type mismatch
; caused by a missing bitcast in vectorizing mul. ; caused by a missing bitcast in vectorizing mul.
; CHECK: vmpy ; CHECK: vmpy
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon" target triple = "hexagon"
define void @fred(i16 signext %a0, ptr %a1, <32 x i16> %a3) #0 { define void @fred(i16 signext %a0, ptr %a1, <32 x i16> %a3, i1 %c0) #0 {
b1: b1:
%v4 = add i16 undef, %a0 %v4 = add i16 undef, %a0
br i1 undef, label %b11, label %b5 br i1 %c0, label %b11, label %b5
b5: ; preds = %b1 b5: ; preds = %b1
%v6 = insertelement <32 x i16> undef, i16 %v4, i32 0 %v6 = insertelement <32 x i16> undef, i16 %v4, i32 0
%v7 = shufflevector <32 x i16> %v6, <32 x i16> undef, <32 x i32> zeroinitializer %v7 = shufflevector <32 x i16> %v6, <32 x i16> undef, <32 x i32> zeroinitializer
%v8 = add <32 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 16, i16 17, i16 18, i16 19, i16 20, i16 21, i16 22, i16 23, i16 24, i16 25, i16 26, i16 27, i16 28, i16 29, i16 30, i16 31>, <i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256> %v8 = add <32 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 16, i16 17, i16 18, i16 19, i16 20, i16 21, i16 22, i16 23, i16 24, i16 25, i16 26, i16 27, i16 28, i16 29, i16 30, i16 31>, <i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256>
%v9 = mul <32 x i16> %v8, %a3 %v9 = mul <32 x i16> %v8, %a3
%v10 = add <32 x i16> %v7, %v9 %v10 = add <32 x i16> %v7, %v9
store <32 x i16> %v10, ptr %a1, align 2 store <32 x i16> %v10, ptr %a1, align 2
ret void ret void
b11: ; preds = %b1 b11: ; preds = %b1
ret void ret void
} }
attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" } attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" }

llvm/test/CodeGen/Hexagon/isel-v3i16.ll

; RUN: llc -march=hexagon < %s | FileCheck %s ; RUN: llc -march=hexagon < %s | FileCheck %s
; Check for a successful compilation. ; Check for a successful compilation.
; CHECK: callr ; CHECK: callr
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon" target triple = "hexagon"
@g0 = external dllexport global ptr, align 4 @g0 = external dllexport global ptr, align 4
define hidden void @f0(i32 %a0, ptr %a1) #0 { define hidden void @f0(i32 %a0, ptr %a1, i1 %c0) #0 {
b0: b0:
%v0 = load ptr, ptr @g0, align 4 %v0 = load ptr, ptr @g0, align 4
%v1 = call ptr %v0(i32 1, i32 %a0, i64 314646, i32 0, i32 16) %v1 = call ptr %v0(i32 1, i32 %a0, i64 314646, i32 0, i32 16)
br label %b1 br label %b1
b1: ; preds = %b2, %b0 b1: ; preds = %b2, %b0
br label %b2 br label %b2
b2: ; preds = %b5, %b1 b2: ; preds = %b5, %b1
%v2 = icmp slt i32 0, 229 %v2 = icmp slt i32 0, 229
br i1 %v2, label %b3, label %b1 br i1 %v2, label %b3, label %b1
b3: ; preds = %b2 b3: ; preds = %b2
br i1 undef, label %b4, label %b5 br i1 %c0, label %b4, label %b5
b4: ; preds = %b3 b4: ; preds = %b3
%v3 = load <3 x i16>, ptr %a1, align 2 %v3 = load <3 x i16>, ptr %a1, align 2
br label %b5 br label %b5
b5: ; preds = %b4, %b3 b5: ; preds = %b4, %b3
%v4 = phi <3 x i16> [ %v3, %b4 ], [ zeroinitializer, %b3 ] %v4 = phi <3 x i16> [ %v3, %b4 ], [ zeroinitializer, %b3 ]
%v6 = getelementptr inbounds i16, ptr %v1, i32 undef %v6 = getelementptr inbounds i16, ptr %v1, i32 undef
store <3 x i16> %v4, ptr %v6, align 2 store <3 x i16> %v4, ptr %v6, align 2
br label %b2 br label %b2
} }
attributes #0 = { "target-cpu"="hexagonv68" } attributes #0 = { "target-cpu"="hexagonv68" }

llvm/test/CodeGen/Hexagon/loop-idiom/lcssa.ll

; RUN: opt -S -hexagon-loop-idiom < %s | opt -S -passes='loop(loop-deletion),gvn' ; RUN: opt -S -hexagon-loop-idiom < %s | opt -S -passes='loop(loop-deletion),gvn'
; REQUIRES: asserts ; REQUIRES: asserts
; This tests that the HexagonLoopIdiom pass does not mark LCSSA information ; This tests that the HexagonLoopIdiom pass does not mark LCSSA information
; as preserved. The pass calls SimplifyInstruction is a couple of places, ; as preserved. The pass calls SimplifyInstruction is a couple of places,
; which can invalidate LCSSA. Specifically, the uses of a LCSSA phi variable ; which can invalidate LCSSA. Specifically, the uses of a LCSSA phi variable
; are replaced by the incoming value. ; are replaced by the incoming value.
define hidden void @test() local_unnamed_addr #0 { define hidden void @test(i1 %c0, i1 %c1, i1 %c2, i1 %c3) local_unnamed_addr #0 {
entry: entry:
br label %if.then63 br label %if.then63
if.then63: if.then63:
br i1 undef, label %do.body311, label %if.end375 br i1 %c0, label %do.body311, label %if.end375
do.body311: do.body311:
br i1 undef, label %do.end318, label %do.body311 br i1 %c1, label %do.end318, label %do.body311
do.end318: do.end318:
br i1 undef, label %if.end322, label %if.end375 br i1 %c2, label %if.end322, label %if.end375
if.end322: if.end322:
%sub325 = sub i32 undef, undef %sub325 = sub i32 undef, undef
br i1 undef, label %do.end329, label %do.body311 br i1 %c3, label %do.end329, label %do.body311
do.end329: do.end329:
%sub325.lcssa = phi i32 [ %sub325, %if.end322 ] %sub325.lcssa = phi i32 [ %sub325, %if.end322 ]
br label %do.body330 br label %do.body330
do.body330: do.body330:
%row_width.7 = phi i32 [ %sub325.lcssa, %do.end329 ], [ %dec334, %do.body330 ] %row_width.7 = phi i32 [ %sub325.lcssa, %do.end329 ], [ %dec334, %do.body330 ]
%sp.5 = phi ptr [ undef, %do.end329 ], [ %incdec.ptr331, %do.body330 ] %sp.5 = phi ptr [ undef, %do.end329 ], [ %incdec.ptr331, %do.body330 ]
Show All 14 Lines

llvm/test/CodeGen/Hexagon/loop-idiom/nullptr-crash.ll

; RUN: opt -hexagon-loop-idiom -mtriple hexagon-unknown-elf < %s ; RUN: opt -hexagon-loop-idiom -mtriple hexagon-unknown-elf < %s
; REQUIRES: asserts ; REQUIRES: asserts
target triple = "hexagon" target triple = "hexagon"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @fred(i8 zeroext %L) #0 { define void @fred(i8 zeroext %L, i1 %c0, i1 %c1) #0 {
entry: entry:
br i1 undef, label %if.end53, label %while.body37 br i1 %c0, label %if.end53, label %while.body37
while.body37: ; preds = %while.body37, %entry while.body37: ; preds = %while.body37, %entry
%i.121 = phi i32 [ %inc46, %while.body37 ], [ 0, %entry ] %i.121 = phi i32 [ %inc46, %while.body37 ], [ 0, %entry ]
%shl = shl i32 1, %i.121 %shl = shl i32 1, %i.121
%and39 = and i32 %shl, undef %and39 = and i32 %shl, undef
%tobool40 = icmp eq i32 %and39, 0 %tobool40 = icmp eq i32 %and39, 0
%inc46 = add nuw nsw i32 %i.121, 1 %inc46 = add nuw nsw i32 %i.121, 1
%storemerge = select i1 %tobool40, i8 %L, i8 0 %storemerge = select i1 %tobool40, i8 %L, i8 0
br i1 undef, label %while.body37, label %if.end53 br i1 %c1, label %while.body37, label %if.end53
if.end53: ; preds = %while.body37, %entry if.end53: ; preds = %while.body37, %entry
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-long-loop.ll

; RUN: opt -march=hexagon -hexagon-loop-idiom -S < %s | FileCheck %s ; RUN: opt -march=hexagon -hexagon-loop-idiom -S < %s | FileCheck %s
; ;
; The number of nested selects caused the simplification loop to take ; The number of nested selects caused the simplification loop to take
; more than the maximum number of iterations. This caused the compiler ; more than the maximum number of iterations. This caused the compiler
; to crash under suspicion of an infinite loop. This (still reduced) ; to crash under suspicion of an infinite loop. This (still reduced)
; testcase shows a legitimate case where this limit was exceeded. ; testcase shows a legitimate case where this limit was exceeded.
; Instead of crashing, gracefully abort the simplification. ; Instead of crashing, gracefully abort the simplification.
; ;
; Check for sane output. ; Check for sane output.
; CHECK: define void @fred
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon" target triple = "hexagon"
define void @fred() unnamed_addr #0 { define void @fred(i1 %c0) unnamed_addr #0 {
b0: b0:
%v1 = select i1 false, i32 undef, i32 2 %v1 = select i1 false, i32 undef, i32 2
br label %b2 br label %b2
b2: ; preds = %b2, %b0 b2: ; preds = %b2, %b0
%v3 = sext i16 undef to i32 %v3 = sext i16 undef to i32
%v4 = add nsw i32 %v1, %v3 %v4 = add nsw i32 %v1, %v3
%v5 = select i1 undef, i32 undef, i32 %v4 %v5 = select i1 undef, i32 undef, i32 %v4
Show All 24 Linesb2: ; preds = %b2, %b0
%v30 = add i32 undef, %v29 %v30 = add i32 undef, %v29
%v31 = add i32 %v11, undef %v31 = add i32 %v11, undef
%v32 = add i32 %v31, undef %v32 = add i32 %v31, undef
%v33 = add i32 %v32, %v19 %v33 = add i32 %v32, %v19
%v34 = add i32 %v33, %v30 %v34 = add i32 %v33, %v30
%v35 = add nsw i32 %v34, 32768 %v35 = add nsw i32 %v34, 32768
%v36 = icmp ult i32 %v35, 65536 %v36 = icmp ult i32 %v35, 65536
%v37 = select i1 %v36, i32 %v34, i32 undef %v37 = select i1 %v36, i32 %v34, i32 undef
br i1 undef, label %b2, label %b38 br i1 %c0, label %b2, label %b38
b38: ; preds = %b2 b38: ; preds = %b2
unreachable unreachable
} }
attributes #0 = { "target-cpu"="hexagonv60" } attributes #0 = { "target-cpu"="hexagonv60" }

llvm/test/CodeGen/Hexagon/machine-sink.ll

; RUN: llc -march=hexagon -machine-sink-split < %s ; RUN: llc -march=hexagon -machine-sink-split < %s
; REQUIRES: asserts ; REQUIRES: asserts
; MachineSink should not sink an MI which is used in a non-phi instruction ; MachineSink should not sink an MI which is used in a non-phi instruction
; in an MBB with multiple predecessors. ; in an MBB with multiple predecessors.
target triple = "hexagon-unknown--elf" target triple = "hexagon-unknown--elf"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0() #0 { define void @f0(i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6) #0 {
b0: b0:
br i1 undef, label %b1, label %b2 br i1 %c0, label %b1, label %b2
b1: ; preds = %b0 b1: ; preds = %b0
unreachable unreachable
b2: ; preds = %b0 b2: ; preds = %b0
%v0 = load ptr, ptr undef, align 4 %v0 = load ptr, ptr undef, align 4
%v1 = getelementptr inbounds i8, ptr %v0, i32 1 %v1 = getelementptr inbounds i8, ptr %v0, i32 1
%v2 = load i8, ptr %v0, align 1, !tbaa !0 %v2 = load i8, ptr %v0, align 1, !tbaa !0
%v3 = zext i8 %v2 to i32 %v3 = zext i8 %v2 to i32
%v4 = shl nuw nsw i32 %v3, 8 %v4 = shl nuw nsw i32 %v3, 8
br i1 undef, label %b3, label %b5 br i1 %c1, label %b3, label %b5
b3: ; preds = %b2 b3: ; preds = %b2
br i1 undef, label %b15, label %b4 br i1 %c2, label %b15, label %b4
b4: ; preds = %b3 b4: ; preds = %b3
br label %b5 br label %b5
b5: ; preds = %b4, %b2 b5: ; preds = %b4, %b2
%v5 = phi ptr [ undef, %b4 ], [ %v1, %b2 ] %v5 = phi ptr [ undef, %b4 ], [ %v1, %b2 ]
%v6 = load i8, ptr %v5, align 1, !tbaa !0 %v6 = load i8, ptr %v5, align 1, !tbaa !0
%v7 = zext i8 %v6 to i32 %v7 = zext i8 %v6 to i32
%v8 = add nsw i32 %v7, %v4 %v8 = add nsw i32 %v7, %v4
%v9 = add nsw i32 %v8, -2 %v9 = add nsw i32 %v8, -2
br label %b6 br label %b6
b6: ; preds = %b8, %b5 b6: ; preds = %b8, %b5
br i1 false, label %b7, label %b8 br i1 false, label %b7, label %b8
b7: ; preds = %b6 b7: ; preds = %b6
unreachable unreachable
b8: ; preds = %b6 b8: ; preds = %b6
br i1 undef, label %b6, label %b9 br i1 %c3, label %b6, label %b9
b9: ; preds = %b8 b9: ; preds = %b8
br i1 undef, label %b10, label %b14 br i1 %c4, label %b10, label %b14
b10: ; preds = %b9 b10: ; preds = %b9
br i1 undef, label %b11, label %b13 br i1 %c5, label %b11, label %b13
b11: ; preds = %b10 b11: ; preds = %b10
br i1 undef, label %b12, label %b13 br i1 %c6, label %b12, label %b13
b12: ; preds = %b11 b12: ; preds = %b11
unreachable unreachable
b13: ; preds = %b11, %b10 b13: ; preds = %b11, %b10
store i32 %v9, ptr undef, align 4, !tbaa !3 store i32 %v9, ptr undef, align 4, !tbaa !3
unreachable unreachable
Show All 14 Lines

llvm/test/CodeGen/Hexagon/mipi-double-small.ll

; RUN: llc -march=hexagon < %s ; RUN: llc -march=hexagon < %s
; REQUIRES: asserts ; REQUIRES: asserts
target triple = "hexagon" target triple = "hexagon"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0() #0 { define void @f0(i1 %c0) #0 {
b0: b0:
br label %b1 br label %b1
b1: ; preds = %b0 b1: ; preds = %b0
br i1 undef, label %b2, label %b3 br i1 %c0, label %b2, label %b3
b2: ; preds = %b1 b2: ; preds = %b1
%v0 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> undef) %v0 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> undef)
store <32 x i32> %v0, ptr undef, align 128 store <32 x i32> %v0, ptr undef, align 128
unreachable unreachable
b3: ; preds = %b1 b3: ; preds = %b1
ret void ret void
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #1 declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #1
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" } attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }

llvm/test/CodeGen/Hexagon/newvalueSameReg.ll

Show All 12 Lines
%s.1 = type { i32, i16, i16 } %s.1 = type { i32, i16, i16 }
@g0 = external global %s.0 @g0 = external global %s.0
@g1 = external unnamed_addr constant [23 x i8], align 8 @g1 = external unnamed_addr constant [23 x i8], align 8
; Function Attrs: nounwind ; Function Attrs: nounwind
declare void @f0(ptr nocapture, ptr nocapture readonly, ...) #0 declare void @f0(ptr nocapture, ptr nocapture readonly, ...) #0
define void @f1() #1 { define void @f1(i1 %c0, i1 %c1, i1 %c2) #1 {
b0: b0:
%v0 = load ptr, ptr undef, align 4 %v0 = load ptr, ptr undef, align 4
%v1 = load i32, ptr undef, align 4 %v1 = load i32, ptr undef, align 4
br i1 undef, label %b4, label %b1 br i1 %c0, label %b4, label %b1
b1: ; preds = %b0 b1: ; preds = %b0
%v2 = icmp slt i32 %v1, 0 %v2 = icmp slt i32 %v1, 0
%v3 = lshr i32 %v1, 5 %v3 = lshr i32 %v1, 5
%v4 = add i32 %v3, -134217728 %v4 = add i32 %v3, -134217728
%v5 = select i1 %v2, i32 %v4, i32 %v3 %v5 = select i1 %v2, i32 %v4, i32 %v3
%v6 = getelementptr inbounds i32, ptr %v0, i32 %v5 %v6 = getelementptr inbounds i32, ptr %v0, i32 %v5
%v7 = icmp ult ptr %v6, %v0 %v7 = icmp ult ptr %v6, %v0
%v8 = select i1 %v7, i32 0, i32 1 %v8 = select i1 %v7, i32 0, i32 1
br i1 undef, label %b2, label %b4 br i1 %c1, label %b2, label %b4
b2: ; preds = %b1 b2: ; preds = %b1
%v9 = icmp slt i32 %v1, 0 %v9 = icmp slt i32 %v1, 0
%v10 = lshr i32 %v1, 5 %v10 = lshr i32 %v1, 5
%v11 = add i32 %v10, -134217728 %v11 = add i32 %v10, -134217728
%v12 = select i1 %v9, i32 %v11, i32 %v10 %v12 = select i1 %v9, i32 %v11, i32 %v10
%v13 = getelementptr inbounds i32, ptr %v0, i32 %v12 %v13 = getelementptr inbounds i32, ptr %v0, i32 %v12
%v14 = icmp ult ptr %v13, %v0 %v14 = icmp ult ptr %v13, %v0
%v15 = select i1 %v14, i32 0, i32 1 %v15 = select i1 %v14, i32 0, i32 1
%v16 = icmp eq i32 %v8, %v15 %v16 = icmp eq i32 %v8, %v15
br i1 %v16, label %b4, label %b3 br i1 %v16, label %b4, label %b3
b3: ; preds = %b2 b3: ; preds = %b2
call void (ptr, ptr, ...) @f0(ptr @g0, ptr @g1, i32 %v8, i32 %v15) #0 call void (ptr, ptr, ...) @f0(ptr @g0, ptr @g1, i32 %v8, i32 %v15) #0
unreachable unreachable
b4: ; preds = %b2, %b1, %b0 b4: ; preds = %b2, %b1, %b0
br i1 undef, label %b6, label %b5 br i1 %c2, label %b6, label %b5
b5: ; preds = %b4 b5: ; preds = %b4
unreachable unreachable
b6: ; preds = %b4 b6: ; preds = %b4
ret void ret void
} }
attributes #0 = { nounwind "target-cpu"="hexagonv5" } attributes #0 = { nounwind "target-cpu"="hexagonv5" }
attributes #1 = { "target-cpu"="hexagonv5" } attributes #1 = { "target-cpu"="hexagonv5" }

llvm/test/CodeGen/Hexagon/newvaluejump-kill.ll

; RUN: llc -march=hexagon -O3 -verify-machineinstrs -hexagon-initial-cfg-cleanup=0 -hexagon-instsimplify=0 < %s | FileCheck %s ; RUN: llc -march=hexagon -O3 -verify-machineinstrs -hexagon-initial-cfg-cleanup=0 -hexagon-instsimplify=0 < %s | FileCheck %s
; ;
; Check that this testcase compiles successfully and that a new-value jump ; Check that this testcase compiles successfully and that a new-value jump
; has been created. ; has been created.
; CHECK: if (cmp.gtu(r{{[0-9]+}}.new,r{{[0-9]+}})) jump ; CHECK: if (cmp.gtu(r{{[0-9]+}}.new,r{{[0-9]+}})) jump
target triple = "hexagon" target triple = "hexagon"
@g0 = external hidden unnamed_addr global [182 x i16], align 8 @g0 = external hidden unnamed_addr global [182 x i16], align 8
define void @fred(i16 signext %a0, i16 signext %a1) #0 { define void @fred(i16 signext %a0, i16 signext %a1, i1 %c0, i1 %c1) #0 {
b1: b1:
%v1 = sext i16 %a0 to i32 %v1 = sext i16 %a0 to i32
%v2 = getelementptr inbounds [182 x i16], ptr @g0, i32 0, i32 %v1 %v2 = getelementptr inbounds [182 x i16], ptr @g0, i32 0, i32 %v1
%v3 = sext i16 %a1 to i32 %v3 = sext i16 %a1 to i32
%v4 = call i32 @llvm.hexagon.A2.asrh(i32 undef) %v4 = call i32 @llvm.hexagon.A2.asrh(i32 undef)
%v5 = trunc i32 %v4 to i16 %v5 = trunc i32 %v4 to i16
br i1 undef, label %b6, label %b14 br i1 %c0, label %b6, label %b14
b6: ; preds = %b1 b6: ; preds = %b1
%v7 = sext i16 %v5 to i32 %v7 = sext i16 %v5 to i32
br label %b8 br label %b8
b8: ; preds = %b8, %b6 b8: ; preds = %b8, %b6
%v9 = phi i32 [ 128, %b6 ], [ %v13, %b8 ] %v9 = phi i32 [ 128, %b6 ], [ %v13, %b8 ]
%v10 = sub nsw i32 %v9, %v7 %v10 = sub nsw i32 %v9, %v7
%v11 = getelementptr inbounds [182 x i16], ptr @g0, i32 0, i32 %v10 %v11 = getelementptr inbounds [182 x i16], ptr @g0, i32 0, i32 %v10
%v12 = load i16, ptr %v11, align 2 %v12 = load i16, ptr %v11, align 2
%v13 = add nuw nsw i32 %v9, 1 %v13 = add nuw nsw i32 %v9, 1
br label %b8 br label %b8
b14: ; preds = %b1 b14: ; preds = %b1
br i1 undef, label %b16, label %b15 br i1 %c1, label %b16, label %b15
b15: ; preds = %b14 b15: ; preds = %b14
unreachable unreachable
b16: ; preds = %b14 b16: ; preds = %b14
%v17 = getelementptr [182 x i16], ptr @g0, i32 0, i32 %v3 %v17 = getelementptr [182 x i16], ptr @g0, i32 0, i32 %v3
%v18 = icmp ugt ptr %v17, %v2 %v18 = icmp ugt ptr %v17, %v2
%v19 = or i1 %v18, undef %v19 = or i1 %v18, undef
Show All 13 Lines

llvm/test/CodeGen/Hexagon/newvaluejump3.ll

; RUN: llc -march=hexagon -filetype=obj -o /dev/null < %s ; RUN: llc -march=hexagon -filetype=obj -o /dev/null < %s
; REQUIRES: asserts ; REQUIRES: asserts
; This crashed in the MC code emitter, because a new-value branch was created ; This crashed in the MC code emitter, because a new-value branch was created
; with IMPLICIT_DEF as the producer. ; with IMPLICIT_DEF as the producer.
target triple = "hexagon" target triple = "hexagon"
%type.0 = type { %type.1, [64 x i8] } %type.0 = type { %type.1, [64 x i8] }
%type.1 = type { [12 x i8], ptr, double } %type.1 = type { [12 x i8], ptr, double }
%type.2 = type { i16, i16, [1 x %type.3] } %type.2 = type { i16, i16, [1 x %type.3] }
%type.3 = type { i32 } %type.3 = type { i32 }
%type.4 = type { ptr, i32 } %type.4 = type { ptr, i32 }
define hidden fastcc ptr @fred(ptr nocapture readonly %a0, ptr readonly %a1) unnamed_addr #2 { define hidden fastcc ptr @fred(ptr nocapture readonly %a0, ptr readonly %a1, i1 %c0, i1 %c1) unnamed_addr #2 {
b2: b2:
%v3 = load i8, ptr %a1, align 1 %v3 = load i8, ptr %a1, align 1
br i1 undef, label %b4, label %b24 br i1 %c0, label %b4, label %b24
b4: ; preds = %b2 b4: ; preds = %b2
switch i8 %v3, label %b13 [ switch i8 %v3, label %b13 [
i8 25, label %b5 i8 25, label %b5
i8 26, label %b6 i8 26, label %b6
i8 28, label %b8 i8 28, label %b8
i8 27, label %b9 i8 27, label %b9
i8 43, label %b11 i8 43, label %b11
Show All 19 Lines
b12: ; preds = %b4 b12: ; preds = %b4
unreachable unreachable
b13: ; preds = %b4 b13: ; preds = %b4
br label %b14 br label %b14
b14: ; preds = %b13 b14: ; preds = %b13
br i1 undef, label %b15, label %b16 br i1 %c1, label %b15, label %b16
b15: ; preds = %b14 b15: ; preds = %b14
unreachable unreachable
b16: ; preds = %b20, %b14, %b8, %b6 b16: ; preds = %b20, %b14, %b8, %b6
%v17 = phi ptr [ %v21, %b20 ], [ undef, %b14 ], [ undef, %b8 ], [ %v7, %b6 ] %v17 = phi ptr [ %v21, %b20 ], [ undef, %b14 ], [ undef, %b8 ], [ %v7, %b6 ]
%v18 = phi i32 [ 0, %b20 ], [ undef, %b14 ], [ 0, %b8 ], [ 8, %b6 ] %v18 = phi i32 [ 0, %b20 ], [ undef, %b14 ], [ 0, %b8 ], [ 8, %b6 ]
%v19 = icmp sgt i32 %v18, 0 %v19 = icmp sgt i32 %v18, 0
Show All 17 Lines

llvm/test/CodeGen/Hexagon/opt-addr-mode-subreg-use.ll

Show All 35 Lines
; Function Attrs: optsize ; Function Attrs: optsize
declare zeroext i1 @f8(ptr, ptr, i64) #1 align 2 declare zeroext i1 @f8(ptr, ptr, i64) #1 align 2
; Function Attrs: nounwind optsize ; Function Attrs: nounwind optsize
declare ptr @f9(ptr nocapture readonly) #0 align 2 declare ptr @f9(ptr nocapture readonly) #0 align 2
; Function Attrs: optsize ; Function Attrs: optsize
define void @f10(ptr %a0, ptr dereferenceable(64) %a1) #1 align 2 { define void @f10(ptr %a0, ptr dereferenceable(64) %a1, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, i1 %c10, i1 %c11, i1 %c12, i1 %c13, i1 %c14, i1 %c15, i1 %c16) #1 align 2 {
b0: b0:
%v0 = alloca %s.0, align 4 %v0 = alloca %s.0, align 4
%v1 = alloca %s.1, align 4 %v1 = alloca %s.1, align 4
%v2 = alloca %s.2, align 4 %v2 = alloca %s.2, align 4
%v3 = alloca %s.3, align 4 %v3 = alloca %s.3, align 4
%v4 = alloca %s.4, align 4 %v4 = alloca %s.4, align 4
%v5 = alloca %s.5, align 8 %v5 = alloca %s.5, align 8
br i1 undef, label %b34, label %b1 br i1 %c0, label %b34, label %b1
b1: ; preds = %b0 b1: ; preds = %b0
br i1 undef, label %b3, label %b2 br i1 %c1, label %b3, label %b2
b2: ; preds = %b1 b2: ; preds = %b1
%v6 = ptrtoint ptr %v0 to i32 %v6 = ptrtoint ptr %v0 to i32
%v7 = zext i32 %v6 to i64 %v7 = zext i32 %v6 to i64
%v8 = shl nuw i64 %v7, 32 %v8 = shl nuw i64 %v7, 32
%v9 = or i64 %v8, zext (i32 ptrtoint (ptr @f2 to i32) to i64) %v9 = or i64 %v8, zext (i32 ptrtoint (ptr @f2 to i32) to i64)
%v10 = ptrtoint ptr %v4 to i32 %v10 = ptrtoint ptr %v4 to i32
%v11 = zext i32 %v10 to i64 %v11 = zext i32 %v10 to i64
Show All 11 Linesb2: ; preds = %b1
%v23 = zext i32 %v22 to i64 %v23 = zext i32 %v22 to i64
%v24 = shl nuw i64 %v23, 32 %v24 = shl nuw i64 %v23, 32
%v25 = or i64 %v24, zext (i32 ptrtoint (ptr @f4 to i32) to i64) %v25 = or i64 %v24, zext (i32 ptrtoint (ptr @f4 to i32) to i64)
%v26 = ptrtoint ptr %v3 to i32 %v26 = ptrtoint ptr %v3 to i32
%v27 = zext i32 %v26 to i64 %v27 = zext i32 %v26 to i64
%v28 = shl nuw i64 %v27, 32 %v28 = shl nuw i64 %v27, 32
%v29 = or i64 %v28, zext (i32 ptrtoint (ptr @f7 to i32) to i64) %v29 = or i64 %v28, zext (i32 ptrtoint (ptr @f7 to i32) to i64)
%v30 = call ptr @f9(ptr nonnull null) #1 %v30 = call ptr @f9(ptr nonnull null) #1
br i1 undef, label %b5, label %b4 br i1 %c2, label %b5, label %b4
b3: ; preds = %b1 b3: ; preds = %b1
unreachable unreachable
b4: ; preds = %b2 b4: ; preds = %b2
store ptr null, ptr null, align 4 store ptr null, ptr null, align 4
%v31 = call zeroext i1 @f0(ptr null) #0 %v31 = call zeroext i1 @f0(ptr null) #0
br i1 %v31, label %b6, label %b32 br i1 %v31, label %b6, label %b32
b5: ; preds = %b2 b5: ; preds = %b2
unreachable unreachable
b6: ; preds = %b4 b6: ; preds = %b4
br i1 undef, label %b7, label %b32 br i1 %c3, label %b7, label %b32
b7: ; preds = %b6 b7: ; preds = %b6
br i1 undef, label %b8, label %b32 br i1 %c4, label %b8, label %b32
b8: ; preds = %b7 b8: ; preds = %b7
br i1 undef, label %b9, label %b32 br i1 %c5, label %b9, label %b32
b9: ; preds = %b8 b9: ; preds = %b8
br i1 undef, label %b10, label %b32 br i1 %c6, label %b10, label %b32
b10: ; preds = %b9 b10: ; preds = %b9
%v32 = call zeroext i1 @f1(ptr null) #0 %v32 = call zeroext i1 @f1(ptr null) #0
br i1 %v32, label %b11, label %b32 br i1 %v32, label %b11, label %b32
b11: ; preds = %b10 b11: ; preds = %b10
br i1 undef, label %b13, label %b12 br i1 %c7, label %b13, label %b12
b12: ; preds = %b11 b12: ; preds = %b11
unreachable unreachable
b13: ; preds = %b11 b13: ; preds = %b11
%v33 = call zeroext i1 @f0(ptr undef) #0 %v33 = call zeroext i1 @f0(ptr undef) #0
br i1 %v33, label %b14, label %b32 br i1 %v33, label %b14, label %b32
b14: ; preds = %b13 b14: ; preds = %b13
br i1 undef, label %b16, label %b15 br i1 %c8, label %b16, label %b15
b15: ; preds = %b14 b15: ; preds = %b14
unreachable unreachable
b16: ; preds = %b14 b16: ; preds = %b14
%v34 = call zeroext i1 @f1(ptr null) #0 %v34 = call zeroext i1 @f1(ptr null) #0
br i1 %v34, label %b18, label %b17 br i1 %v34, label %b18, label %b17
b17: ; preds = %b16 b17: ; preds = %b16
unreachable unreachable
b18: ; preds = %b16 b18: ; preds = %b16
br i1 undef, label %b19, label %b32 br i1 %c9, label %b19, label %b32
b19: ; preds = %b18 b19: ; preds = %b18
br i1 undef, label %b26, label %b20 br i1 %c10, label %b26, label %b20
b20: ; preds = %b19 b20: ; preds = %b19
br i1 undef, label %b22, label %b21 br i1 %c11, label %b22, label %b21
b21: ; preds = %b20 b21: ; preds = %b20
br i1 undef, label %b23, label %b32 br i1 %c12, label %b23, label %b32
b22: ; preds = %b20 b22: ; preds = %b20
unreachable unreachable
b23: ; preds = %b21 b23: ; preds = %b21
br i1 undef, label %b24, label %b32 br i1 %c13, label %b24, label %b32
b24: ; preds = %b23 b24: ; preds = %b23
%v35 = call zeroext i1 @f8(ptr nonnull %a1, ptr undef, i64 undef) #1 %v35 = call zeroext i1 @f8(ptr nonnull %a1, ptr undef, i64 undef) #1
br i1 %v35, label %b25, label %b32 br i1 %v35, label %b25, label %b32
b25: ; preds = %b24 b25: ; preds = %b24
%v36 = call zeroext i1 @f8(ptr nonnull %a1, ptr undef, i64 %v9) #1 %v36 = call zeroext i1 @f8(ptr nonnull %a1, ptr undef, i64 %v9) #1
unreachable unreachable
b26: ; preds = %b19 b26: ; preds = %b19
br i1 undef, label %b27, label %b32 br i1 %c14, label %b27, label %b32
b27: ; preds = %b26 b27: ; preds = %b26
br i1 undef, label %b28, label %b32 br i1 %c15, label %b28, label %b32
b28: ; preds = %b27 b28: ; preds = %b27
br i1 undef, label %b31, label %b29 br i1 %c16, label %b31, label %b29
b29: ; preds = %b28 b29: ; preds = %b28
%v37 = call zeroext i1 @f8(ptr nonnull %a1, ptr null, i64 %v21) #1 %v37 = call zeroext i1 @f8(ptr nonnull %a1, ptr null, i64 %v21) #1
%v38 = call zeroext i1 @f8(ptr nonnull %a1, ptr undef, i64 %v25) #1 %v38 = call zeroext i1 @f8(ptr nonnull %a1, ptr undef, i64 %v25) #1
br i1 %v38, label %b30, label %b32 br i1 %v38, label %b30, label %b32
b30: ; preds = %b29 b30: ; preds = %b29
%v39 = call zeroext i1 @f8(ptr nonnull %a1, ptr undef, i64 %v29) #1 %v39 = call zeroext i1 @f8(ptr nonnull %a1, ptr undef, i64 %v29) #1
Show All 20 Lines

llvm/test/CodeGen/Hexagon/packetize-impdef-1.ll

; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 -hexagon-instsimplify=0 < %s | FileCheck %s ; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 -hexagon-instsimplify=0 < %s | FileCheck %s
; REQUIRES: asserts ; REQUIRES: asserts
; Test that the compiler doesn't assert because IMPLICIT_DEF instructions are ; Test that the compiler doesn't assert because IMPLICIT_DEF instructions are
; are added to the same packet as a use. This test case asserts if the ; are added to the same packet as a use. This test case asserts if the
; IMPLICIT_DEFs are not handled properly. ; IMPLICIT_DEFs are not handled properly.
; ;
; r0 = IMPLICIT_DEF ; r0 = IMPLICIT_DEF
; r1 = IMPLICIT_DEF ; r1 = IMPLICIT_DEF
; S2_storerd_io r29, 0, d0 ; S2_storerd_io r29, 0, d0
; CHECK: memd(r29+#0) = r{{[0-9]+}}:{{[0-9]+}} ; CHECK: memd(r29+#0) = r{{[0-9]+}}:{{[0-9]+}}
; CHECK: memd(r29+#0) = r{{[0-9]+}}:{{[0-9]+}} ; CHECK: memd(r29+#0) = r{{[0-9]+}}:{{[0-9]+}}
define ptr @f0(ptr %a0) local_unnamed_addr { define ptr @f0(ptr %a0, i1 %c0, i1 %c1, i1 %c2, i1 %c3) local_unnamed_addr {
b0: b0:
%v0 = tail call ptr @f1(i32 0) %v0 = tail call ptr @f1(i32 0)
%v1 = tail call ptr @f1(i32 8) %v1 = tail call ptr @f1(i32 8)
%v3 = load i32, ptr undef, align 4 %v3 = load i32, ptr undef, align 4
%v4 = tail call ptr @f4(ptr %a0, i32 0, i32 %v3) %v4 = tail call ptr @f4(ptr %a0, i32 0, i32 %v3)
%v5 = sub nsw i32 %v3, 0 %v5 = sub nsw i32 %v3, 0
br label %b1 br label %b1
Show All 9 Lines
b3: ; preds = %b1 b3: ; preds = %b1
unreachable unreachable
b4: ; preds = %b1, %b1 b4: ; preds = %b1, %b1
br label %b5 br label %b5
b5: ; preds = %b4 b5: ; preds = %b4
br i1 undef, label %b27, label %b6 br i1 %c0, label %b27, label %b6
b6: ; preds = %b5 b6: ; preds = %b5
%v6 = ptrtoint ptr %v4 to i32 %v6 = ptrtoint ptr %v4 to i32
%v7 = sub i32 0, %v6 %v7 = sub i32 0, %v6
%v8 = call ptr @f4(ptr nonnull %v4, i32 0, i32 %v7) %v8 = call ptr @f4(ptr nonnull %v4, i32 0, i32 %v7)
%v9 = call ptr @f4(ptr nonnull %v4, i32 undef, i32 %v5) %v9 = call ptr @f4(ptr nonnull %v4, i32 undef, i32 %v5)
br label %b7 br label %b7
b7: ; preds = %b6 b7: ; preds = %b6
br i1 undef, label %b8, label %b9 br i1 %c1, label %b8, label %b9
b8: ; preds = %b7 b8: ; preds = %b7
br label %b9 br label %b9
b9: ; preds = %b8, %b7 b9: ; preds = %b8, %b7
%v10 = phi i32 [ 2, %b8 ], [ 0, %b7 ] %v10 = phi i32 [ 2, %b8 ], [ 0, %b7 ]
%v11 = load i8, ptr %v9, align 1 %v11 = load i8, ptr %v9, align 1
switch i8 %v11, label %b12 [ switch i8 %v11, label %b12 [
i8 43, label %b10 i8 43, label %b10
i8 45, label %b10 i8 45, label %b10
] ]
b10: ; preds = %b9, %b9 b10: ; preds = %b9, %b9
br i1 undef, label %b11, label %b12 br i1 %c2, label %b11, label %b12
b11: ; preds = %b10 b11: ; preds = %b10
%v12 = call i64 @f6(ptr nonnull %v9, ptr nonnull undef, i32 10) %v12 = call i64 @f6(ptr nonnull %v9, ptr nonnull undef, i32 10)
%v13 = load ptr, ptr undef, align 4 %v13 = load ptr, ptr undef, align 4
%v14 = ptrtoint ptr %v13 to i32 %v14 = ptrtoint ptr %v13 to i32
br label %b15 br label %b15
b12: ; preds = %b10, %b9 b12: ; preds = %b10, %b9
Show All 20 Linesb16: ; preds = %b15
%v20 = or i1 undef, %v19 %v20 = or i1 undef, %v19
br i1 %v20, label %b17, label %b18 br i1 %v20, label %b17, label %b18
b17: ; preds = %b16 b17: ; preds = %b16
call void @f2(ptr %v8) call void @f2(ptr %v8)
br label %b27 br label %b27
b18: ; preds = %b16 b18: ; preds = %b16
br i1 undef, label %b19, label %b20 br i1 %c3, label %b19, label %b20
b19: ; preds = %b18 b19: ; preds = %b18
br label %b24 br label %b24
b20: ; preds = %b18 b20: ; preds = %b18
%v21 = add i32 %v5, -2 %v21 = add i32 %v5, -2
%v22 = sub i32 %v21, %v7 %v22 = sub i32 %v21, %v7
%v23 = add i32 %v22, %v15 %v23 = add i32 %v22, %v15
▲ Show 20 Lines • Show All 47 Lines • Show Last 20 Lines

llvm/test/CodeGen/Hexagon/packetize-impdef.ll

Show All 17 Lines
@g0 = external hidden unnamed_addr constant [7 x %0], align 8 @g0 = external hidden unnamed_addr constant [7 x %0], align 8
@g1 = external hidden global %1, align 4 @g1 = external hidden global %1, align 4
@g2 = external hidden constant %3, align 4 @g2 = external hidden constant %3, align 4
@g3 = external hidden constant %3, align 4 @g3 = external hidden constant %3, align 4
declare void @f0(ptr, i32, i32) declare void @f0(ptr, i32, i32)
define hidden fastcc i32 @f1(ptr %a0, ptr %a1, ptr %a2) { define hidden fastcc i32 @f1(ptr %a0, ptr %a1, ptr %a2, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, i1 %c10, i1 %c11, i1 %c12, i1 %c13, i1 %c14) {
b0: b0:
br i1 undef, label %b1, label %b2 br i1 %c0, label %b1, label %b2
b1: ; preds = %b0 b1: ; preds = %b0
unreachable unreachable
b2: ; preds = %b0 b2: ; preds = %b0
br i1 undef, label %b3, label %b4 br i1 %c1, label %b3, label %b4
b3: ; preds = %b2 b3: ; preds = %b2
br label %b55 br label %b55
b4: ; preds = %b2 b4: ; preds = %b2
br i1 undef, label %b6, label %b5 br i1 %c2, label %b6, label %b5
b5: ; preds = %b4 b5: ; preds = %b4
%v0 = getelementptr inbounds %5, ptr %a0, i32 0, i32 1 %v0 = getelementptr inbounds %5, ptr %a0, i32 0, i32 1
br label %b7 br label %b7
b6: ; preds = %b4 b6: ; preds = %b4
br label %b55 br label %b55
Show All 10 Lines
b8: ; preds = %b7 b8: ; preds = %b7
call void @f0(ptr @g2, i32 %v3, i32 %v4) call void @f0(ptr @g2, i32 %v3, i32 %v4)
br label %b54 br label %b54
b9: ; preds = %b7 b9: ; preds = %b7
%v9 = load i8, ptr undef, align 1 %v9 = load i8, ptr undef, align 1
%v10 = zext i8 %v9 to i32 %v10 = zext i8 %v9 to i32
br i1 undef, label %b10, label %b11 br i1 %c3, label %b10, label %b11
b10: ; preds = %b9 b10: ; preds = %b9
br label %b47 br label %b47
b11: ; preds = %b9 b11: ; preds = %b9
br i1 undef, label %b12, label %b47 br i1 %c4, label %b12, label %b47
b12: ; preds = %b11 b12: ; preds = %b11
br i1 undef, label %b13, label %b47 br i1 %c5, label %b13, label %b47
b13: ; preds = %b12 b13: ; preds = %b12
%v11 = getelementptr inbounds [7 x %0], ptr @g0, i32 0, i32 %v10, i32 2 %v11 = getelementptr inbounds [7 x %0], ptr @g0, i32 0, i32 %v10, i32 2
%v12 = load ptr, ptr %v11, align 4 %v12 = load ptr, ptr %v11, align 4
%v13 = call zeroext i8 %v12(i8 zeroext %v9) %v13 = call zeroext i8 %v12(i8 zeroext %v9)
br i1 undef, label %b14, label %b47 br i1 %c6, label %b14, label %b47
b14: ; preds = %b13 b14: ; preds = %b13
br i1 undef, label %b15, label %b16 br i1 %c7, label %b15, label %b16
b15: ; preds = %b14 b15: ; preds = %b14
br label %b46 br label %b46
b16: ; preds = %b14 b16: ; preds = %b14
br i1 false, label %b17, label %b22 br i1 false, label %b17, label %b22
b17: ; preds = %b16 b17: ; preds = %b16
br i1 undef, label %b18, label %b19 br i1 %c8, label %b18, label %b19
b18: ; preds = %b17 b18: ; preds = %b17
unreachable unreachable
b19: ; preds = %b17 b19: ; preds = %b17
br label %b20 br label %b20
b20: ; preds = %b20, %b19 b20: ; preds = %b20, %b19
br i1 undef, label %b20, label %b21 br i1 %c9, label %b20, label %b21
b21: ; preds = %b20 b21: ; preds = %b20
unreachable unreachable
b22: ; preds = %b16 b22: ; preds = %b16
br i1 false, label %b23, label %b24 br i1 false, label %b23, label %b24
b23: ; preds = %b22 b23: ; preds = %b22
Show All 38 Linesb31: ; preds = %b29
%v28 = and i1 undef, %v27 %v28 = and i1 undef, %v27
br i1 %v28, label %b32, label %b33 br i1 %v28, label %b32, label %b33
b32: ; preds = %b31 b32: ; preds = %b31
store i32 %v26, ptr undef, align 4 store i32 %v26, ptr undef, align 4
br label %b36 br label %b36
b33: ; preds = %b31 b33: ; preds = %b31
br i1 undef, label %b34, label %b35 br i1 %c10, label %b34, label %b35
b34: ; preds = %b33 b34: ; preds = %b33
%v29 = getelementptr inbounds %1, ptr @g1, i32 0, i32 3, i32 %v14 %v29 = getelementptr inbounds %1, ptr @g1, i32 0, i32 3, i32 %v14
store i32 undef, ptr %v29, align 4 store i32 undef, ptr %v29, align 4
br label %b36 br label %b36
b35: ; preds = %b33 b35: ; preds = %b33
br label %b36 br label %b36
b36: ; preds = %b35, %b34, %b32 b36: ; preds = %b35, %b34, %b32
%v30 = add nuw nsw i32 %v14, 1 %v30 = add nuw nsw i32 %v14, 1
%v31 = icmp ult i32 %v30, 8192 %v31 = icmp ult i32 %v30, 8192
br i1 %v31, label %b27, label %b37 br i1 %v31, label %b27, label %b37
b37: ; preds = %b36 b37: ; preds = %b36
br label %b38 br label %b38
b38: ; preds = %b38, %b37 b38: ; preds = %b38, %b37
br i1 undef, label %b38, label %b39 br i1 %c11, label %b38, label %b39
b39: ; preds = %b38 b39: ; preds = %b38
br i1 false, label %b40, label %b41 br i1 false, label %b40, label %b41
b40: ; preds = %b39 b40: ; preds = %b39
unreachable unreachable
b41: ; preds = %b39 b41: ; preds = %b39
%v32 = icmp ult i8 %v9, 6 %v32 = icmp ult i8 %v9, 6
br i1 %v32, label %b43, label %b42 br i1 %v32, label %b43, label %b42
b42: ; preds = %b41 b42: ; preds = %b41
br label %b47 br label %b47
b43: ; preds = %b41 b43: ; preds = %b41
%v33 = load i64, ptr undef, align 8 %v33 = load i64, ptr undef, align 8
br label %b44 br label %b44
b44: ; preds = %b44, %b43 b44: ; preds = %b44, %b43
br i1 undef, label %b45, label %b44 br i1 %c12, label %b45, label %b44
b45: ; preds = %b44 b45: ; preds = %b44
%v34 = sdiv i64 undef, %v33 %v34 = sdiv i64 undef, %v33
%v35 = trunc i64 %v34 to i32 %v35 = trunc i64 %v34 to i32
%v36 = add nsw i32 0, %v3 %v36 = add nsw i32 0, %v3
%v37 = sext i32 %v36 to i64 %v37 = sext i32 %v36 to i64
%v38 = mul nsw i64 %v37, 4096000 %v38 = mul nsw i64 %v37, 4096000
%v39 = sdiv i64 %v38, 0 %v39 = sdiv i64 %v38, 0
Show All 9 Linesb47: ; preds = %b46, %b42, %b23, %b13, %b12, %b11, %b10
%v43 = phi i32 [ %v1, %b10 ], [ %v41, %b46 ], [ %v1, %b23 ], [ %v1, %b42 ], [ %v1, %b13 ], [ %v1, %b12 ], [ %v1, %b11 ] %v43 = phi i32 [ %v1, %b10 ], [ %v41, %b46 ], [ %v1, %b23 ], [ %v1, %b42 ], [ %v1, %b13 ], [ %v1, %b12 ], [ %v1, %b11 ]
%v44 = icmp eq i8 %v42, 1 %v44 = icmp eq i8 %v42, 1
br i1 %v44, label %b48, label %b49 br i1 %v44, label %b48, label %b49
b48: ; preds = %b47 b48: ; preds = %b47
br label %b54 br label %b54
b49: ; preds = %b47 b49: ; preds = %b47
br i1 undef, label %b50, label %b52 br i1 %c13, label %b50, label %b52
b50: ; preds = %b49 b50: ; preds = %b49
br i1 undef, label %b51, label %b53 br i1 %c14, label %b51, label %b53
b51: ; preds = %b50 b51: ; preds = %b50
br label %b52 br label %b52
b52: ; preds = %b51, %b49 b52: ; preds = %b51, %b49
%v45 = add nsw i32 %v2, -1 %v45 = add nsw i32 %v2, -1
%v46 = icmp eq i32 %v45, 0 %v46 = icmp eq i32 %v45, 0
br i1 %v46, label %b54, label %b7 br i1 %v46, label %b54, label %b7
Show All 11 Lines

llvm/test/CodeGen/Hexagon/peephole-op-swap.ll

; RUN: llc -march=hexagon < %s ; RUN: llc -march=hexagon < %s
; REQUIRES: asserts ; REQUIRES: asserts
; The operand-swapping code in HexagonPeephole was not handling subregisters ; The operand-swapping code in HexagonPeephole was not handling subregisters
; correctly, resulting in a crash on this code. ; correctly, resulting in a crash on this code.
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon" target triple = "hexagon"
@float_rounding_mode = external global i8, align 1 @float_rounding_mode = external global i8, align 1
@float_exception_flags = external global i8, align 1 @float_exception_flags = external global i8, align 1
; Function Attrs: nounwind ; Function Attrs: nounwind
define i64 @fred(i32 %a) #0 { define i64 @fred(i32 %a, i1 %c0) #0 {
entry: entry:
br i1 undef, label %cleanup, label %lor.lhs.false br i1 %c0, label %cleanup, label %lor.lhs.false
lor.lhs.false: ; preds = %entry lor.lhs.false: ; preds = %entry
%cmp3 = icmp eq i32 undef, 255 %cmp3 = icmp eq i32 undef, 255
%tobool4 = icmp ne i32 undef, 0 %tobool4 = icmp ne i32 undef, 0
%or.cond = and i1 %tobool4, %cmp3 %or.cond = and i1 %tobool4, %cmp3
%. = select i1 %or.cond, i64 9223372036854775807, i64 -9223372036854775808 %. = select i1 %or.cond, i64 9223372036854775807, i64 -9223372036854775808
br label %cleanup br label %cleanup
cleanup: ; preds = %lor.lhs.false, %entry cleanup: ; preds = %lor.lhs.false, %entry
%retval.0 = phi i64 [ 9223372036854775807, %entry ], [ %., %lor.lhs.false ] %retval.0 = phi i64 [ 9223372036854775807, %entry ], [ %., %lor.lhs.false ]
ret i64 %retval.0 ret i64 %retval.0
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

llvm/test/CodeGen/Hexagon/postinc-offset.ll

; RUN: llc -enable-aa-sched-mi -march=hexagon -mcpu=hexagonv5 -rdf-opt=0 \ ; RUN: llc -enable-aa-sched-mi -march=hexagon -mcpu=hexagonv5 -rdf-opt=0 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; CHECK: { ; CHECK: {
; CHECK: = memd([[REG0:(r[0-9]+)]]++#8) ; CHECK: = memd([[REG0:(r[0-9]+)]]++#8)
; CHECK-NOT: memw([[REG0]]+#0) = ; CHECK-NOT: memw([[REG0]]+#0) =
; CHECK: } ; CHECK: }
define void @f0(ptr %a0) #0 { define void @f0(ptr %a0, i1 %c0) #0 {
b0: b0:
store i32 -1, ptr %a0, align 8, !tbaa !0 store i32 -1, ptr %a0, align 8, !tbaa !0
br label %b4 br label %b4
b1: ; preds = %b3 b1: ; preds = %b3
unreachable unreachable
b2: ; preds = %b3 b2: ; preds = %b3
ret void ret void
b3: ; preds = %b4 b3: ; preds = %b4
%v0 = extractelement <2 x i32> %v6, i32 1 %v0 = extractelement <2 x i32> %v6, i32 1
br i1 undef, label %b2, label %b1 br i1 %c0, label %b2, label %b1
b4: ; preds = %b4, %b0 b4: ; preds = %b4, %b0
%v1 = phi <2 x i32> [ %v6, %b4 ], [ zeroinitializer, %b0 ] %v1 = phi <2 x i32> [ %v6, %b4 ], [ zeroinitializer, %b0 ]
%v2 = phi ptr [ %v9, %b4 ], [ %a0, %b0 ] %v2 = phi ptr [ %v9, %b4 ], [ %a0, %b0 ]
%v3 = phi i32 [ %v7, %b4 ], [ 0, %b0 ] %v3 = phi i32 [ %v7, %b4 ], [ 0, %b0 ]
%v5 = load <2 x i32>, ptr %v2, align 8 %v5 = load <2 x i32>, ptr %v2, align 8
%v6 = add <2 x i32> %v5, %v1 %v6 = add <2 x i32> %v5, %v1
%v7 = add nsw i32 %v3, 2 %v7 = add nsw i32 %v3, 2
Show All 11 Lines

llvm/test/CodeGen/Hexagon/pred-taken-jump.ll

; RUN: llc -march=hexagon < %s | FileCheck %s ; RUN: llc -march=hexagon < %s | FileCheck %s
; Predicated (old) taken jumps weren't supported prior to V60. The purpose ; Predicated (old) taken jumps weren't supported prior to V60. The purpose
; of this test is to make sure that these instructions are not ; of this test is to make sure that these instructions are not
; generated for V55. ; generated for V55.
; CHECK-NOT: if ({{!?}}p{{[0-3]}}) jump:t ; CHECK-NOT: if ({{!?}}p{{[0-3]}}) jump:t
%s.0 = type { ptr, i8 } %s.0 = type { ptr, i8 }
define i32 @f0(ptr nocapture %a0, i32 %a1) #0 { define i32 @f0(ptr nocapture %a0, i32 %a1, i1 %c0) #0 {
b0: b0:
%v0 = and i32 %a1, 63 %v0 = and i32 %a1, 63
%v1 = icmp eq i32 %v0, %a1 %v1 = icmp eq i32 %v0, %a1
br i1 %v1, label %b1, label %b7 br i1 %v1, label %b1, label %b7
b1: ; preds = %b0 b1: ; preds = %b0
%v2 = tail call ptr @f1() %v2 = tail call ptr @f1()
br label %b2 br label %b2
Show All 10 Linesb3: ; preds = %b2
%v8 = icmp eq ptr %v7, null %v8 = icmp eq ptr %v7, null
br i1 %v8, label %b7, label %b4 br i1 %v8, label %b7, label %b4
b4: ; preds = %b3 b4: ; preds = %b3
%v9 = select i1 undef, i32 1, i32 %v3 %v9 = select i1 undef, i32 1, i32 %v3
br label %b2 br label %b2
b5: ; preds = %b2 b5: ; preds = %b2
br i1 undef, label %b7, label %b6 br i1 %c0, label %b7, label %b6
b6: ; preds = %b5 b6: ; preds = %b5
br label %b7 br label %b7
b7: ; preds = %b6, %b5, %b3, %b0 b7: ; preds = %b6, %b5, %b3, %b0
%v10 = phi i32 [ -1, %b0 ], [ 1, %b6 ], [ %v3, %b5 ], [ -1, %b3 ] %v10 = phi i32 [ -1, %b0 ], [ 1, %b6 ], [ %v3, %b5 ], [ -1, %b3 ]
ret i32 %v10 ret i32 %v10
} }
declare ptr @f1() declare ptr @f1()
declare ptr @f2(ptr, ptr) declare ptr @f2(ptr, ptr)
attributes #0 = { nounwind "target-cpu"="hexagonv55" } attributes #0 = { nounwind "target-cpu"="hexagonv55" }

llvm/test/CodeGen/Hexagon/rdf-copy-undef.ll

Show All 17 Lines
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
declare fastcc void @f0(i16 signext, i16 signext, i16 signext, ptr nocapture readonly, i16 signext, ptr nocapture) unnamed_addr #1 declare fastcc void @f0(i16 signext, i16 signext, i16 signext, ptr nocapture readonly, i16 signext, ptr nocapture) unnamed_addr #1
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
declare fastcc signext i16 @f1(i16 signext, i16 signext) unnamed_addr #1 declare fastcc signext i16 @f1(i16 signext, i16 signext) unnamed_addr #1
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define fastcc i32 @f2(ptr nocapture readonly %a0, i16 signext %a1, i16 signext %a2, ptr nocapture readonly %a3, i16 signext %a4, ptr nocapture readonly %a51, ptr nocapture %a6) unnamed_addr #1 { define fastcc i32 @f2(ptr nocapture readonly %a0, i16 signext %a1, i16 signext %a2, ptr nocapture readonly %a3, i16 signext %a4, ptr nocapture readonly %a51, ptr nocapture %a6, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9) unnamed_addr #1 {
b0: b0:
%v0 = tail call ptr @llvm.stacksave() %v0 = tail call ptr @llvm.stacksave()
%v1 = tail call fastcc signext i16 @f1(i16 signext %a2, i16 signext %a1) %v1 = tail call fastcc signext i16 @f1(i16 signext %a2, i16 signext %a1)
br i1 undef, label %b7, label %b1 br i1 %c0, label %b7, label %b1
b1: ; preds = %b0 b1: ; preds = %b0
br i1 undef, label %b3, label %b2 br i1 %c1, label %b3, label %b2
b2: ; preds = %b1 b2: ; preds = %b1
br i1 undef, label %b4, label %b8 br i1 %c2, label %b4, label %b8
b3: ; preds = %b1 b3: ; preds = %b1
br i1 undef, label %b5, label %b8 br i1 %c3, label %b5, label %b8
b4: ; preds = %b4, %b2 b4: ; preds = %b4, %b2
br i1 undef, label %b4, label %b6, !llvm.loop !2 br i1 %c4, label %b4, label %b6, !llvm.loop !2
b5: ; preds = %b5, %b3 b5: ; preds = %b5, %b3
%v2 = phi i16 [ %v3, %b5 ], [ 0, %b3 ] %v2 = phi i16 [ %v3, %b5 ], [ 0, %b3 ]
%v3 = add i16 %v2, 1 %v3 = add i16 %v2, 1
%v4 = icmp sgt i32 0, -1073741825 %v4 = icmp sgt i32 0, -1073741825
br i1 %v4, label %b5, label %b6 br i1 %v4, label %b5, label %b6
b6: ; preds = %b5, %b4 b6: ; preds = %b5, %b4
%v5 = phi i16 [ %v3, %b5 ], [ undef, %b4 ] %v5 = phi i16 [ %v3, %b5 ], [ undef, %b4 ]
br label %b7 br label %b7
b7: ; preds = %b6, %b0 b7: ; preds = %b6, %b0
%v6 = phi i16 [ %v5, %b6 ], [ 0, %b0 ] %v6 = phi i16 [ %v5, %b6 ], [ 0, %b0 ]
br i1 undef, label %b9, label %b8 br i1 %c5, label %b9, label %b8
b8: ; preds = %b7, %b3, %b2 b8: ; preds = %b7, %b3, %b2
%v7 = or i32 0, undef %v7 = or i32 0, undef
br label %b9 br label %b9
b9: ; preds = %b8, %b7 b9: ; preds = %b8, %b7
%v8 = phi i16 [ 0, %b8 ], [ %v6, %b7 ] %v8 = phi i16 [ 0, %b8 ], [ %v6, %b7 ]
%v9 = phi i32 [ %v7, %b8 ], [ 0, %b7 ] %v9 = phi i32 [ %v7, %b8 ], [ 0, %b7 ]
%v10 = load i16, ptr undef, align 2, !tbaa !4 %v10 = load i16, ptr undef, align 2, !tbaa !4
%v11 = sext i16 %v10 to i32 %v11 = sext i16 %v10 to i32
%v12 = zext i16 %v10 to i32 %v12 = zext i16 %v10 to i32
br i1 undef, label %b10, label %b11 br i1 %c6, label %b10, label %b11
b10: ; preds = %b9 b10: ; preds = %b9
store i1 true, ptr @g0, align 4 store i1 true, ptr @g0, align 4
br label %b11 br label %b11
b11: ; preds = %b10, %b9 b11: ; preds = %b10, %b9
%v13 = load i16, ptr undef, align 2, !tbaa !4 %v13 = load i16, ptr undef, align 2, !tbaa !4
%v14 = sext i16 %v13 to i32 %v14 = sext i16 %v13 to i32
Show All 13 Linesb11: ; preds = %b10, %b9
%v28 = and i1 %v27, undef %v28 = and i1 %v27, undef
br i1 %v28, label %b12, label %b13 br i1 %v28, label %b12, label %b13
b12: ; preds = %b11 b12: ; preds = %b11
store i1 true, ptr @g0, align 4 store i1 true, ptr @g0, align 4
br label %b13 br label %b13
b13: ; preds = %b12, %b11 b13: ; preds = %b12, %b11
br i1 undef, label %b14, label %b24 br i1 %c7, label %b14, label %b24
b14: ; preds = %b13 b14: ; preds = %b13
br label %b15 br label %b15
b15: ; preds = %b23, %b14 b15: ; preds = %b23, %b14
br i1 undef, label %b16, label %b17 br i1 %c8, label %b16, label %b17
b16: ; preds = %b15 b16: ; preds = %b15
br label %b19 br label %b19
b17: ; preds = %b15 b17: ; preds = %b15
%v29 = trunc i32 %v26 to i16 %v29 = trunc i32 %v26 to i16
%v30 = icmp eq i16 %v29, -32768 %v30 = icmp eq i16 %v29, -32768
%v31 = and i1 undef, %v30 %v31 = and i1 undef, %v30
Show All 18 Lines
b22: ; preds = %b20 b22: ; preds = %b20
br label %b23 br label %b23
b23: ; preds = %b22, %b21 b23: ; preds = %b22, %b21
%v34 = add nsw i32 %v32, 32768 %v34 = add nsw i32 %v32, 32768
%v35 = lshr i32 %v34, 16 %v35 = lshr i32 %v34, 16
%v36 = trunc i32 %v35 to i16 %v36 = trunc i32 %v35 to i16
store i16 %v36, ptr undef, align 2, !tbaa !4 store i16 %v36, ptr undef, align 2, !tbaa !4
br i1 undef, label %b24, label %b15 br i1 %c9, label %b24, label %b15
b24: ; preds = %b23, %b13 b24: ; preds = %b23, %b13
call fastcc void @f0(i16 signext undef, i16 signext %a1, i16 signext %a2, ptr %a3, i16 signext %a4, ptr %a6) call fastcc void @f0(i16 signext undef, i16 signext %a1, i16 signext %a2, ptr %a3, i16 signext %a4, ptr %a6)
call void @llvm.stackrestore(ptr %v0) call void @llvm.stackrestore(ptr %v0)
ret i32 undef ret i32 undef
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }
Show All 12 Lines

llvm/test/CodeGen/Hexagon/rdf-copy-undef2.ll

; RUN: llc -march=hexagon < %s ; RUN: llc -march=hexagon < %s
; REQUIRES: asserts ; REQUIRES: asserts
target triple = "hexagon" target triple = "hexagon"
declare void @llvm.lifetime.start.p0(i64, ptr nocapture) #0 declare void @llvm.lifetime.start.p0(i64, ptr nocapture) #0
declare void @llvm.lifetime.end.p0(i64, ptr nocapture) #0 declare void @llvm.lifetime.end.p0(i64, ptr nocapture) #0
declare signext i16 @cat(i16 signext) #1 declare signext i16 @cat(i16 signext) #1
declare void @danny(i16 signext, i16 signext, i16 signext, ptr nocapture readonly, i16 signext, ptr nocapture) #1 declare void @danny(i16 signext, i16 signext, i16 signext, ptr nocapture readonly, i16 signext, ptr nocapture) #1
declare void @sammy(ptr nocapture readonly, ptr nocapture readonly, ptr nocapture readonly, ptr nocapture, ptr nocapture, i16 signext, i16 signext, i16 signext) #1 declare void @sammy(ptr nocapture readonly, ptr nocapture readonly, ptr nocapture readonly, ptr nocapture, ptr nocapture, i16 signext, i16 signext, i16 signext) #1
declare ptr @llvm.stacksave() #2 declare ptr @llvm.stacksave() #2
declare void @llvm.stackrestore(ptr) #2 declare void @llvm.stackrestore(ptr) #2
define i32 @fred(i16 signext %p0, i16 signext %p1, ptr nocapture readonly %p2, i16 signext %p3, ptr nocapture readonly %p4, ptr nocapture %p5) #1 { define i32 @fred(i16 signext %p0, i16 signext %p1, ptr nocapture readonly %p2, i16 signext %p3, ptr nocapture readonly %p4, ptr nocapture %p5, i1 %c0, i1 %c1) #1 {
entry: entry:
%0 = tail call ptr @llvm.stacksave() %0 = tail call ptr @llvm.stacksave()
%vla = alloca i16, i32 undef, align 8 %vla = alloca i16, i32 undef, align 8
%call17 = call signext i16 @cat(i16 signext 1) #1 %call17 = call signext i16 @cat(i16 signext 1) #1
br i1 undef, label %for.cond23.preheader, label %for.end47 br i1 %c0, label %for.cond23.preheader, label %for.end47
for.cond23.preheader: ; preds = %for.end40, %entry for.cond23.preheader: ; preds = %for.end40, %entry
%i.190 = phi i16 [ %inc46, %for.end40 ], [ 0, %entry ] %i.190 = phi i16 [ %inc46, %for.end40 ], [ 0, %entry ]
br i1 undef, label %for.body27, label %for.end40 br i1 %c1, label %for.body27, label %for.end40
for.body27: ; preds = %for.body27, %for.cond23.preheader for.body27: ; preds = %for.body27, %for.cond23.preheader
%indvars.iv = phi i32 [ %indvars.iv.next, %for.body27 ], [ 0, %for.cond23.preheader ] %indvars.iv = phi i32 [ %indvars.iv.next, %for.body27 ], [ 0, %for.cond23.preheader ]
%call30 = call signext i16 @cat(i16 signext 7) #1 %call30 = call signext i16 @cat(i16 signext 7) #1
%arrayidx32 = getelementptr inbounds i16, ptr %vla, i32 %indvars.iv %arrayidx32 = getelementptr inbounds i16, ptr %vla, i32 %indvars.iv
store i16 %call30, ptr %arrayidx32, align 2 store i16 %call30, ptr %arrayidx32, align 2
%arrayidx37 = getelementptr inbounds i16, ptr undef, i32 %indvars.iv %arrayidx37 = getelementptr inbounds i16, ptr undef, i32 %indvars.iv
%indvars.iv.next = add nuw nsw i32 %indvars.iv, 1 %indvars.iv.next = add nuw nsw i32 %indvars.iv, 1
Show All 24 Lines

llvm/test/CodeGen/Hexagon/rdf-cover-use.ll

; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s
; Check for sane output. ; Check for sane output.
; CHECK: vmpyweh ; CHECK: vmpyweh
target triple = "hexagon" target triple = "hexagon"
declare i32 @llvm.hexagon.S2.clb(i32) #0 declare i32 @llvm.hexagon.S2.clb(i32) #0
declare i32 @llvm.hexagon.S2.asl.r.r(i32, i32) #0 declare i32 @llvm.hexagon.S2.asl.r.r(i32, i32) #0
declare i32 @llvm.hexagon.S2.vrndpackwh(i64) #0 declare i32 @llvm.hexagon.S2.vrndpackwh(i64) #0
declare i64 @llvm.hexagon.M2.mmpyl.s1(i64, i64) #0 declare i64 @llvm.hexagon.M2.mmpyl.s1(i64, i64) #0
define i64 @fred(i32 %a0, i32 %a1) local_unnamed_addr #1 { define i64 @fred(i32 %a0, i32 %a1, i1 %c0) local_unnamed_addr #1 {
b2: b2:
br i1 undef, label %b15, label %b3 br i1 %c0, label %b15, label %b3
b3: ; preds = %b2 b3: ; preds = %b2
%v4 = tail call i32 @llvm.hexagon.S2.clb(i32 %a1) #0 %v4 = tail call i32 @llvm.hexagon.S2.clb(i32 %a1) #0
%v5 = add nsw i32 %v4, -32 %v5 = add nsw i32 %v4, -32
%v6 = zext i32 %v5 to i64 %v6 = zext i32 %v5 to i64
%v7 = shl nuw i64 %v6, 32 %v7 = shl nuw i64 %v6, 32
%v8 = or i64 %v7, 0 %v8 = or i64 %v7, 0
%v9 = tail call i32 @llvm.hexagon.S2.asl.r.r(i32 %a0, i32 0) %v9 = tail call i32 @llvm.hexagon.S2.asl.r.r(i32 %a0, i32 0)
Show All 15 Lines

llvm/test/CodeGen/Hexagon/rdf-extra-livein.ll

; RUN: llc -march=hexagon -verify-machineinstrs -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s ; RUN: llc -march=hexagon -verify-machineinstrs -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s
; Verify that the code compiles successfully. ; Verify that the code compiles successfully.
; CHECK: call printf ; CHECK: call printf
target triple = "hexagon" target triple = "hexagon"
%struct.0 = type { i32, i32, i32, i32, i32, i32, i32, i32, i32 } %struct.0 = type { i32, i32, i32, i32, i32, i32, i32, i32, i32 }
@.str.13 = external unnamed_addr constant [60 x i8], align 1 @.str.13 = external unnamed_addr constant [60 x i8], align 1
declare void @printf(ptr nocapture readonly, ...) local_unnamed_addr #0 declare void @printf(ptr nocapture readonly, ...) local_unnamed_addr #0
declare void @danny() local_unnamed_addr #0 declare void @danny() local_unnamed_addr #0
declare zeroext i8 @sammy() local_unnamed_addr #0 declare zeroext i8 @sammy() local_unnamed_addr #0
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @main() local_unnamed_addr #0 { define void @main(i1 %c0, i1 %c1, i1 %c2, i1 %c3) local_unnamed_addr #0 {
entry: entry:
br i1 undef, label %if.then8, label %if.end10 br i1 %c0, label %if.then8, label %if.end10
if.then8: ; preds = %entry if.then8: ; preds = %entry
ret void ret void
if.end10: ; preds = %entry if.end10: ; preds = %entry
br label %do.body br label %do.body
do.body: ; preds = %if.end88.do.body_crit_edge, %if.end10 do.body: ; preds = %if.end88.do.body_crit_edge, %if.end10
%cond = icmp eq i32 undef, 0 %cond = icmp eq i32 undef, 0
br i1 %cond, label %if.end49, label %if.then124 br i1 %cond, label %if.end49, label %if.then124
if.end49: ; preds = %do.body if.end49: ; preds = %do.body
br i1 undef, label %if.end55, label %if.then53 br i1 %c1, label %if.end55, label %if.then53
if.then53: ; preds = %if.end49 if.then53: ; preds = %if.end49
call void @danny() call void @danny()
br label %if.end55 br label %if.end55
if.end55: ; preds = %if.then53, %if.end49 if.end55: ; preds = %if.then53, %if.end49
%call76 = call zeroext i8 @sammy() #0 %call76 = call zeroext i8 @sammy() #0
switch i8 %call76, label %sw.epilog79 [ switch i8 %call76, label %sw.epilog79 [
i8 0, label %sw.bb77 i8 0, label %sw.bb77
i8 3, label %sw.bb77 i8 3, label %sw.bb77
] ]
sw.bb77: ; preds = %if.end55, %if.end55 sw.bb77: ; preds = %if.end55, %if.end55
unreachable unreachable
sw.epilog79: ; preds = %if.end55 sw.epilog79: ; preds = %if.end55
br i1 undef, label %if.end88, label %if.then81 br i1 %c2, label %if.end88, label %if.then81
if.then81: ; preds = %sw.epilog79 if.then81: ; preds = %sw.epilog79
%div87 = fdiv float 0.000000e+00, undef %div87 = fdiv float 0.000000e+00, undef
br label %if.end88 br label %if.end88
if.end88: ; preds = %if.then81, %sw.epilog79 if.end88: ; preds = %if.then81, %sw.epilog79
%t.1 = phi float [ undef, %sw.epilog79 ], [ %div87, %if.then81 ] %t.1 = phi float [ undef, %sw.epilog79 ], [ %div87, %if.then81 ]
%div89 = fdiv float 1.000000e+00, %t.1 %div89 = fdiv float 1.000000e+00, %t.1
%mul92 = fmul float undef, %div89 %mul92 = fmul float undef, %div89
%div93 = fdiv float %mul92, 1.000000e+06 %div93 = fdiv float %mul92, 1.000000e+06
%conv107 = fpext float %div93 to double %conv107 = fpext float %div93 to double
call void (ptr, ...) @printf(ptr @.str.13, double %conv107, double undef, i64 undef, i32 undef) #0 call void (ptr, ...) @printf(ptr @.str.13, double %conv107, double undef, i64 undef, i32 undef) #0
br i1 undef, label %if.end88.do.body_crit_edge, label %if.then124 br i1 %c3, label %if.end88.do.body_crit_edge, label %if.then124
if.end88.do.body_crit_edge: ; preds = %if.end88 if.end88.do.body_crit_edge: ; preds = %if.end88
br label %do.body br label %do.body
if.then124: ; preds = %if.end88, %do.body if.then124: ; preds = %if.end88, %do.body
unreachable unreachable
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

llvm/test/CodeGen/Hexagon/rdf-ignore-undef.ll

; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s
; Check that we don't crash. ; Check that we don't crash.
; CHECK: call foo ; CHECK: call foo
target triple = "hexagon" target triple = "hexagon"
%struct.1 = type { i16, i8, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr } %struct.1 = type { i16, i8, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr }
%struct.0 = type { i32, i32, i32, i32, i32, i32, i32, i32, i32 } %struct.0 = type { i32, i32, i32, i32, i32, i32, i32, i32, i32 }
declare void @foo(ptr, ptr) local_unnamed_addr #0 declare void @foo(ptr, ptr) local_unnamed_addr #0
declare void @bar(ptr, ptr readonly) local_unnamed_addr #0 declare void @bar(ptr, ptr readonly) local_unnamed_addr #0
define i32 @fred(i32 %argc, ptr nocapture readonly %argv) local_unnamed_addr #0 { define i32 @fred(i32 %argc, ptr nocapture readonly %argv, i1 %c0, i1 %c1, i1 %c2) local_unnamed_addr #0 {
entry: entry:
br label %do.body br label %do.body
do.body: ; preds = %if.end88.do.body_crit_edge, %entry do.body: ; preds = %if.end88.do.body_crit_edge, %entry
%cond = icmp eq i32 undef, 0 %cond = icmp eq i32 undef, 0
br i1 %cond, label %if.end49, label %if.then124 br i1 %cond, label %if.end49, label %if.then124
if.end49: ; preds = %do.body if.end49: ; preds = %do.body
call void @foo(ptr nonnull undef, ptr nonnull undef) #0 call void @foo(ptr nonnull undef, ptr nonnull undef) #0
br i1 undef, label %if.end55, label %if.then53 br i1 %c0, label %if.end55, label %if.then53
if.then53: ; preds = %if.end49 if.then53: ; preds = %if.end49
call void @bar(ptr null, ptr nonnull undef) call void @bar(ptr null, ptr nonnull undef)
br label %if.end55 br label %if.end55
if.end55: ; preds = %if.then53, %if.end49 if.end55: ; preds = %if.then53, %if.end49
switch i8 undef, label %sw.epilog79 [ switch i8 undef, label %sw.epilog79 [
i8 0, label %sw.bb77 i8 0, label %sw.bb77
i8 3, label %sw.bb77 i8 3, label %sw.bb77
] ]
sw.bb77: ; preds = %if.end55, %if.end55 sw.bb77: ; preds = %if.end55, %if.end55
br label %sw.epilog79 br label %sw.epilog79
sw.epilog79: ; preds = %sw.bb77, %if.end55 sw.epilog79: ; preds = %sw.bb77, %if.end55
br i1 undef, label %if.end88, label %if.then81 br i1 %c1, label %if.end88, label %if.then81
if.then81: ; preds = %sw.epilog79 if.then81: ; preds = %sw.epilog79
br label %if.end88 br label %if.end88
if.end88: ; preds = %if.then81, %sw.epilog79 if.end88: ; preds = %if.then81, %sw.epilog79
store float 0.000000e+00, ptr undef, align 4 store float 0.000000e+00, ptr undef, align 4
br i1 undef, label %if.end88.do.body_crit_edge, label %if.then124 br i1 %c2, label %if.end88.do.body_crit_edge, label %if.then124
if.end88.do.body_crit_edge: ; preds = %if.end88 if.end88.do.body_crit_edge: ; preds = %if.end88
br label %do.body br label %do.body
if.then124: ; preds = %if.end88, %do.body if.then124: ; preds = %if.end88, %do.body
ret i32 0 ret i32 0
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

llvm/test/CodeGen/Hexagon/rdf-kill-last-op.ll

; RUN: llc -march=hexagon < %s ; RUN: llc -march=hexagon < %s
; REQUIRES: asserts ; REQUIRES: asserts
target triple = "hexagon" target triple = "hexagon"
%s.0 = type { %s.1 } %s.0 = type { %s.1 }
%s.1 = type { i32, ptr } %s.1 = type { i32, ptr }
@g0 = external unnamed_addr constant [6 x [2 x i32]], align 8 @g0 = external unnamed_addr constant [6 x [2 x i32]], align 8
@g1 = external constant %s.0, align 4 @g1 = external constant %s.0, align 4
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0() #0 { define void @f0(i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, i1 %c10, i1 %c11, i1 %c12) #0 {
b0: b0:
br i1 undef, label %b1, label %b2 br i1 %c0, label %b1, label %b2
b1: ; preds = %b0 b1: ; preds = %b0
unreachable unreachable
b2: ; preds = %b0 b2: ; preds = %b0
br i1 undef, label %b3, label %b4 br i1 %c1, label %b3, label %b4
b3: ; preds = %b2 b3: ; preds = %b2
switch i32 undef, label %b4 [ switch i32 undef, label %b4 [
i32 10, label %b5 i32 10, label %b5
] ]
b4: ; preds = %b3, %b2 b4: ; preds = %b3, %b2
unreachable unreachable
b5: ; preds = %b3 b5: ; preds = %b3
br i1 undef, label %b7, label %b6 br i1 %c2, label %b7, label %b6
b6: ; preds = %b5 b6: ; preds = %b5
switch i32 undef, label %b40 [ switch i32 undef, label %b40 [
i32 10, label %b38 i32 10, label %b38
i32 5, label %b8 i32 5, label %b8
] ]
b7: ; preds = %b5 b7: ; preds = %b5
unreachable unreachable
b8: ; preds = %b6 b8: ; preds = %b6
br i1 undef, label %b9, label %b37 br i1 %c3, label %b9, label %b37
b9: ; preds = %b8 b9: ; preds = %b8
br i1 undef, label %b10, label %b37 br i1 %c4, label %b10, label %b37
b10: ; preds = %b9 b10: ; preds = %b9
br i1 undef, label %b12, label %b11 br i1 %c5, label %b12, label %b11
b11: ; preds = %b10 b11: ; preds = %b10
unreachable unreachable
b12: ; preds = %b10 b12: ; preds = %b10
br i1 undef, label %b13, label %b17 br i1 %c6, label %b13, label %b17
b13: ; preds = %b12 b13: ; preds = %b12
br i1 undef, label %b14, label %b15 br i1 %c7, label %b14, label %b15
b14: ; preds = %b13 b14: ; preds = %b13
unreachable unreachable
b15: ; preds = %b13 b15: ; preds = %b13
br i1 undef, label %b16, label %b18 br i1 %c8, label %b16, label %b18
b16: ; preds = %b15 b16: ; preds = %b15
unreachable unreachable
b17: ; preds = %b12 b17: ; preds = %b12
unreachable unreachable
b18: ; preds = %b15 b18: ; preds = %b15
br i1 undef, label %b19, label %b20 br i1 %c9, label %b19, label %b20
b19: ; preds = %b18 b19: ; preds = %b18
br label %b21 br label %b21
b20: ; preds = %b18 b20: ; preds = %b18
unreachable unreachable
b21: ; preds = %b35, %b19 b21: ; preds = %b35, %b19
Show All 34 Lines
b25: ; preds = %b24 b25: ; preds = %b24
%v24 = getelementptr inbounds [6 x [2 x i32]], ptr @g0, i32 0, i32 %v21, i32 0 %v24 = getelementptr inbounds [6 x [2 x i32]], ptr @g0, i32 0, i32 %v21, i32 0
%v25 = load i32, ptr %v24, align 8, !tbaa !0 %v25 = load i32, ptr %v24, align 8, !tbaa !0
%v26 = icmp eq i32 undef, %v25 %v26 = icmp eq i32 undef, %v25
br i1 %v26, label %b26, label %b27 br i1 %v26, label %b26, label %b27
b26: ; preds = %b25 b26: ; preds = %b25
br i1 undef, label %b32, label %b27 br i1 %c10, label %b32, label %b27
b27: ; preds = %b26, %b25 b27: ; preds = %b26, %b25
%v27 = getelementptr inbounds [6 x [2 x i32]], ptr @g0, i32 0, i32 %v23, i32 0 %v27 = getelementptr inbounds [6 x [2 x i32]], ptr @g0, i32 0, i32 %v23, i32 0
%v28 = load i32, ptr %v27, align 8, !tbaa !0 %v28 = load i32, ptr %v27, align 8, !tbaa !0
%v29 = icmp eq i32 undef, %v28 %v29 = icmp eq i32 undef, %v28
br i1 %v29, label %b28, label %b29 br i1 %v29, label %b28, label %b29
b28: ; preds = %b27 b28: ; preds = %b27
br i1 undef, label %b32, label %b29 br i1 %c11, label %b32, label %b29
b29: ; preds = %b28, %b27 b29: ; preds = %b28, %b27
%v30 = load i32, ptr undef, align 4, !tbaa !4 %v30 = load i32, ptr undef, align 4, !tbaa !4
%v31 = load i32, ptr undef, align 4, !tbaa !4 %v31 = load i32, ptr undef, align 4, !tbaa !4
%v32 = icmp ne i32 %v30, 0 %v32 = icmp ne i32 %v30, 0
%v33 = and i1 %v32, undef %v33 = and i1 %v32, undef
%v34 = and i1 undef, %v33 %v34 = and i1 undef, %v33
br i1 %v34, label %b30, label %b31 br i1 %v34, label %b30, label %b31
b30: ; preds = %b29 b30: ; preds = %b29
%v35 = mul nsw i32 %v31, %v31 %v35 = mul nsw i32 %v31, %v31
%v36 = sdiv i32 %v35, 0 %v36 = sdiv i32 %v35, 0
%v37 = trunc i32 %v36 to i16 %v37 = trunc i32 %v36 to i16
br label %b31 br label %b31
b31: ; preds = %b30, %b29 b31: ; preds = %b30, %b29
%v38 = phi i16 [ %v37, %b30 ], [ 0, %b29 ] %v38 = phi i16 [ %v37, %b30 ], [ 0, %b29 ]
br label %b32 br label %b32
b32: ; preds = %b31, %b28, %b26 b32: ; preds = %b31, %b28, %b26
%v39 = phi i16 [ %v38, %b31 ], [ %v2, %b28 ], [ %v2, %b26 ] %v39 = phi i16 [ %v38, %b31 ], [ %v2, %b28 ], [ %v2, %b26 ]
br i1 undef, label %b33, label %b34 br i1 %c12, label %b33, label %b34
b33: ; preds = %b32 b33: ; preds = %b32
call void (ptr, i32, ...) @f1(ptr nonnull @g1, i32 6, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 %v7) #0 call void (ptr, i32, ...) @f1(ptr nonnull @g1, i32 6, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 %v7) #0
br label %b34 br label %b34
b34: ; preds = %b33, %b32 b34: ; preds = %b33, %b32
%v40 = icmp slt i32 %v19, 0 %v40 = icmp slt i32 %v19, 0
%v41 = and i1 %v40, undef %v41 = and i1 %v40, undef
▲ Show 20 Lines • Show All 49 Lines • Show Last 20 Lines

llvm/test/CodeGen/Hexagon/rdf-multiple-phis-up.ll

; RUN: llc -march=hexagon < %s | FileCheck %s ; RUN: llc -march=hexagon < %s | FileCheck %s
; REQUIRES: asserts ; REQUIRES: asserts
; Check that we do not crash. ; Check that we do not crash.
; CHECK: call foo ; CHECK: call foo
target triple = "hexagon" target triple = "hexagon"
%struct.0 = type { ptr, ptr, [2 x ptr], i32, i32, ptr, i32, i32, i32, i32, i32, [2 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %struct.0 = type { ptr, ptr, [2 x ptr], i32, i32, ptr, i32, i32, i32, i32, i32, [2 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
define i32 @fred(ptr %p0) local_unnamed_addr #0 { define i32 @fred(ptr %p0, i1 %c0) local_unnamed_addr #0 {
entry: entry:
br i1 undef, label %if.then21, label %for.body.i br i1 %c0, label %if.then21, label %for.body.i
if.then21: ; preds = %entry if.then21: ; preds = %entry
%.pr = load i32, ptr undef, align 4 %.pr = load i32, ptr undef, align 4
switch i32 %.pr, label %cleanup [ switch i32 %.pr, label %cleanup [
i32 1, label %for.body.i i32 1, label %for.body.i
i32 3, label %if.then60 i32 3, label %if.then60
] ]
Show All 18 Lines

llvm/test/CodeGen/Hexagon/rdf-phi-shadows.ll

; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s
; Check that we don't crash. ; Check that we don't crash.
; CHECK: call printf ; CHECK: call printf
target triple = "hexagon" target triple = "hexagon"
%struct.1 = type { i16, i8, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr } %struct.1 = type { i16, i8, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr }
%struct.0 = type { i32, i32, i32, i32, i32, i32, i32, i32, i32 } %struct.0 = type { i32, i32, i32, i32, i32, i32, i32, i32, i32 }
declare void @foo(ptr, ptr readonly) local_unnamed_addr #0 declare void @foo(ptr, ptr readonly) local_unnamed_addr #0
declare zeroext i8 @bar() local_unnamed_addr #0 declare zeroext i8 @bar() local_unnamed_addr #0
declare i32 @printf(ptr nocapture readonly, ...) local_unnamed_addr #0 declare i32 @printf(ptr nocapture readonly, ...) local_unnamed_addr #0
@.str = private unnamed_addr constant [5 x i8] c"blah\00", align 1 @.str = private unnamed_addr constant [5 x i8] c"blah\00", align 1
define i32 @main(i32 %argc, ptr nocapture readonly %argv) local_unnamed_addr #0 { define i32 @main(i32 %argc, ptr nocapture readonly %argv, i1 %c0, i1 %c1, i1 %c2) local_unnamed_addr #0 {
entry: entry:
%t0 = alloca %struct.0, align 4 %t0 = alloca %struct.0, align 4
br label %do.body br label %do.body
do.body: ; preds = %if.end88.do.body_crit_edge, %entry do.body: ; preds = %if.end88.do.body_crit_edge, %entry
%cond = icmp eq i32 undef, 0 %cond = icmp eq i32 undef, 0
br i1 %cond, label %if.end49, label %if.then124 br i1 %cond, label %if.end49, label %if.then124
if.end49: ; preds = %do.body if.end49: ; preds = %do.body
br i1 undef, label %if.end55, label %if.then53 br i1 %c0, label %if.end55, label %if.then53
if.then53: ; preds = %if.end49 if.then53: ; preds = %if.end49
call void @foo(ptr null, ptr nonnull %t0) call void @foo(ptr null, ptr nonnull %t0)
br label %if.end55 br label %if.end55
if.end55: ; preds = %if.then53, %if.end49 if.end55: ; preds = %if.then53, %if.end49
%call76 = call zeroext i8 @bar() #0 %call76 = call zeroext i8 @bar() #0
switch i8 %call76, label %sw.epilog79 [ switch i8 %call76, label %sw.epilog79 [
i8 0, label %sw.bb77 i8 0, label %sw.bb77
i8 3, label %sw.bb77 i8 3, label %sw.bb77
] ]
sw.bb77: ; preds = %if.end55, %if.end55 sw.bb77: ; preds = %if.end55, %if.end55
unreachable unreachable
sw.epilog79: ; preds = %if.end55 sw.epilog79: ; preds = %if.end55
br i1 undef, label %if.end88, label %if.then81 br i1 %c1, label %if.end88, label %if.then81
if.then81: ; preds = %sw.epilog79 if.then81: ; preds = %sw.epilog79
%div87 = fdiv float 0.000000e+00, undef %div87 = fdiv float 0.000000e+00, undef
br label %if.end88 br label %if.end88
if.end88: ; preds = %if.then81, %sw.epilog79 if.end88: ; preds = %if.then81, %sw.epilog79
%t1 = phi float [ undef, %sw.epilog79 ], [ %div87, %if.then81 ] %t1 = phi float [ undef, %sw.epilog79 ], [ %div87, %if.then81 ]
%div89 = fdiv float 1.000000e+00, %t1 %div89 = fdiv float 1.000000e+00, %t1
%.sroa.speculated = select i1 undef, float 0.000000e+00, float undef %.sroa.speculated = select i1 undef, float 0.000000e+00, float undef
%conv108 = fpext float %.sroa.speculated to double %conv108 = fpext float %.sroa.speculated to double
%call113 = call i32 (ptr, ...) @printf(ptr @.str, double undef, double %conv108, i64 undef, i32 undef) #0 %call113 = call i32 (ptr, ...) @printf(ptr @.str, double undef, double %conv108, i64 undef, i32 undef) #0
br i1 undef, label %if.end88.do.body_crit_edge, label %if.then124 br i1 %c2, label %if.end88.do.body_crit_edge, label %if.then124
if.end88.do.body_crit_edge: ; preds = %if.end88 if.end88.do.body_crit_edge: ; preds = %if.end88
br label %do.body br label %do.body
if.then124: ; preds = %if.end88, %do.body if.then124: ; preds = %if.end88, %do.body
%t2 = phi float [ undef, %do.body ], [ %t1, %if.end88 ] %t2 = phi float [ undef, %do.body ], [ %t1, %if.end88 ]
ret i32 0 ret i32 0
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

llvm/test/CodeGen/Hexagon/rdf-reset-kills.ll

; RUN: llc -march=hexagon < %s ; RUN: llc -march=hexagon < %s
; REQUIRES: asserts ; REQUIRES: asserts
; This test used to crash in register scavenger due to incorrectly set ; This test used to crash in register scavenger due to incorrectly set
; kill flags. ; kill flags.
target triple = "hexagon" target triple = "hexagon"
define void @foo(i64 %a) #0 { define void @foo(i64 %a, i1 %c0) #0 {
entry: entry:
%conv.i = and i64 %a, 9218868437227405312 %conv.i = and i64 %a, 9218868437227405312
%cmp = icmp ne i64 %conv.i, 9218868437227405312 %cmp = icmp ne i64 %conv.i, 9218868437227405312
%and.i37 = and i64 %a, 4503599627370495 %and.i37 = and i64 %a, 4503599627370495
%tobool = icmp eq i64 %and.i37, 0 %tobool = icmp eq i64 %and.i37, 0
%or.cond = or i1 %cmp, %tobool %or.cond = or i1 %cmp, %tobool
br i1 %or.cond, label %lor.lhs.false, label %if.then br i1 %or.cond, label %lor.lhs.false, label %if.then
lor.lhs.false: ; preds = %entry lor.lhs.false: ; preds = %entry
br i1 undef, label %return, label %if.then br i1 %c0, label %return, label %if.then
if.then: ; preds = %lor.lhs.false, %entry if.then: ; preds = %lor.lhs.false, %entry
br label %return br label %return
return: ; preds = %if.then, %lor.lhs.false return: ; preds = %if.then, %lor.lhs.false
ret void ret void
} }
attributes #0 = { norecurse nounwind } attributes #0 = { norecurse nounwind }

llvm/test/CodeGen/Hexagon/redundant-branching2.ll

; RUN: llc -march=hexagon -O2 < %s | FileCheck %s ; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
; This test checks if redundant conditional branches are removed. ; This test checks if redundant conditional branches are removed.
; CHECK: memub ; CHECK: memub
; CHECK: memub ; CHECK: memub
; CHECK: cmp.eq ; CHECK: cmp.eq
; CHECK: memub ; CHECK: memub
; CHECK-NOT: if{{.*}}jump .LBB ; CHECK-NOT: if{{.*}}jump .LBB
target triple = "hexagon-unknown--elf" target triple = "hexagon-unknown--elf"
; Function Attrs: nounwind ; Function Attrs: nounwind
declare void @f0() #0 declare void @f0() #0
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f1(ptr %a0, i32 %a1, ptr %a2, ptr %a3, i32 %a4) #0 { define void @f1(ptr %a0, i32 %a1, ptr %a2, ptr %a3, i32 %a4, i1 %c0) #0 {
b0: b0:
br i1 undef, label %b8, label %b1 br i1 %c0, label %b8, label %b1
b1: ; preds = %b0 b1: ; preds = %b0
tail call void @f0() #0 tail call void @f0() #0
br i1 false, label %b8, label %b2 br i1 false, label %b8, label %b2
b2: ; preds = %b1 b2: ; preds = %b1
%v0 = getelementptr inbounds i8, ptr %a0, i32 undef %v0 = getelementptr inbounds i8, ptr %a0, i32 undef
%v1 = sub i32 0, %a1 %v1 = sub i32 0, %a1
▲ Show 20 Lines • Show All 48 Lines • Show Last 20 Lines

llvm/test/CodeGen/Hexagon/reg-scavengebug-2.ll

; RUN: llc -O3 -march=hexagon < %s | FileCheck %s ; RUN: llc -O3 -march=hexagon < %s | FileCheck %s
; CHECK: v{{[0-9]+}}.cur = vmem(r{{[0-9]+}}+#0) ; CHECK: v{{[0-9]+}}.cur = vmem(r{{[0-9]+}}+#0)
target triple = "hexagon" target triple = "hexagon"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0(ptr nocapture %a0) #0 { define void @f0(ptr nocapture %a0, i1 %c0) #0 {
b0: b0:
br i1 undef, label %b1, label %b5 br i1 %c0, label %b1, label %b5
b1: ; preds = %b0 b1: ; preds = %b0
br label %b2 br label %b2
b2: ; preds = %b4, %b1 b2: ; preds = %b4, %b1
%v1 = phi i32 [ 0, %b1 ], [ %v50, %b4 ] %v1 = phi i32 [ 0, %b1 ], [ %v50, %b4 ]
%v2 = phi ptr [ %a0, %b1 ], [ undef, %b4 ] %v2 = phi ptr [ %a0, %b1 ], [ undef, %b4 ]
br label %b3 br label %b3
▲ Show 20 Lines • Show All 103 Lines • Show Last 20 Lines

llvm/test/CodeGen/Hexagon/reg-scavengebug-4.ll

; RUN: llc -march=hexagon < %s ; RUN: llc -march=hexagon < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Test that the register scavenger does not fail because it can't find ; Test that the register scavenger does not fail because it can't find
; a spill slot. This occurs the offset for a spilled object is too large ; a spill slot. This occurs the offset for a spilled object is too large
; and requires another register to compute the location on the stack. ; and requires another register to compute the location on the stack.
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0(ptr nocapture readonly %a0, i32 %a1, i32 %a2, ptr nocapture readonly %a3, ptr nocapture readonly %a4, ptr nocapture %a5) #0 { define void @f0(ptr nocapture readonly %a0, i32 %a1, i32 %a2, ptr nocapture readonly %a3, ptr nocapture readonly %a4, ptr nocapture %a5, i1 %c0) #0 {
b0: b0:
%v0 = tail call <16 x i32> @llvm.hexagon.V6.vshuffb(<16 x i32> zeroinitializer) %v0 = tail call <16 x i32> @llvm.hexagon.V6.vshuffb(<16 x i32> zeroinitializer)
br i1 undef, label %b1, label %b5 br i1 %c0, label %b1, label %b5
b1: ; preds = %b0 b1: ; preds = %b0
%v1 = getelementptr inbounds i8, ptr %a3, i32 31 %v1 = getelementptr inbounds i8, ptr %a3, i32 31
br label %b2 br label %b2
b2: ; preds = %b4, %b1 b2: ; preds = %b4, %b1
%v2 = phi ptr [ undef, %b1 ], [ %v102, %b4 ] %v2 = phi ptr [ undef, %b1 ], [ %v102, %b4 ]
%v3 = phi i32 [ %a2, %b1 ], [ undef, %b4 ] %v3 = phi i32 [ %a2, %b1 ], [ undef, %b4 ]
▲ Show 20 Lines • Show All 184 Lines • Show Last 20 Lines

llvm/test/CodeGen/Hexagon/reg-scavengebug-5.ll

; RUN: llc -march=hexagon < %s ; RUN: llc -march=hexagon < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Test that the register scavenger does not assert because a spill slot ; Test that the register scavenger does not assert because a spill slot
; was not found. The bug is that the Hexagon spill code was not allocating ; was not found. The bug is that the Hexagon spill code was not allocating
; the spill slot because the function that returns true, which indicates ; the spill slot because the function that returns true, which indicates
; the code changed when a spill is inserted, was not always returning true. ; the code changed when a spill is inserted, was not always returning true.
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0(ptr noalias nocapture readonly %a0, i32 %a1, i32 %a2, i32 %a3, ptr noalias nocapture %a4, i32 %a5) #0 { define void @f0(ptr noalias nocapture readonly %a0, i32 %a1, i32 %a2, i32 %a3, ptr noalias nocapture %a4, i32 %a5, i1 %c0) #0 {
b0: b0:
%v0 = sub i32 0, %a1 %v0 = sub i32 0, %a1
%v1 = getelementptr inbounds i8, ptr %a0, i32 %v0 %v1 = getelementptr inbounds i8, ptr %a0, i32 %v0
%v2 = getelementptr inbounds i8, ptr %a0, i32 %a1 %v2 = getelementptr inbounds i8, ptr %a0, i32 %a1
%v3 = mul nsw i32 %a1, 2 %v3 = mul nsw i32 %a1, 2
%v4 = getelementptr inbounds i8, ptr %a0, i32 %v3 %v4 = getelementptr inbounds i8, ptr %a0, i32 %v3
%v6 = getelementptr inbounds i8, ptr %a4, i32 %a5 %v6 = getelementptr inbounds i8, ptr %a4, i32 %a5
%v8 = tail call <16 x i32> @llvm.hexagon.V6.vd0() %v8 = tail call <16 x i32> @llvm.hexagon.V6.vd0()
Show All 26 Linesb1: ; preds = %b0
%v35 = getelementptr inbounds i8, ptr %v1, i32 64 %v35 = getelementptr inbounds i8, ptr %v1, i32 64
%v37 = add i32 0, 64 %v37 = add i32 0, 64
%v38 = getelementptr i8, ptr %a4, i32 %v37 %v38 = getelementptr i8, ptr %a4, i32 %v37
%v39 = add i32 %a2, -65 %v39 = add i32 %a2, -65
%v40 = lshr i32 %v39, 6 %v40 = lshr i32 %v39, 6
%v41 = add nuw nsw i32 %v40, 1 %v41 = add nuw nsw i32 %v40, 1
%v42 = and i32 %v41, 3 %v42 = and i32 %v41, 3
%v43 = icmp eq i32 %v42, 0 %v43 = icmp eq i32 %v42, 0
br i1 undef, label %b2, label %b4 br i1 %c0, label %b2, label %b4
b2: ; preds = %b2, %b1 b2: ; preds = %b2, %b1
%v44 = phi i32 [ %v144, %b2 ], [ %a2, %b1 ] %v44 = phi i32 [ %v144, %b2 ], [ %a2, %b1 ]
%v45 = phi <16 x i32> [ %v101, %b2 ], [ %v8, %b1 ] %v45 = phi <16 x i32> [ %v101, %b2 ], [ %v8, %b1 ]
%v46 = phi <16 x i32> [ %v113, %b2 ], [ undef, %b1 ] %v46 = phi <16 x i32> [ %v113, %b2 ], [ undef, %b1 ]
%v47 = phi <16 x i32> [ %v102, %b2 ], [ %v8, %b1 ] %v47 = phi <16 x i32> [ %v102, %b2 ], [ %v8, %b1 ]
%v48 = phi <16 x i32> [ %v118, %b2 ], [ undef, %b1 ] %v48 = phi <16 x i32> [ %v118, %b2 ], [ undef, %b1 ]
%v49 = phi ptr [ %v112, %b2 ], [ %v35, %b1 ] %v49 = phi ptr [ %v112, %b2 ], [ %v35, %b1 ]
▲ Show 20 Lines • Show All 195 Lines • Show Last 20 Lines

llvm/test/CodeGen/Hexagon/regalloc-block-overlap.ll

Show All 10 Lines
declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #1 declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #1
declare <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32>, <32 x i32>) #1 declare <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32>, <32 x i32>) #1
declare <32 x i32> @llvm.hexagon.V6.vmpyiewuh.128B(<32 x i32>, <32 x i32>) #1 declare <32 x i32> @llvm.hexagon.V6.vmpyiewuh.128B(<32 x i32>, <32 x i32>) #1
declare <64 x i32> @llvm.hexagon.V6.vaddw.dv.128B(<64 x i32>, <64 x i32>) #1 declare <64 x i32> @llvm.hexagon.V6.vaddw.dv.128B(<64 x i32>, <64 x i32>) #1
declare <32 x i32> @llvm.hexagon.V6.vasrwhsat.128B(<32 x i32>, <32 x i32>, i32) #1 declare <32 x i32> @llvm.hexagon.V6.vasrwhsat.128B(<32 x i32>, <32 x i32>, i32) #1
declare <64 x i32> @llvm.hexagon.V6.vlutvwh.128B(<32 x i32>, <32 x i32>, i32) #1 declare <64 x i32> @llvm.hexagon.V6.vlutvwh.128B(<32 x i32>, <32 x i32>, i32) #1
declare <64 x i32> @llvm.hexagon.V6.vlutvwh.oracc.128B(<64 x i32>, <32 x i32>, <32 x i32>, i32) #1 declare <64 x i32> @llvm.hexagon.V6.vlutvwh.oracc.128B(<64 x i32>, <32 x i32>, <32 x i32>, i32) #1
define hidden void @fred(ptr %a0, i32 %a1, i1 %cond) #0 { define hidden void @fred(ptr %a0, i32 %a1, i1 %cond, i1 %c0) #0 {
b0: b0:
%v1 = ashr i32 %a1, 7 %v1 = ashr i32 %a1, 7
%v2 = shl nsw i32 %v1, 7 %v2 = shl nsw i32 %v1, 7
switch i32 undef, label %b7 [ switch i32 undef, label %b7 [
i32 1, label %b3 i32 1, label %b3
i32 2, label %b5 i32 2, label %b5
i32 3, label %b6 i32 3, label %b6
] ]
Show All 31 Lines
b12: ; preds = %b11, %b10, %b9, %b8 b12: ; preds = %b11, %b10, %b9, %b8
br label %b13 br label %b13
b13: ; preds = %b14, %b12 b13: ; preds = %b14, %b12
br label %b14 br label %b14
b14: ; preds = %b13 b14: ; preds = %b13
br i1 undef, label %b15, label %b13 br i1 %c0, label %b15, label %b13
b15: ; preds = %b14 b15: ; preds = %b14
br label %b16 br label %b16
b16: ; preds = %b15 b16: ; preds = %b15
br i1 %cond, label %b17, label %b18 br i1 %cond, label %b17, label %b18
b17: ; preds = %b16 b17: ; preds = %b16
▲ Show 20 Lines • Show All 69 Lines • Show Last 20 Lines

llvm/test/CodeGen/Hexagon/registerscav-missing-spill-slot.ll

; RUN: llc -march=hexagon -machine-sink-split=0 < %s ; RUN: llc -march=hexagon -machine-sink-split=0 < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Used to fail with: Assertion `ScavengingFrameIndex >= 0 && "Cannot scavenge register without an emergency spill slot!"' failed. ; Used to fail with: Assertion `ScavengingFrameIndex >= 0 && "Cannot scavenge register without an emergency spill slot!"' failed.
target triple = "hexagon-unknown-linux-gnu" target triple = "hexagon-unknown-linux-gnu"
%s.0 = type { double, double, double, double, double, double, i32, double, double, double, double, ptr, i8, [9 x i8], double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, [200 x ptr], [32 x ptr], [32 x i8], i32 } %s.0 = type { double, double, double, double, double, double, i32, double, double, double, double, ptr, i8, [9 x i8], double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, [200 x ptr], [32 x ptr], [32 x i8], i32 }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0() #0 { define void @f0(i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4) #0 {
b0: b0:
%v0 = call ptr @f2() %v0 = call ptr @f2()
br i1 undef, label %b1, label %b2 br i1 %c0, label %b1, label %b2
b1: ; preds = %b0 b1: ; preds = %b0
ret void ret void
b2: ; preds = %b0 b2: ; preds = %b0
br i1 undef, label %b3, label %b4 br i1 %c1, label %b3, label %b4
b3: ; preds = %b2 b3: ; preds = %b2
unreachable unreachable
b4: ; preds = %b2 b4: ; preds = %b2
br i1 undef, label %b5, label %b6 br i1 %c2, label %b5, label %b6
b5: ; preds = %b4 b5: ; preds = %b4
unreachable unreachable
b6: ; preds = %b4 b6: ; preds = %b4
%v1 = call i32 @f1() #0 %v1 = call i32 @f1() #0
br i1 undef, label %b7, label %b20 br i1 %c3, label %b7, label %b20
b7: ; preds = %b6 b7: ; preds = %b6
switch i32 undef, label %b8 [ switch i32 undef, label %b8 [
i32 6, label %b9 i32 6, label %b9
i32 1, label %b14 i32 1, label %b14
i32 2, label %b13 i32 2, label %b13
i32 3, label %b12 i32 3, label %b12
i32 4, label %b11 i32 4, label %b11
Show All 19 Linesb13: ; preds = %b7
unreachable unreachable
b14: ; preds = %b7 b14: ; preds = %b7
%v2 = call ptr @f3(i32 0) #0 %v2 = call ptr @f3(i32 0) #0
br label %b15 br label %b15
b15: ; preds = %b15, %b14 b15: ; preds = %b15, %b14
%v4 = fadd double undef, undef %v4 = fadd double undef, undef
br i1 undef, label %b16, label %b15 br i1 %c4, label %b16, label %b15
b16: ; preds = %b15 b16: ; preds = %b15
switch i32 undef, label %b18 [ switch i32 undef, label %b18 [
i32 0, label %b19 i32 0, label %b19
i32 2, label %b17 i32 2, label %b17
] ]
b17: ; preds = %b16 b17: ; preds = %b16
▲ Show 20 Lines • Show All 100 Lines • Show Last 20 Lines

llvm/test/CodeGen/Hexagon/registerscavenger-fail1.ll

; RUN: llc -march=hexagon -machine-sink-split=0 < %s ; RUN: llc -march=hexagon -machine-sink-split=0 < %s
; REQUIRES: asserts ; REQUIRES: asserts
target triple = "hexagon-unknown-linux-gnu" target triple = "hexagon-unknown-linux-gnu"
%s.0 = type { double, double, double, double, double, double, i32, double, double, double, double, ptr, i8, [9 x i8], double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, [200 x ptr], [32 x ptr], [32 x i8], i32 } %s.0 = type { double, double, double, double, double, double, i32, double, double, double, double, ptr, i8, [9 x i8], double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, [200 x ptr], [32 x ptr], [32 x i8], i32 }
@g0 = external unnamed_addr constant [6 x i8], align 8 @g0 = external unnamed_addr constant [6 x i8], align 8
; Function Attrs: nounwind ; Function Attrs: nounwind
define i32 @f0(double %a0) #0 { define i32 @f0(double %a0, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9) #0 {
b0: b0:
%v0 = call double @f1(ptr @g0) #0 %v0 = call double @f1(ptr @g0) #0
%v1 = call i32 @f2() #0 %v1 = call i32 @f2() #0
%v2 = call ptr @f3(i32 undef) %v2 = call ptr @f3(i32 undef)
br i1 undef, label %b1, label %b2 br i1 %c0, label %b1, label %b2
b1: ; preds = %b0 b1: ; preds = %b0
unreachable unreachable
b2: ; preds = %b0 b2: ; preds = %b0
br i1 undef, label %b3, label %b4 br i1 %c1, label %b3, label %b4
b3: ; preds = %b2 b3: ; preds = %b2
unreachable unreachable
b4: ; preds = %b2 b4: ; preds = %b2
%v3 = mul i32 %v1, 12 %v3 = mul i32 %v1, 12
br i1 undef, label %b5, label %b6 br i1 %c2, label %b5, label %b6
b5: ; preds = %b4 b5: ; preds = %b4
ret i32 0 ret i32 0
b6: ; preds = %b4 b6: ; preds = %b4
%v4 = call i32 @f2() #0 %v4 = call i32 @f2() #0
br i1 undef, label %b7, label %b24 br i1 %c3, label %b7, label %b24
b7: ; preds = %b6 b7: ; preds = %b6
switch i32 undef, label %b8 [ switch i32 undef, label %b8 [
i32 0, label %b15 i32 0, label %b15
i32 1, label %b14 i32 1, label %b14
i32 2, label %b13 i32 2, label %b13
i32 3, label %b12 i32 3, label %b12
i32 4, label %b11 i32 4, label %b11
Show All 24 Linesb14: ; preds = %b7
%v6 = icmp ult i32 %v4, 8 %v6 = icmp ult i32 %v4, 8
br i1 %v6, label %b16, label %b15 br i1 %v6, label %b16, label %b15
b15: ; preds = %b14, %b7 b15: ; preds = %b14, %b7
unreachable unreachable
b16: ; preds = %b14 b16: ; preds = %b14
%v7 = and i32 %v4, 3 %v7 = and i32 %v4, 3
br i1 undef, label %b17, label %b18 br i1 %c4, label %b17, label %b18
b17: ; preds = %b16 b17: ; preds = %b16
br i1 undef, label %b19, label %b18 br i1 %c5, label %b19, label %b18
b18: ; preds = %b18, %b17, %b16 b18: ; preds = %b18, %b17, %b16
%v8 = phi i32 [ %v10, %b18 ], [ 0, %b16 ], [ undef, %b17 ] %v8 = phi i32 [ %v10, %b18 ], [ 0, %b16 ], [ undef, %b17 ]
%v9 = shl i32 %v8, 5 %v9 = shl i32 %v8, 5
%v10 = add nsw i32 %v8, 4 %v10 = add nsw i32 %v8, 4
%v11 = icmp eq i32 %v10, %v4 %v11 = icmp eq i32 %v10, %v4
br i1 %v11, label %b19, label %b18 br i1 %v11, label %b19, label %b18
b19: ; preds = %b18, %b17 b19: ; preds = %b18, %b17
br i1 undef, label %b20, label %b23 br i1 %c6, label %b20, label %b23
b20: ; preds = %b19 b20: ; preds = %b19
%v12 = icmp eq i32 %v7, 2 %v12 = icmp eq i32 %v7, 2
br i1 %v12, label %b21, label %b22 br i1 %v12, label %b21, label %b22
b21: ; preds = %b20 b21: ; preds = %b20
%v15 = or i32 0, 16 %v15 = or i32 0, 16
%v16 = getelementptr i8, ptr %v2, i32 %v15 %v16 = getelementptr i8, ptr %v2, i32 %v15
Show All 37 Linesb22: ; preds = %b21, %b20
%v54 = fcmp olt double %v39, %v53 %v54 = fcmp olt double %v39, %v53
%v55 = select i1 %v54, double %v53, double %v39 %v55 = select i1 %v54, double %v53, double %v39
%v56 = fcmp ogt double %v36, %v48 %v56 = fcmp ogt double %v36, %v48
%v57 = select i1 %v56, double %v48, double %v36 %v57 = select i1 %v56, double %v48, double %v36
%v58 = fcmp ogt double %v38, %v50 %v58 = fcmp ogt double %v38, %v50
%v59 = select i1 %v58, double %v50, double %v38 %v59 = select i1 %v58, double %v50, double %v38
%v60 = select i1 undef, double %v53, double %v40 %v60 = select i1 undef, double %v53, double %v40
%v61 = add i32 %v42, 1 %v61 = add i32 %v42, 1
br i1 undef, label %b24, label %b23 br i1 %c7, label %b24, label %b23
b23: ; preds = %b23, %b22, %b19 b23: ; preds = %b23, %b22, %b19
%v62 = phi double [ %v79, %b23 ], [ 1.000000e+11, %b19 ], [ %v57, %b22 ] %v62 = phi double [ %v79, %b23 ], [ 1.000000e+11, %b19 ], [ %v57, %b22 ]
%v63 = phi double [ %v81, %b23 ], [ 1.000000e+11, %b19 ], [ %v59, %b22 ] %v63 = phi double [ %v81, %b23 ], [ 1.000000e+11, %b19 ], [ %v59, %b22 ]
%v64 = phi i32 [ %v82, %b23 ], [ 0, %b19 ], [ %v61, %b22 ] %v64 = phi i32 [ %v82, %b23 ], [ 0, %b19 ], [ %v61, %b22 ]
%v65 = shl i32 %v64, 5 %v65 = shl i32 %v64, 5
%v66 = load double, ptr undef, align 8, !tbaa !0 %v66 = load double, ptr undef, align 8, !tbaa !0
%v67 = load double, ptr undef, align 8, !tbaa !0 %v67 = load double, ptr undef, align 8, !tbaa !0
Show All 22 Linesb24: ; preds = %b23, %b22, %b6
%v88 = fsub double %v84, undef %v88 = fsub double %v84, undef
%v89 = fsub double %v85, undef %v89 = fsub double %v85, undef
%v90 = fadd double undef, 1.000000e+00 %v90 = fadd double undef, 1.000000e+00
%v91 = fptosi double %v90 to i32 %v91 = fptosi double %v90 to i32
%v92 = fsub double %v86, %v87 %v92 = fsub double %v86, %v87
%v93 = fdiv double %v92, %v0 %v93 = fdiv double %v92, %v0
%v94 = fadd double %v93, 1.000000e+00 %v94 = fadd double %v93, 1.000000e+00
%v95 = fptosi double %v94 to i32 %v95 = fptosi double %v94 to i32
br i1 undef, label %b25, label %b27 br i1 %c8, label %b25, label %b27
b25: ; preds = %b24 b25: ; preds = %b24
%v96 = fdiv double %v88, 0.000000e+00 %v96 = fdiv double %v88, 0.000000e+00
%v97 = fadd double %v96, 1.000000e+00 %v97 = fadd double %v96, 1.000000e+00
%v98 = fptosi double %v97 to i32 %v98 = fptosi double %v97 to i32
%v99 = fdiv double %v89, 0.000000e+00 %v99 = fdiv double %v89, 0.000000e+00
%v100 = fadd double %v99, 1.000000e+00 %v100 = fadd double %v99, 1.000000e+00
%v101 = fptosi double %v100 to i32 %v101 = fptosi double %v100 to i32
Show All 18 Linesb27: ; preds = %b25, %b24
%v114 = fmul double %v109, 5.000000e-01 %v114 = fmul double %v109, 5.000000e-01
%v115 = and i32 %v106, 3 %v115 = and i32 %v106, 3
%v116 = icmp ult i32 %v106, 4 %v116 = icmp ult i32 %v106, 4
br label %b28 br label %b28
b28: ; preds = %b35, %b27 b28: ; preds = %b35, %b27
%v117 = phi i32 [ %v146, %b35 ], [ 0, %b27 ] %v117 = phi i32 [ %v146, %b35 ], [ 0, %b27 ]
%v118 = mul i32 %v117, 232 %v118 = mul i32 %v117, 232
br i1 undef, label %b29, label %b35 br i1 %c9, label %b29, label %b35
b29: ; preds = %b28 b29: ; preds = %b28
%v119 = add i32 %v118, 8 %v119 = add i32 %v118, 8
%v120 = add i32 %v118, 16 %v120 = add i32 %v118, 16
br i1 %v111, label %b30, label %b35 br i1 %v111, label %b30, label %b35
b30: ; preds = %b34, %b29 b30: ; preds = %b34, %b29
%v121 = phi i32 [ %v144, %b34 ], [ 0, %b29 ] %v121 = phi i32 [ %v144, %b34 ], [ 0, %b29 ]
▲ Show 20 Lines • Show All 62 Lines • Show Last 20 Lines

llvm/test/CodeGen/Hexagon/save-kill-csr.ll

Show All 25 Lines
@g13 = external hidden global [4 x %s.0], align 8 @g13 = external hidden global [4 x %s.0], align 8
@g14 = external hidden global [3 x %s.0], align 8 @g14 = external hidden global [3 x %s.0], align 8
@g15 = external hidden global [3 x %s.0], align 8 @g15 = external hidden global [3 x %s.0], align 8
@g16 = external hidden global [3 x %s.0], align 8 @g16 = external hidden global [3 x %s.0], align 8
@g17 = external hidden global [4 x %s.0], align 8 @g17 = external hidden global [4 x %s.0], align 8
@g18 = external hidden global [3 x %s.0], align 8 @g18 = external hidden global [3 x %s.0], align 8
; Function Attrs: norecurse nounwind optsize ssp ; Function Attrs: norecurse nounwind optsize ssp
define hidden zeroext i8 @f0(ptr nocapture readnone %a0, ptr readonly %a1, ptr %a2, i32 %a3) unnamed_addr #0 align 2 { define hidden zeroext i8 @f0(ptr nocapture readnone %a0, ptr readonly %a1, ptr %a2, i32 %a3, i1 %c0, i1 %c1) unnamed_addr #0 align 2 {
b0: b0:
br i1 undef, label %b4, label %b1 br i1 %c0, label %b4, label %b1
b1: ; preds = %b0 b1: ; preds = %b0
%v0 = icmp eq i32 %a3, 1 %v0 = icmp eq i32 %a3, 1
%v1 = select i1 %v0, ptr @g18, ptr @g0 %v1 = select i1 %v0, ptr @g18, ptr @g0
%v2 = icmp eq i32 %a3, 2 %v2 = icmp eq i32 %a3, 2
%v3 = select i1 %v2, ptr @g16, ptr %v1 %v3 = select i1 %v2, ptr @g16, ptr %v1
%v4 = icmp eq i32 %a3, 3 %v4 = icmp eq i32 %a3, 3
%v5 = select i1 %v4, ptr @g15, ptr %v3 %v5 = select i1 %v4, ptr @g15, ptr %v3
Show All 25 Linesb1: ; preds = %b0
%v31 = select i1 %v30, ptr null, ptr %v29 %v31 = select i1 %v30, ptr null, ptr %v29
%v32 = select i1 undef, ptr @g10, ptr %v31 %v32 = select i1 undef, ptr @g10, ptr %v31
%v33 = select i1 undef, ptr @g6, ptr %v32 %v33 = select i1 undef, ptr @g6, ptr %v32
%v34 = add i32 %a3, -15 %v34 = add i32 %a3, -15
%v35 = icmp ult i32 %v34, 2 %v35 = icmp ult i32 %v34, 2
%v36 = select i1 %v35, i8 4, i8 3 %v36 = select i1 %v35, i8 4, i8 3
%v37 = select i1 undef, i8 0, i8 %v36 %v37 = select i1 undef, i8 0, i8 %v36
%v38 = select i1 undef, i8 4, i8 %v37 %v38 = select i1 undef, i8 4, i8 %v37
br i1 undef, label %b2, label %b3 br i1 %c1, label %b2, label %b3
b2: ; preds = %b3, %b1 b2: ; preds = %b3, %b1
%v39 = phi ptr [ undef, %b3 ], [ %v33, %b1 ] %v39 = phi ptr [ undef, %b3 ], [ %v33, %b1 ]
%v40 = phi i8 [ undef, %b3 ], [ %v38, %b1 ] %v40 = phi i8 [ undef, %b3 ], [ %v38, %b1 ]
%v41 = getelementptr inbounds %s.5, ptr %a2, i32 0, i32 1 %v41 = getelementptr inbounds %s.5, ptr %a2, i32 0, i32 1
store ptr %v39, ptr %v41, align 4 store ptr %v39, ptr %v41, align 4
store i8 %v40, ptr undef, align 4 store i8 %v40, ptr undef, align 4
br label %b4 br label %b4
Show All 9 Lines

llvm/test/CodeGen/Hexagon/split-muxii.ll

; RUN: llc -march=hexagon -O2 -hexagon-expand-condsets=true -hexagon-gen-mux-threshold=4 < %s | FileCheck %s ; RUN: llc -march=hexagon -O2 -hexagon-expand-condsets=true -hexagon-gen-mux-threshold=4 < %s | FileCheck %s
; CHECK-NOT: mux(p ; CHECK-NOT: mux(p
target triple = "hexagon" target triple = "hexagon"
define void @f0() #0 { define void @f0(i1 %c0) #0 {
b0: b0:
%v0 = load i32, ptr null, align 4 %v0 = load i32, ptr null, align 4
%v1 = icmp slt i32 undef, %v0 %v1 = icmp slt i32 undef, %v0
%v2 = zext i1 %v1 to i32 %v2 = zext i1 %v1 to i32
%v3 = icmp sgt i32 undef, 0 %v3 = icmp sgt i32 undef, 0
%v4 = zext i1 %v3 to i32 %v4 = zext i1 %v3 to i32
%v5 = add nsw i32 %v2, %v4 %v5 = add nsw i32 %v2, %v4
store i32 %v5, ptr undef, align 4 store i32 %v5, ptr undef, align 4
br i1 undef, label %b1, label %b2 br i1 %c0, label %b1, label %b2
b1: ; preds = %b0 b1: ; preds = %b0
br label %b2 br label %b2
b2: ; preds = %b1, %b0 b2: ; preds = %b1, %b0
unreachable unreachable
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

llvm/test/CodeGen/Hexagon/split-vecpred.ll

; RUN: llc -march=hexagon < %s ; RUN: llc -march=hexagon < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Test that the splitVecPredRegs pass in the Hexagon Peephole pass does not ; Test that the splitVecPredRegs pass in the Hexagon Peephole pass does not
; move a vector predicate definition illegally, which ends up causing an assert ; move a vector predicate definition illegally, which ends up causing an assert
; later. The assert occurs because there is a use of a register that does not ; later. The assert occurs because there is a use of a register that does not
; have a correct definition. ; have a correct definition.
define void @f0() local_unnamed_addr #0 { define void @f0(i1 %c0, i1 %c1, i1 %c2) local_unnamed_addr #0 {
b0: b0:
br label %b1 br label %b1
b1: ; preds = %b0 b1: ; preds = %b0
br i1 undef, label %b2, label %b3 br i1 %c0, label %b2, label %b3
b2: ; preds = %b1 b2: ; preds = %b1
unreachable unreachable
b3: ; preds = %b1 b3: ; preds = %b1
br label %b4 br label %b4
b4: ; preds = %b3 b4: ; preds = %b3
br label %b5 br label %b5
b5: ; preds = %b4 b5: ; preds = %b4
br i1 undef, label %b13, label %b6 br i1 %c1, label %b13, label %b6
b6: ; preds = %b5 b6: ; preds = %b5
br label %b7 br label %b7
b7: ; preds = %b6 b7: ; preds = %b6
br label %b8 br label %b8
b8: ; preds = %b7 b8: ; preds = %b7
%v0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> undef, i32 -1) %v0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> undef, i32 -1)
br i1 undef, label %b9, label %b11 br i1 %c2, label %b9, label %b11
b9: ; preds = %b8 b9: ; preds = %b8
br label %b12 br label %b12
b10: ; preds = %b12 b10: ; preds = %b12
br label %b11 br label %b11
b11: ; preds = %b10, %b8 b11: ; preds = %b10, %b8
▲ Show 20 Lines • Show All 62 Lines • Show Last 20 Lines

llvm/test/CodeGen/Hexagon/stack-align-reset.ll

Show All 9 Lines
%struct.1 = type { ptr, i32, i32, i32 } %struct.1 = type { ptr, i32, i32, i32 }
@g0 = external hidden unnamed_addr constant [52 x i8], align 1 @g0 = external hidden unnamed_addr constant [52 x i8], align 1
@g1 = external hidden unnamed_addr constant [3 x i8], align 1 @g1 = external hidden unnamed_addr constant [3 x i8], align 1
declare extern_weak void @f0(i32, ptr, i32, ptr, ...) #0 declare extern_weak void @f0(i32, ptr, i32, ptr, ...) #0
declare void @f1(ptr, i32) #0 declare void @f1(ptr, i32) #0
define void @fred(ptr %a0) #0 { define void @fred(ptr %a0, i1 %c0, i1 %c1) #0 {
b1: b1:
%v2 = alloca %struct.0, align 4 %v2 = alloca %struct.0, align 4
%v3 = alloca %struct.2, i32 undef, align 8 %v3 = alloca %struct.2, i32 undef, align 8
br i1 undef, label %b5, label %b4 br i1 %c0, label %b5, label %b4
b4: ; preds = %b1 b4: ; preds = %b1
br label %b7 br label %b7
b5: ; preds = %b5, %b1 b5: ; preds = %b5, %b1
%v6 = getelementptr inbounds %struct.2, ptr %v3, i32 undef, i32 3 %v6 = getelementptr inbounds %struct.2, ptr %v3, i32 undef, i32 3
store ptr undef, ptr %v6, align 4 store ptr undef, ptr %v6, align 4
br label %b5 br label %b5
b7: ; preds = %b10, %b4 b7: ; preds = %b10, %b4
%v8 = call i32 @llvm.hexagon.V6.extractw(<16 x i32> zeroinitializer, i32 0) %v8 = call i32 @llvm.hexagon.V6.extractw(<16 x i32> zeroinitializer, i32 0)
br i1 icmp eq (ptr @f0, ptr null), label %b11, label %b9 br i1 icmp eq (ptr @f0, ptr null), label %b11, label %b9
b9: ; preds = %b7 b9: ; preds = %b7
call void (i32, ptr, i32, ptr, ...) @f0(i32 2, ptr @g0, i32 2346, ptr @g1, i32 %v8) call void (i32, ptr, i32, ptr, ...) @f0(i32 2, ptr @g0, i32 2346, ptr @g1, i32 %v8)
unreachable unreachable
b10: ; preds = %b11 b10: ; preds = %b11
call void @f1(ptr nonnull %v2, i32 28) call void @f1(ptr nonnull %v2, i32 28)
br label %b7 br label %b7
b11: ; preds = %b11, %b7 b11: ; preds = %b11, %b7
br i1 undef, label %b10, label %b11 br i1 %c1, label %b10, label %b11
} }
declare i32 @llvm.hexagon.V6.extractw(<16 x i32>, i32) #1 declare i32 @llvm.hexagon.V6.extractw(<16 x i32>, i32) #1
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }

llvm/test/CodeGen/Hexagon/store-vector-pred.ll

; RUN: llc -march=hexagon -hexagon-instsimplify=0 -hexagon-masked-vmem=0 < %s | FileCheck %s ; RUN: llc -march=hexagon -hexagon-instsimplify=0 -hexagon-masked-vmem=0 < %s | FileCheck %s
; This test checks that store a vector predicate of type v128i1 is lowered ; This test checks that store a vector predicate of type v128i1 is lowered
; without crashing. ; without crashing.
; CHECK: valign ; CHECK: valign
target triple = "hexagon" target triple = "hexagon"
define dso_local void @f0() local_unnamed_addr #0 { define dso_local void @f0(i1 %c0) local_unnamed_addr #0 {
b0: b0:
br i1 undef, label %b2, label %b1 br i1 %c0, label %b2, label %b1
b1: ; preds = %b0 b1: ; preds = %b0
%v0 = load i8, ptr undef, align 1 %v0 = load i8, ptr undef, align 1
%v1 = zext i8 %v0 to i32 %v1 = zext i8 %v0 to i32
%v2 = add nsw i32 %v1, -1 %v2 = add nsw i32 %v1, -1
%v3 = insertelement <128 x i32> undef, i32 %v2, i32 0 %v3 = insertelement <128 x i32> undef, i32 %v2, i32 0
%v4 = shufflevector <128 x i32> %v3, <128 x i32> undef, <128 x i32> zeroinitializer %v4 = shufflevector <128 x i32> %v3, <128 x i32> undef, <128 x i32> zeroinitializer
%v5 = icmp ule <128 x i32> undef, %v4 %v5 = icmp ule <128 x i32> undef, %v4
Show All 27 Lines

llvm/test/CodeGen/Hexagon/swp-art-deps-rec.ll

Show All 10 Lines
; Test that the artificial dependences are ignored while computing the ; Test that the artificial dependences are ignored while computing the
; circuits. ; circuits.
; The recurrence should be 1 here. If we do not ignore artificial deps, ; The recurrence should be 1 here. If we do not ignore artificial deps,
; it will be greater. ; it will be greater.
; CHECK: rec=1, ; CHECK: rec=1,
define void @foo(i32 %size) #0 { define void @foo(i32 %size, i1 %c0, i1 %c1) #0 {
entry: entry:
%add = add nsw i32 0, 4 %add = add nsw i32 0, 4
%shr = ashr i32 %size, 1 %shr = ashr i32 %size, 1
br i1 undef, label %L57.us, label %L57.us.ur br i1 %c0, label %L57.us, label %L57.us.ur
L57.us: L57.us:
%R9.0470.us = phi i32 [ %sub40.us.3, %L57.us ], [ undef, %entry ] %R9.0470.us = phi i32 [ %sub40.us.3, %L57.us ], [ undef, %entry ]
%sub40.us.3 = add i32 %R9.0470.us, -64 %sub40.us.3 = add i32 %R9.0470.us, -64
br i1 undef, label %L57.us, label %for.cond22.for.end_crit_edge.us.ur-lcssa br i1 %c1, label %L57.us, label %for.cond22.for.end_crit_edge.us.ur-lcssa
for.cond22.for.end_crit_edge.us.ur-lcssa: for.cond22.for.end_crit_edge.us.ur-lcssa:
%inc.us.3.lcssa = phi i32 [ undef, %L57.us ] %inc.us.3.lcssa = phi i32 [ undef, %L57.us ]
%sub40.us.3.lcssa = phi i32 [ %sub40.us.3, %L57.us ] %sub40.us.3.lcssa = phi i32 [ %sub40.us.3, %L57.us ]
%0 = icmp eq i32 %inc.us.3.lcssa, %shr %0 = icmp eq i32 %inc.us.3.lcssa, %shr
br i1 %0, label %for.cond22.for.end_crit_edge.us, label %L57.us.ur br i1 %0, label %for.cond22.for.end_crit_edge.us, label %L57.us.ur
L57.us.ur: L57.us.ur:
▲ Show 20 Lines • Show All 77 Lines • Show Last 20 Lines

llvm/test/CodeGen/Hexagon/swp-badorder.ll

; RUN: llc -march=hexagon -enable-pipeliner < %s ; RUN: llc -march=hexagon -enable-pipeliner < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0(ptr nocapture %a0) #0 { define void @f0(ptr nocapture %a0, i1 %c0) #0 {
b0: b0:
br i1 undef, label %b1, label %b2 br i1 %c0, label %b1, label %b2
b1: ; preds = %b1, %b0 b1: ; preds = %b1, %b0
%v0 = phi i64 [ %v9, %b1 ], [ 0, %b0 ] %v0 = phi i64 [ %v9, %b1 ], [ 0, %b0 ]
%v1 = phi i32 [ %v10, %b1 ], [ 0, %b0 ] %v1 = phi i32 [ %v10, %b1 ], [ 0, %b0 ]
%v2 = getelementptr inbounds i32, ptr %a0, i32 %v1 %v2 = getelementptr inbounds i32, ptr %a0, i32 %v1
%v3 = load i32, ptr %v2, align 4, !tbaa !0 %v3 = load i32, ptr %v2, align 4, !tbaa !0
%v4 = zext i32 %v3 to i64 %v4 = zext i32 %v3 to i64
%v5 = load i32, ptr undef, align 4, !tbaa !0 %v5 = load i32, ptr undef, align 4, !tbaa !0
Show All 23 Lines

llvm/test/CodeGen/Hexagon/swp-carried-1.ll

; RUN: llc -march=hexagon -rdf-opt=0 -disable-hexagon-misched -hexagon-initial-cfg-cleanup=0 -lsr-setupcost-depth-limit=1 < %s -pipeliner-experimental-cg=true | FileCheck %s ; RUN: llc -march=hexagon -rdf-opt=0 -disable-hexagon-misched -hexagon-initial-cfg-cleanup=0 -lsr-setupcost-depth-limit=1 < %s -pipeliner-experimental-cg=true | FileCheck %s
; Test that we generate the correct code when a loop carried value ; Test that we generate the correct code when a loop carried value
; is scheduled one stage earlier than it's use. The code in ; is scheduled one stage earlier than it's use. The code in
; isLoopCarried was returning false in this case, and the generated ; isLoopCarried was returning false in this case, and the generated
; code was missing an copy. ; code was missing an copy.
; CHECK: loop0(.LBB0_[[LOOP:.]], ; CHECK: loop0(.LBB0_[[LOOP:.]],
; CHECK: .LBB0_[[LOOP]]: ; CHECK: .LBB0_[[LOOP]]:
; CHECK: += mpy([[REG0:(r[0-9]+)]],r{{[0-9]+}}) ; CHECK: += mpy([[REG0:(r[0-9]+)]],r{{[0-9]+}})
; CHECK: [[REG0]] = r{{[0-9]+}} ; CHECK: [[REG0]] = r{{[0-9]+}}
; CHECK-NOT: [[REG0]] = memw ; CHECK-NOT: [[REG0]] = memw
; CHECK: endloop0 ; CHECK: endloop0
@g0 = external global [256 x i32], align 8 @g0 = external global [256 x i32], align 8
define void @f0() #0 { define void @f0(i1 %c0, i1 %c1, i1 %c2) #0 {
b0: b0:
br label %b1 br label %b1
b1: ; preds = %b1, %b0 b1: ; preds = %b1, %b0
br i1 undef, label %b2, label %b1 br i1 %c0, label %b2, label %b1
b2: ; preds = %b1 b2: ; preds = %b1
br label %b3 br label %b3
b3: ; preds = %b3, %b2 b3: ; preds = %b3, %b2
%v0 = phi ptr [ @g0, %b2 ], [ %v1, %b3 ] %v0 = phi ptr [ @g0, %b2 ], [ %v1, %b3 ]
%v1 = getelementptr i32, ptr %v0, i32 6 %v1 = getelementptr i32, ptr %v0, i32 6
br i1 undef, label %b4, label %b3 br i1 %c1, label %b4, label %b3
b4: ; preds = %b3 b4: ; preds = %b3
br i1 undef, label %b6, label %b5 br i1 %c2, label %b6, label %b5
b5: ; preds = %b5, %b4 b5: ; preds = %b5, %b4
%v2 = phi i64 [ %v19, %b5 ], [ undef, %b4 ] %v2 = phi i64 [ %v19, %b5 ], [ undef, %b4 ]
%v3 = phi ptr [ %v8, %b5 ], [ %v1, %b4 ] %v3 = phi ptr [ %v8, %b5 ], [ %v1, %b4 ]
%v4 = phi i32 [ %v9, %b5 ], [ undef, %b4 ] %v4 = phi i32 [ %v9, %b5 ], [ undef, %b4 ]
%v5 = phi i32 [ %v11, %b5 ], [ undef, %b4 ] %v5 = phi i32 [ %v11, %b5 ], [ undef, %b4 ]
%v6 = phi i32 [ %v5, %b5 ], [ undef, %b4 ] %v6 = phi i32 [ %v5, %b5 ], [ undef, %b4 ]
%v7 = phi i32 [ %v10, %b5 ], [ 0, %b4 ] %v7 = phi i32 [ %v10, %b5 ], [ 0, %b4 ]
Show All 21 Lines

llvm/test/CodeGen/Hexagon/swp-chain-refs.ll

; RUN: llc -march=hexagon -enable-pipeliner=true -stats -o /dev/null < %s \ ; RUN: llc -march=hexagon -enable-pipeliner=true -stats -o /dev/null < %s \
; RUN: 2>&1 -pipeliner-experimental-cg=true | FileCheck %s --check-prefix=STATS ; RUN: 2>&1 -pipeliner-experimental-cg=true | FileCheck %s --check-prefix=STATS
; REQUIRES: asserts ; REQUIRES: asserts
; Test that we do not schedule chained references too far apart, ; Test that we do not schedule chained references too far apart,
; which enables the loop to be pipelined. In this test, the loop should ; which enables the loop to be pipelined. In this test, the loop should
; not be pipelined when the chained references are constrained correctly. ; not be pipelined when the chained references are constrained correctly.
; STATS-NOT: 1 pipeliner - Number of loops software pipelined ; STATS-NOT: 1 pipeliner - Number of loops software pipelined
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0() #0 { define void @f0(i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4) #0 {
b0: b0:
br label %b2 br label %b2
b1: ; preds = %b6 b1: ; preds = %b6
br label %b7 br label %b7
b2: ; preds = %b6, %b0 b2: ; preds = %b6, %b0
br label %b3 br label %b3
b3: ; preds = %b5, %b2 b3: ; preds = %b5, %b2
br i1 undef, label %b4, label %b5 br i1 %c0, label %b4, label %b5
b4: ; preds = %b3 b4: ; preds = %b3
br label %b5 br label %b5
b5: ; preds = %b4, %b3 b5: ; preds = %b4, %b3
br i1 undef, label %b3, label %b6 br i1 %c1, label %b3, label %b6
b6: ; preds = %b5 b6: ; preds = %b5
br i1 undef, label %b1, label %b2 br i1 %c2, label %b1, label %b2
b7: ; preds = %b7, %b1 b7: ; preds = %b7, %b1
%v0 = phi i32 [ 0, %b1 ], [ %v4, %b7 ] %v0 = phi i32 [ 0, %b1 ], [ %v4, %b7 ]
%v1 = load i16, ptr undef, align 8, !tbaa !0 %v1 = load i16, ptr undef, align 8, !tbaa !0
%v2 = icmp sgt i16 %v1, undef %v2 = icmp sgt i16 %v1, undef
%v3 = select i1 %v2, i16 4, i16 undef %v3 = select i1 %v2, i16 4, i16 undef
store i16 %v3, ptr undef, align 2, !tbaa !0 store i16 %v3, ptr undef, align 2, !tbaa !0
store i16 -32768, ptr undef, align 2, !tbaa !0 store i16 -32768, ptr undef, align 2, !tbaa !0
%v4 = add i32 %v0, 1 %v4 = add i32 %v0, 1
%v5 = icmp eq i32 %v4, 5 %v5 = icmp eq i32 %v4, 5
br i1 %v5, label %b8, label %b7 br i1 %v5, label %b8, label %b7
b8: ; preds = %b7 b8: ; preds = %b7
br i1 undef, label %b9, label %b10 br i1 %c3, label %b9, label %b10
b9: ; preds = %b8 b9: ; preds = %b8
br label %b10 br label %b10
b10: ; preds = %b9, %b8 b10: ; preds = %b9, %b8
br i1 undef, label %b11, label %b12 br i1 %c4, label %b11, label %b12
b11: ; preds = %b10 b11: ; preds = %b10
unreachable unreachable
b12: ; preds = %b10 b12: ; preds = %b10
ret void ret void
} }
attributes #0 = { nounwind "target-cpu"="hexagonv55" } attributes #0 = { nounwind "target-cpu"="hexagonv55" }
!0 = !{!1, !1, i64 0} !0 = !{!1, !1, i64 0}
!1 = !{!"short", !2} !1 = !{!"short", !2}
!2 = !{!"omnipotent char", !3} !2 = !{!"omnipotent char", !3}
!3 = !{!"Simple C/C++ TBAA"} !3 = !{!"Simple C/C++ TBAA"}

llvm/test/CodeGen/Hexagon/swp-change-dep-cycle.ll

; RUN: llc -march=hexagon -O3 < %s ; RUN: llc -march=hexagon -O3 < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Don't change the dependences if it's going to cause a cycle. ; Don't change the dependences if it's going to cause a cycle.
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0(ptr nocapture %a0, i32 %a1) #0 { define void @f0(ptr nocapture %a0, i32 %a1, i1 %c0) #0 {
b0: b0:
br i1 undef, label %b1, label %b2 br i1 %c0, label %b1, label %b2
b1: ; preds = %b1, %b0 b1: ; preds = %b1, %b0
%v0 = phi ptr [ undef, %b1 ], [ undef, %b0 ] %v0 = phi ptr [ undef, %b1 ], [ undef, %b0 ]
%v1 = phi i32 [ %v20, %b1 ], [ 1, %b0 ] %v1 = phi i32 [ %v20, %b1 ], [ 1, %b0 ]
%v2 = phi ptr [ %v6, %b1 ], [ %a0, %b0 ] %v2 = phi ptr [ %v6, %b1 ], [ %a0, %b0 ]
%v3 = load i8, ptr %v2, align 1 %v3 = load i8, ptr %v2, align 1
%v4 = zext i8 %v3 to i32 %v4 = zext i8 %v3 to i32
%v5 = mul nsw i32 %v4, 3 %v5 = mul nsw i32 %v4, 3
Show All 25 Lines

llvm/test/CodeGen/Hexagon/swp-change-dep.ll

; RUN: llc -march=hexagon -enable-aa-sched-mi -enable-pipeliner < %s ; RUN: llc -march=hexagon -enable-aa-sched-mi -enable-pipeliner < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0() #0 { define void @f0(i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6) #0 {
b0: b0:
br i1 undef, label %b1, label %b2 br i1 %c0, label %b1, label %b2
b1: ; preds = %b0 b1: ; preds = %b0
unreachable unreachable
b2: ; preds = %b0 b2: ; preds = %b0
br i1 undef, label %b3, label %b4 br i1 %c1, label %b3, label %b4
b3: ; preds = %b2 b3: ; preds = %b2
unreachable unreachable
b4: ; preds = %b2 b4: ; preds = %b2
br i1 undef, label %b5, label %b6 br i1 %c2, label %b5, label %b6
b5: ; preds = %b4 b5: ; preds = %b4
unreachable unreachable
b6: ; preds = %b4 b6: ; preds = %b4
br label %b7 br label %b7
b7: ; preds = %b7, %b6 b7: ; preds = %b7, %b6
br i1 undef, label %b8, label %b7 br i1 %c3, label %b8, label %b7
b8: ; preds = %b7 b8: ; preds = %b7
br i1 undef, label %b15, label %b9 br i1 %c4, label %b15, label %b9
b9: ; preds = %b8 b9: ; preds = %b8
br label %b10 br label %b10
b10: ; preds = %b10, %b9 b10: ; preds = %b10, %b9
br i1 undef, label %b11, label %b10 br i1 %c5, label %b11, label %b10
b11: ; preds = %b10 b11: ; preds = %b10
br label %b12 br label %b12
b12: ; preds = %b12, %b11 b12: ; preds = %b12, %b11
br i1 undef, label %b13, label %b12 br i1 %c6, label %b13, label %b12
b13: ; preds = %b13, %b12 b13: ; preds = %b13, %b12
%v0 = phi i32 [ %v5, %b13 ], [ 0, %b12 ] %v0 = phi i32 [ %v5, %b13 ], [ 0, %b12 ]
%v1 = getelementptr inbounds [11 x i32], ptr undef, i32 0, i32 %v0 %v1 = getelementptr inbounds [11 x i32], ptr undef, i32 0, i32 %v0
%v2 = load i32, ptr %v1, align 4 %v2 = load i32, ptr %v1, align 4
%v3 = add i32 %v2, 1 %v3 = add i32 %v2, 1
%v4 = lshr i32 %v3, 1 %v4 = lshr i32 %v3, 1
store i32 %v4, ptr %v1, align 4 store i32 %v4, ptr %v1, align 4
Show All 13 Lines

llvm/test/CodeGen/Hexagon/swp-const-tc1.ll

; RUN: llc -march=hexagon -enable-pipeliner -enable-pipeliner-opt-size \ ; RUN: llc -march=hexagon -enable-pipeliner -enable-pipeliner-opt-size \
; RUN: -verify-machineinstrs -hexagon-initial-cfg-cleanup=0 \ ; RUN: -verify-machineinstrs -hexagon-initial-cfg-cleanup=0 \
; RUN: -enable-aa-sched-mi=false -hexagon-expand-condsets=0 \ ; RUN: -enable-aa-sched-mi=false -hexagon-expand-condsets=0 \
; RUN: < %s -pipeliner-experimental-cg=true | FileCheck %s ; RUN: < %s -pipeliner-experimental-cg=true | FileCheck %s
; Disable expand-condsets because it will assert on undefined registers.
; Test that we change the CFG correctly for pipelined loops where the trip ; Test that we change the CFG correctly for pipelined loops where the trip
; count is a compile-time constant, and the trip count is the same as the ; count is a compile-time constant, and the trip count is the same as the
; number of prolog blocks (i.e., stages). ; number of prolog blocks (i.e., stages).
; CHECK: memb(r{{[0-9]+}}+#0) = ; CHECK: memb(r{{[0-9]+}}+#0) =
; CHECK: memb(r{{[0-9]+}}+#0) = ; CHECK: memb(r{{[0-9]+}}+#0) =
; Function Attrs: nounwind optsize ; Function Attrs: nounwind optsize
define void @f0(i1 %x) #0 { define void @f0(i1 %x, i1 %c0, i1 %c1) #0 {
b0: b0:
br label %b1 br label %b1
b1: ; preds = %b5, %b0 b1: ; preds = %b5, %b0
%v0 = load i16, ptr undef, align 2, !tbaa !0 %v0 = load i16, ptr undef, align 2, !tbaa !0
%v1 = sext i16 %v0 to i32 %v1 = sext i16 %v0 to i32
%v2 = load i16, ptr undef, align 2, !tbaa !0 %v2 = load i16, ptr undef, align 2, !tbaa !0
%v3 = sext i16 %v2 to i32 %v3 = sext i16 %v2 to i32
Show All 22 Linesb3: ; preds = %b3, %b2
%v20 = lshr i32 %v19, 6 %v20 = lshr i32 %v19, 6
%v21 = trunc i32 %v20 to i8 %v21 = trunc i32 %v20 to i8
store i8 %v21, ptr undef, align 1, !tbaa !4 store i8 %v21, ptr undef, align 1, !tbaa !4
%v22 = add i32 %v6, 1 %v22 = add i32 %v6, 1
%v23 = icmp eq i32 %v22, 2 %v23 = icmp eq i32 %v22, 2
br i1 %v23, label %b4, label %b3 br i1 %v23, label %b4, label %b3
b4: ; preds = %b3 b4: ; preds = %b3
br i1 undef, label %b5, label %b2 br i1 %c0, label %b5, label %b2
b5: ; preds = %b4 b5: ; preds = %b4
br i1 undef, label %b1, label %b6 br i1 %c1, label %b1, label %b6
b6: ; preds = %b5 b6: ; preds = %b5
ret void ret void
} }
attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" } attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" }
!0 = !{!1, !1, i64 0} !0 = !{!1, !1, i64 0}
!1 = !{!"short", !2} !1 = !{!"short", !2}
!2 = !{!"omnipotent char", !3} !2 = !{!"omnipotent char", !3}
!3 = !{!"Simple C/C++ TBAA"} !3 = !{!"Simple C/C++ TBAA"}
!4 = !{!2, !2, i64 0} !4 = !{!2, !2, i64 0}

llvm/test/CodeGen/Hexagon/swp-cse-phi.ll

; RUN: llc -march=hexagon -enable-pipeliner < %s ; RUN: llc -march=hexagon -enable-pipeliner < %s
; REQUIRES: asserts ; REQUIRES: asserts
; This test checks that we don't assert when the Phi value from the ; This test checks that we don't assert when the Phi value from the
; loop is actually defined prior to the loop, e.g., from CSE.
define fastcc void @f0() { define fastcc void @f0(i1 %c0, i1 %c1, i1 %c2, i1 %c3) {
b0: b0:
br i1 undef, label %b10, label %b1 br i1 %c0, label %b10, label %b1
b1: ; preds = %b0 b1: ; preds = %b0
br i1 undef, label %b3, label %b2 br i1 %c1, label %b3, label %b2
b2: ; preds = %b1 b2: ; preds = %b1
br label %b8 br label %b8
b3: ; preds = %b1 b3: ; preds = %b1
br i1 undef, label %b4, label %b6 br i1 %c2, label %b4, label %b6
b4: ; preds = %b3 b4: ; preds = %b3
%v0 = load i16, ptr undef, align 2 %v0 = load i16, ptr undef, align 2
br label %b7 br label %b7
b5: ; preds = %b7 b5: ; preds = %b7
br label %b6 br label %b6
b6: ; preds = %b5, %b3 b6: ; preds = %b5, %b3
%v1 = phi i16 [ %v9, %b5 ], [ 0, %b3 ] %v1 = phi i16 [ %v9, %b5 ], [ 0, %b3 ]
br i1 undef, label %b10, label %b9 br i1 %c3, label %b10, label %b9
b7: ; preds = %b7, %b4 b7: ; preds = %b7, %b4
%v2 = phi i16 [ 0, %b7 ], [ %v0, %b4 ] %v2 = phi i16 [ 0, %b7 ], [ %v0, %b4 ]
%v3 = phi i16 [ %v9, %b7 ], [ 0, %b4 ] %v3 = phi i16 [ %v9, %b7 ], [ 0, %b4 ]
%v4 = phi i32 [ %v10, %b7 ], [ undef, %b4 ] %v4 = phi i32 [ %v10, %b7 ], [ undef, %b4 ]
%v5 = or i16 0, %v3 %v5 = or i16 0, %v3
%v6 = or i16 0, %v5 %v6 = or i16 0, %v5
%v7 = or i16 0, %v6 %v7 = or i16 0, %v6
Show All 15 Lines

llvm/test/CodeGen/Hexagon/swp-dag-phi1.ll

; RUN: llc -march=hexagon -enable-pipeliner < %s ; RUN: llc -march=hexagon -enable-pipeliner < %s
; REQUIRES: asserts ; REQUIRES: asserts
; This test check that a dependence is created between a Phi and it's uses. ; This test check that a dependence is created between a Phi and it's uses.
; An assert occurs if the Phi dependences are not correct. ; An assert occurs if the Phi dependences are not correct.
define void @f0(ptr nocapture %a0, i32 %a1) #0 { define void @f0(ptr nocapture %a0, i32 %a1, i1 %c0) #0 {
b0: b0:
br i1 undef, label %b1, label %b2 br i1 %c0, label %b1, label %b2
b1: ; preds = %b1, %b0 b1: ; preds = %b1, %b0
%v0 = phi float [ %v1, %b1 ], [ undef, %b0 ] %v0 = phi float [ %v1, %b1 ], [ undef, %b0 ]
%v1 = phi float [ %v13, %b1 ], [ undef, %b0 ] %v1 = phi float [ %v13, %b1 ], [ undef, %b0 ]
%v2 = phi ptr [ null, %b1 ], [ %a0, %b0 ] %v2 = phi ptr [ null, %b1 ], [ %a0, %b0 ]
%v3 = phi i32 [ %v14, %b1 ], [ 0, %b0 ] %v3 = phi i32 [ %v14, %b1 ], [ 0, %b0 ]
%v4 = phi float [ %v5, %b1 ], [ undef, %b0 ] %v4 = phi float [ %v5, %b1 ], [ undef, %b0 ]
%v5 = load float, ptr %v2, align 4 %v5 = load float, ptr %v2, align 4
Show All 18 Lines

llvm/test/CodeGen/Hexagon/swp-dep-neg-offset.ll

; RUN: llc -march=hexagon -enable-pipeliner -hexagon-initial-cfg-cleanup=0 < %s -pipeliner-experimental-cg=true | FileCheck %s ; RUN: llc -march=hexagon -enable-pipeliner -hexagon-initial-cfg-cleanup=0 < %s -pipeliner-experimental-cg=true | FileCheck %s
; Test that the code that changes the dependences does not allow ; Test that the code that changes the dependences does not allow
; a load with a negative offset to be overlapped with the post ; a load with a negative offset to be overlapped with the post
; increment store that generates the base register. ; increment store that generates the base register.
; CHECK: loop0(.LBB0_[[LOOP:.]], ; CHECK: loop0(.LBB0_[[LOOP:.]],
; CHECK: .LBB0_[[LOOP]]: ; CHECK: .LBB0_[[LOOP]]:
; CHECK: = mem{{u?}}b([[REG:(r[0-9])+]]+#-1) ; CHECK: = mem{{u?}}b([[REG:(r[0-9])+]]+#-1)
; CHECK-NOT: memb([[REG]]{{\+?}}#0) = ; CHECK-NOT: memb([[REG]]{{\+?}}#0) =
; CHECK: } ; CHECK: }
; CHECK: }{{[ \t]*}}:endloop0 ; CHECK: }{{[ \t]*}}:endloop0
@g0 = external global [1000000 x i8], align 8 @g0 = external global [1000000 x i8], align 8
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0(i32 %a0, ptr %a1, ptr %a2) #0 { define void @f0(i32 %a0, ptr %a1, ptr %a2, i1 %c0, i1 %c1, i1 %c2, i1 %c3) #0 {
b0: b0:
br i1 undef, label %b1, label %b7 br i1 %c0, label %b1, label %b7
b1: ; preds = %b0 b1: ; preds = %b0
br i1 undef, label %b2, label %b6 br i1 %c1, label %b2, label %b6
b2: ; preds = %b5, %b1 b2: ; preds = %b5, %b1
br i1 undef, label %b3, label %b5 br i1 %c2, label %b3, label %b5
b3: ; preds = %b3, %b2 b3: ; preds = %b3, %b2
%v0 = phi i32 [ %v17, %b3 ], [ 1, %b2 ] %v0 = phi i32 [ %v17, %b3 ], [ 1, %b2 ]
%v1 = phi i32 [ %v16, %b3 ], [ 0, %b2 ] %v1 = phi i32 [ %v16, %b3 ], [ 0, %b2 ]
%v2 = add nsw i32 %v0, -1 %v2 = add nsw i32 %v0, -1
%v3 = getelementptr inbounds [1000 x i8], ptr %a1, i32 undef, i32 %v2 %v3 = getelementptr inbounds [1000 x i8], ptr %a1, i32 undef, i32 %v2
%v4 = load i8, ptr %v3, align 1, !tbaa !0 %v4 = load i8, ptr %v3, align 1, !tbaa !0
%v5 = zext i8 %v4 to i32 %v5 = zext i8 %v4 to i32
Show All 12 Linesb3: ; preds = %b3, %b2
%v17 = add nsw i32 %v0, 1 %v17 = add nsw i32 %v0, 1
%v18 = icmp eq i32 %v17, %a0 %v18 = icmp eq i32 %v17, %a0
br i1 %v18, label %b4, label %b3 br i1 %v18, label %b4, label %b3
b4: ; preds = %b3 b4: ; preds = %b3
br label %b5 br label %b5
b5: ; preds = %b4, %b2 b5: ; preds = %b4, %b2
br i1 undef, label %b6, label %b2 br i1 %c3, label %b6, label %b2
b6: ; preds = %b5, %b1 b6: ; preds = %b5, %b1
unreachable unreachable
b7: ; preds = %b0 b7: ; preds = %b0
ret void ret void
} }
attributes #0 = { nounwind "target-cpu"="hexagonv55" } attributes #0 = { nounwind "target-cpu"="hexagonv55" }
!0 = !{!1, !1, i64 0} !0 = !{!1, !1, i64 0}
!1 = !{!"omnipotent char", !2, i64 0} !1 = !{!"omnipotent char", !2, i64 0}
!2 = !{!"Simple C/C++ TBAA"} !2 = !{!"Simple C/C++ TBAA"}

llvm/test/CodeGen/Hexagon/swp-epilog-phi12.ll

; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 -pipeliner-experimental-cg=true < %s | FileCheck %s ; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 -pipeliner-experimental-cg=true < %s | FileCheck %s
; Test epilogue generation when reading loop-carried dependency from a previous ; Test epilogue generation when reading loop-carried dependency from a previous
; stage. The first epilogue should read value from iteration N-1 of the kernel. ; stage. The first epilogue should read value from iteration N-1 of the kernel.
; CHECK: loop0 ; CHECK: loop0
; CHECK: r{{[0-9]+}} = add([[REG0:r([0-9]+)]],#8) ; CHECK: r{{[0-9]+}} = add([[REG0:r([0-9]+)]],#8)
; CHECK: [[REG0]] = [[REG1:r([0-9]+)]] ; CHECK: [[REG0]] = [[REG1:r([0-9]+)]]
; CHECK: endloop0 ; CHECK: endloop0
; CHECK: = add([[REG1]],#8) ; CHECK: = add([[REG1]],#8)
; Function Attrs: nounwind ; Function Attrs: nounwind
define ptr @f0(ptr nocapture readonly %a0, i32 %a1) #0 { define ptr @f0(ptr nocapture readonly %a0, i32 %a1, i1 %c0) #0 {
b0: b0:
%v0 = alloca [129 x i32], align 8 %v0 = alloca [129 x i32], align 8
br i1 undef, label %b1, label %b3 br i1 %c0, label %b1, label %b3
b1: ; preds = %b0 b1: ; preds = %b0
br label %b2 br label %b2
b2: ; preds = %b2, %b1 b2: ; preds = %b2, %b1
%v1 = phi ptr [ %a0, %b1 ], [ %v2, %b2 ] %v1 = phi ptr [ %a0, %b1 ], [ %v2, %b2 ]
%v2 = phi ptr [ undef, %b1 ], [ %v15, %b2 ] %v2 = phi ptr [ undef, %b1 ], [ %v15, %b2 ]
%v3 = phi ptr [ null, %b1 ], [ %v4, %b2 ] %v3 = phi ptr [ null, %b1 ], [ %v4, %b2 ]
Show All 30 Lines

llvm/test/CodeGen/Hexagon/swp-epilog-phi13.ll

; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 -pipeliner-experimental-cg=true < %s | FileCheck %s ; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 -pipeliner-experimental-cg=true < %s | FileCheck %s
; Test epilogue generation when reading loop-carried dependency in stage 1 from ; Test epilogue generation when reading loop-carried dependency in stage 1 from
; stage 0. Make sure the illegal phi the expender creates gets cleaned up ; stage 0. Make sure the illegal phi the expender creates gets cleaned up
; correctly during peeling ; correctly during peeling
; CHECK: loop0 ; CHECK: loop0
; CHECK: [[REG0:r([0-9]+)]] = add(r{{[0-9]+}},#8) ; CHECK: [[REG0:r([0-9]+)]] = add(r{{[0-9]+}},#8)
; CHECK: memw([[REG0]]+#0) ; CHECK: memw([[REG0]]+#0)
; CHECK: endloop0 ; CHECK: endloop0
; Function Attrs: nounwind ; Function Attrs: nounwind
define ptr @f0(ptr nocapture readonly %a0, i32 %a1, i32 %a2, i32 %a3, ptr %b) #0 { define ptr @f0(ptr nocapture readonly %a0, i32 %a1, i32 %a2, i32 %a3, ptr %b, i1 %c0) #0 {
b0: b0:
br i1 undef, label %b1, label %b3 br i1 %c0, label %b1, label %b3
b1: ; preds = %b0 b1: ; preds = %b0
br label %b2 br label %b2
b2: ; preds = %b2, %b1 b2: ; preds = %b2, %b1
%v1 = phi ptr [ %a0, %b1 ], [ %v2, %b2 ] %v1 = phi ptr [ %a0, %b1 ], [ %v2, %b2 ]
%v2 = phi ptr [ undef, %b1 ], [ %v15, %b2 ] %v2 = phi ptr [ undef, %b1 ], [ %v15, %b2 ]
%v3 = phi ptr [ null, %b1 ], [ %v4, %b2 ] %v3 = phi ptr [ null, %b1 ], [ %v4, %b2 ]
Show All 34 Lines

llvm/test/CodeGen/Hexagon/swp-epilog-phi8.ll

; RUN: llc -march=hexagon -mno-pairing -mno-compound -hexagon-initial-cfg-cleanup=0 < %s -pipeliner-experimental-cg=true | FileCheck %s ; RUN: llc -march=hexagon -mno-pairing -mno-compound -hexagon-initial-cfg-cleanup=0 < %s -pipeliner-experimental-cg=true | FileCheck %s
; XFAIL: * ; XFAIL: *
; Test that we generate the correct phi names in the epilog when the pipeliner ; Test that we generate the correct phi names in the epilog when the pipeliner
; schedules a phi and it's loop definition in different stages, e.g., a phi is ; schedules a phi and it's loop definition in different stages, e.g., a phi is
; scheduled in stage 2, but the loop definition in scheduled in stage 0). The ; scheduled in stage 2, but the loop definition in scheduled in stage 0). The
; code in generateExistingPhis was generating the wrong name for the last ; code in generateExistingPhis was generating the wrong name for the last
; epilog bock. ; epilog bock.
; CHECK: endloop0 ; CHECK: endloop0
; CHECK: sub([[REG:r([0-9]+)]],r{{[0-9]+}}):sat ; CHECK: sub([[REG:r([0-9]+)]],r{{[0-9]+}}):sat
; CHECK-NOT: sub([[REG]],r{{[0-9]+}}):sat ; CHECK-NOT: sub([[REG]],r{{[0-9]+}}):sat
define void @f0() { define void @f0(i1 %c0) {
b0: b0:
br label %b1 br label %b1
b1: ; preds = %b1, %b0 b1: ; preds = %b1, %b0
br i1 undef, label %b2, label %b1 br i1 %c0, label %b2, label %b1
b2: ; preds = %b1 b2: ; preds = %b1
br label %b3 br label %b3
b3: ; preds = %b3, %b2 b3: ; preds = %b3, %b2
%v0 = phi i32 [ %v8, %b3 ], [ 7, %b2 ] %v0 = phi i32 [ %v8, %b3 ], [ 7, %b2 ]
%v1 = phi i32 [ %v6, %b3 ], [ undef, %b2 ] %v1 = phi i32 [ %v6, %b3 ], [ undef, %b2 ]
%v2 = phi i32 [ %v1, %b3 ], [ undef, %b2 ] %v2 = phi i32 [ %v1, %b3 ], [ undef, %b2 ]
Show All 18 Lines

llvm/test/CodeGen/Hexagon/swp-epilog-phi9.ll

; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s ; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s
; Test that we generate the correct Phi name in the last couple of epilog ; Test that we generate the correct Phi name in the last couple of epilog
; blocks, when there are 3 epilog blocks. The Phi was scheduled in stage ; blocks, when there are 3 epilog blocks. The Phi was scheduled in stage
; 2, so the computation for the number of Phis needs to be adjusted when ; 2, so the computation for the number of Phis needs to be adjusted when
; the incoming prolog block is from prolog 0 or prolog 1. ; the incoming prolog block is from prolog 0 or prolog 1.
; Note: the pipeliner no longer generates a 3 stage pipeline for this test. ; Note: the pipeliner no longer generates a 3 stage pipeline for this test.
; CHECK: loop0 ; CHECK: loop0
; CHECK: [[REG0:r([0-9]+)]] = add(r{{[0-8]+}},#8) ; CHECK: [[REG0:r([0-9]+)]] = add(r{{[0-8]+}},#8)
; CHECK: endloop0 ; CHECK: endloop0
; CHECK: [[REG0]] = add(r{{[0-9]+}},#8) ; CHECK: [[REG0]] = add(r{{[0-9]+}},#8)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0(ptr nocapture readonly %a0, i32 %a1) #0 { define void @f0(ptr nocapture readonly %a0, i32 %a1, i1 %c0) #0 {
b0: b0:
%v0 = alloca [129 x i32], align 8 %v0 = alloca [129 x i32], align 8
br i1 undef, label %b1, label %b3 br i1 %c0, label %b1, label %b3
b1: ; preds = %b0 b1: ; preds = %b0
br label %b2 br label %b2
b2: ; preds = %b2, %b1 b2: ; preds = %b2, %b1
%v1 = phi ptr [ %a0, %b1 ], [ %v2, %b2 ] %v1 = phi ptr [ %a0, %b1 ], [ %v2, %b2 ]
%v2 = phi ptr [ undef, %b1 ], [ %v15, %b2 ] %v2 = phi ptr [ undef, %b1 ], [ %v15, %b2 ]
%v3 = phi ptr [ null, %b1 ], [ %v4, %b2 ] %v3 = phi ptr [ null, %b1 ], [ %v4, %b2 ]
Show All 29 Lines

llvm/test/CodeGen/Hexagon/swp-epilog-reuse.ll

; RUN: llc -fp-contract=fast -O3 -march=hexagon -mcpu=hexagonv5 < %s ; RUN: llc -fp-contract=fast -O3 -march=hexagon -mcpu=hexagonv5 < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Test that the pipeliner doesn't ICE due because the PHI generation ; Test that the pipeliner doesn't ICE due because the PHI generation
; code in the epilog does not attempt to reuse an existing PHI. ; code in the epilog does not attempt to reuse an existing PHI.
define void @test(ptr noalias %srcImg, i32 %width, ptr noalias %dstImg) { define void @test(ptr noalias %srcImg, i32 %width, ptr noalias %dstImg, i1 %c0, i1 %c1) {
entry.split: entry.split:
%shr = lshr i32 %width, 1 %shr = lshr i32 %width, 1
%incdec.ptr253 = getelementptr inbounds float, ptr %dstImg, i32 2 %incdec.ptr253 = getelementptr inbounds float, ptr %dstImg, i32 2
br i1 undef, label %for.body, label %for.end br i1 %c0, label %for.body, label %for.end
for.body: for.body:
%dst.21518.reg2mem.0 = phi ptr [ null, %while.end712 ], [ %incdec.ptr253, %entry.split ] %dst.21518.reg2mem.0 = phi ptr [ null, %while.end712 ], [ %incdec.ptr253, %entry.split ]
%dstEnd.01519 = phi ptr [ %add.ptr725, %while.end712 ], [ undef, %entry.split ] %dstEnd.01519 = phi ptr [ %add.ptr725, %while.end712 ], [ undef, %entry.split ]
%add.ptr367 = getelementptr inbounds float, ptr %srcImg, i32 undef %add.ptr367 = getelementptr inbounds float, ptr %srcImg, i32 undef
%dst.31487 = getelementptr inbounds float, ptr %dst.21518.reg2mem.0, i32 1 %dst.31487 = getelementptr inbounds float, ptr %dst.21518.reg2mem.0, i32 1
br i1 undef, label %while.body661.preheader, label %while.end712 br i1 %c1, label %while.body661.preheader, label %while.end712
while.body661.preheader: while.body661.preheader:
%scevgep1941 = getelementptr float, ptr %add.ptr367, i32 1 %scevgep1941 = getelementptr float, ptr %add.ptr367, i32 1
br label %while.body661.ur br label %while.body661.ur
while.body661.ur: while.body661.ur:
%lsr.iv1942 = phi ptr [ %scevgep1941, %while.body661.preheader ], [ undef, %while.body661.ur ] %lsr.iv1942 = phi ptr [ %scevgep1941, %while.body661.preheader ], [ undef, %while.body661.ur ]
%col1.31508.reg2mem.0.ur = phi float [ %col3.31506.reg2mem.0.ur, %while.body661.ur ], [ undef, %while.body661.preheader ] %col1.31508.reg2mem.0.ur = phi float [ %col3.31506.reg2mem.0.ur, %while.body661.ur ], [ undef, %while.body661.preheader ]
Show All 39 Lines

llvm/test/CodeGen/Hexagon/swp-epilog-reuse2.ll

; RUN: llc -fp-contract=fast -O3 -march=hexagon < %s ; RUN: llc -fp-contract=fast -O3 -march=hexagon < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Test that the pipeliner doesn't ICE due because the PHI generation ; Test that the pipeliner doesn't ICE due because the PHI generation
; code in the epilog does not attempt to reuse an existing PHI. ; code in the epilog does not attempt to reuse an existing PHI.
; Similar test case as swp-epilog-reuse.ll but with a couple of ; Similar test case as swp-epilog-reuse.ll but with a couple of
; differences. ; differences.
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0(ptr noalias %a0, ptr noalias %a1) #0 { define void @f0(ptr noalias %a0, ptr noalias %a1, i1 %c0, i1 %c1, i1 %c2) #0 {
b0: b0:
%v0 = getelementptr inbounds float, ptr %a1, i32 2 %v0 = getelementptr inbounds float, ptr %a1, i32 2
br i1 undef, label %b1, label %b6 br i1 %c0, label %b1, label %b6
b1: ; preds = %b5, %b0 b1: ; preds = %b5, %b0
%v1 = phi ptr [ undef, %b5 ], [ %v0, %b0 ] %v1 = phi ptr [ undef, %b5 ], [ %v0, %b0 ]
%v2 = phi ptr [ %v32, %b5 ], [ undef, %b0 ] %v2 = phi ptr [ %v32, %b5 ], [ undef, %b0 ]
%v3 = getelementptr inbounds float, ptr %a0, i32 undef %v3 = getelementptr inbounds float, ptr %a0, i32 undef
%v4 = getelementptr inbounds float, ptr %v1, i32 1 %v4 = getelementptr inbounds float, ptr %v1, i32 1
br i1 undef, label %b2, label %b5 br i1 %c1, label %b2, label %b5
b2: ; preds = %b1 b2: ; preds = %b1
%v5 = getelementptr float, ptr %v3, i32 1 %v5 = getelementptr float, ptr %v3, i32 1
br label %b3 br label %b3
b3: ; preds = %b3, %b2 b3: ; preds = %b3, %b2
%v6 = phi ptr [ %v5, %b2 ], [ %v20, %b3 ] %v6 = phi ptr [ %v5, %b2 ], [ %v20, %b3 ]
%v7 = phi float [ %v19, %b3 ], [ undef, %b2 ] %v7 = phi float [ %v19, %b3 ], [ undef, %b2 ]
Show All 23 Linesb5: ; preds = %b4, %b1
%v26 = fadd float %v25, undef %v26 = fadd float %v25, undef
%v27 = fadd float undef, %v26 %v27 = fadd float undef, %v26
%v28 = fadd float undef, %v27 %v28 = fadd float undef, %v27
%v29 = fpext float %v28 to double %v29 = fpext float %v28 to double
%v30 = fmul double %v29, 0x3F7111112119E8FB %v30 = fmul double %v29, 0x3F7111112119E8FB
%v31 = fptrunc double %v30 to float %v31 = fptrunc double %v30 to float
store float %v31, ptr %v23, align 4, !tbaa !0 store float %v31, ptr %v23, align 4, !tbaa !0
%v32 = getelementptr inbounds float, ptr %v2, i32 undef %v32 = getelementptr inbounds float, ptr %v2, i32 undef
br i1 undef, label %b1, label %b6 br i1 %c2, label %b1, label %b6
b6: ; preds = %b5, %b0 b6: ; preds = %b5, %b0
ret void ret void
} }
attributes #0 = { nounwind "target-cpu"="hexagonv55" } attributes #0 = { nounwind "target-cpu"="hexagonv55" }
!0 = !{!1, !1, i64 0} !0 = !{!1, !1, i64 0}
!1 = !{!"omnipotent char", !2, i64 0} !1 = !{!"omnipotent char", !2, i64 0}
!2 = !{!"Simple C/C++ TBAA"} !2 = !{!"Simple C/C++ TBAA"}

llvm/test/CodeGen/Hexagon/swp-epilog-reuse3.ll

; RUN: llc -march=hexagon -enable-pipeliner < %s ; RUN: llc -march=hexagon -enable-pipeliner < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Test that the pipeliner doesn't ICE due to incorrect PHI ; Test that the pipeliner doesn't ICE due to incorrect PHI
; generation code that attemps to reuse an exsting PHI. ; generation code that attemps to reuse an exsting PHI.
; Similar to the other swp-epillog-reuse test, but from a ; Similar to the other swp-epillog-reuse test, but from a
; different test case. ; different test case.
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare i32 @llvm.hexagon.S2.asl.r.r.sat(i32, i32) #0 declare i32 @llvm.hexagon.S2.asl.r.r.sat(i32, i32) #0
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0() #1 { define void @f0(i1 %c0, i1 %c1) #1 {
b0: b0:
br label %b1 br label %b1
b1: ; preds = %b1, %b0 b1: ; preds = %b1, %b0
br i1 undef, label %b2, label %b1 br i1 %c0, label %b2, label %b1
b2: ; preds = %b2, %b1 b2: ; preds = %b2, %b1
br i1 undef, label %b3, label %b2 br i1 %c1, label %b3, label %b2
b3: ; preds = %b3, %b2 b3: ; preds = %b3, %b2
%v0 = phi i16 [ %v10, %b3 ], [ undef, %b2 ] %v0 = phi i16 [ %v10, %b3 ], [ undef, %b2 ]
%v1 = phi i16 [ %v0, %b3 ], [ undef, %b2 ] %v1 = phi i16 [ %v0, %b3 ], [ undef, %b2 ]
%v2 = phi i32 [ %v26, %b3 ], [ undef, %b2 ] %v2 = phi i32 [ %v26, %b3 ], [ undef, %b2 ]
%v3 = phi ptr [ undef, %b3 ], [ undef, %b2 ] %v3 = phi ptr [ undef, %b3 ], [ undef, %b2 ]
%v4 = phi ptr [ %v5, %b3 ], [ undef, %b2 ] %v4 = phi ptr [ %v5, %b3 ], [ undef, %b2 ]
%v5 = getelementptr inbounds i16, ptr %v4, i32 1 %v5 = getelementptr inbounds i16, ptr %v4, i32 1
▲ Show 20 Lines • Show All 61 Lines • Show Last 20 Lines

llvm/test/CodeGen/Hexagon/swp-epilog-reuse4.ll

; RUN: llc -march=hexagon -enable-pipeliner -hexagon-expand-condsets=0 < %s ; RUN: llc -march=hexagon -enable-pipeliner -hexagon-expand-condsets=0 < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Disable expand-condsets because it will assert on undefined registers.
; Another test that the pipeliner doesn't ICE when reusing a ; Another test that the pipeliner doesn't ICE when reusing a
; PHI in the epilog code. ; PHI in the epilog code.
@g0 = external global [18 x i16], align 8 @g0 = external global [18 x i16], align 8
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare i32 @llvm.hexagon.S2.asl.r.r.sat(i32, i32) #0 declare i32 @llvm.hexagon.S2.asl.r.r.sat(i32, i32) #0
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare i32 @llvm.hexagon.A2.sxth(i32) #0 declare i32 @llvm.hexagon.A2.sxth(i32) #0
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0() #1 { define void @f0(i1 %c0, i1 %c1) #1 {
b0: b0:
%v0 = alloca [166 x i32], align 8 %v0 = alloca [166 x i32], align 8
br label %b1 br label %b1
b1: ; preds = %b1, %b0 b1: ; preds = %b1, %b0
%v1 = icmp eq i16 undef, 0 %v1 = icmp eq i16 undef, 0
br i1 %v1, label %b2, label %b1 br i1 %v1, label %b2, label %b1
b2: ; preds = %b1 b2: ; preds = %b1
br i1 undef, label %b3, label %b4 br i1 %c0, label %b3, label %b4
b3: ; preds = %b3, %b2 b3: ; preds = %b3, %b2
%v2 = add i32 0, 2 %v2 = add i32 0, 2
br i1 undef, label %b3, label %b4 br i1 %c1, label %b3, label %b4
b4: ; preds = %b3, %b2 b4: ; preds = %b3, %b2
%v3 = phi ptr [ undef, %b2 ], [ undef, %b3 ] %v3 = phi ptr [ undef, %b2 ], [ undef, %b3 ]
%v4 = phi i32 [ 0, %b2 ], [ %v2, %b3 ] %v4 = phi i32 [ 0, %b2 ], [ %v2, %b3 ]
%v5 = getelementptr [18 x i16], ptr @g0, i32 0, i32 undef %v5 = getelementptr [18 x i16], ptr @g0, i32 0, i32 undef
br label %b5 br label %b5
b5: ; preds = %b5, %b4 b5: ; preds = %b5, %b4
▲ Show 20 Lines • Show All 70 Lines • Show Last 20 Lines

llvm/test/CodeGen/Hexagon/swp-exit-fixup.ll

; RUN: llc -march=hexagon -enable-pipeliner < %s ; RUN: llc -march=hexagon -enable-pipeliner < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Make sure we fix up the Phis when we connect the last ; Make sure we fix up the Phis when we connect the last
; epilog block to the CFG. ; epilog block to the CFG.
define void @f0(ptr nocapture %a0) #0 { define void @f0(ptr nocapture %a0, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7) #0 {
b0: b0:
br i1 undef, label %b1, label %b2 br i1 %c0, label %b1, label %b2
b1: ; preds = %b0 b1: ; preds = %b0
br label %b3 br label %b3
b2: ; preds = %b0 b2: ; preds = %b0
unreachable unreachable
b3: ; preds = %b3, %b1 b3: ; preds = %b3, %b1
br i1 undef, label %b4, label %b3 br i1 %c1, label %b4, label %b3
b4: ; preds = %b3 b4: ; preds = %b3
br i1 undef, label %b6, label %b5 br i1 %c2, label %b6, label %b5
b5: ; preds = %b4 b5: ; preds = %b4
store i16 4096, ptr %a0, align 2 store i16 4096, ptr %a0, align 2
br label %b11 br label %b11
b6: ; preds = %b4 b6: ; preds = %b4
br i1 undef, label %b7, label %b8 br i1 %c3, label %b7, label %b8
b7: ; preds = %b7, %b6 b7: ; preds = %b7, %b6
br label %b7 br label %b7
b8: ; preds = %b8, %b6 b8: ; preds = %b8, %b6
br i1 undef, label %b9, label %b8 br i1 %c4, label %b9, label %b8
b9: ; preds = %b8 b9: ; preds = %b8
%v0 = icmp sgt i32 undef, 1 %v0 = icmp sgt i32 undef, 1
br i1 %v0, label %b10, label %b11 br i1 %v0, label %b10, label %b11
b10: ; preds = %b10, %b9 b10: ; preds = %b10, %b9
%v1 = phi i32 [ %v8, %b10 ], [ 1, %b9 ] %v1 = phi i32 [ %v8, %b10 ], [ 1, %b9 ]
%v2 = getelementptr inbounds [11 x i32], ptr undef, i32 0, i32 %v1 %v2 = getelementptr inbounds [11 x i32], ptr undef, i32 0, i32 %v1
%v3 = load i32, ptr undef, align 4 %v3 = load i32, ptr undef, align 4
%v4 = add nsw i32 %v3, 0 %v4 = add nsw i32 %v3, 0
%v5 = add nsw i32 %v4, 2048 %v5 = add nsw i32 %v4, 2048
%v6 = lshr i32 %v5, 12 %v6 = lshr i32 %v5, 12
%v7 = trunc i32 %v6 to i16 %v7 = trunc i32 %v6 to i16
store i16 %v7, ptr undef, align 2 store i16 %v7, ptr undef, align 2
%v8 = add nsw i32 %v1, 1 %v8 = add nsw i32 %v1, 1
%v9 = icmp eq i32 %v8, undef %v9 = icmp eq i32 %v8, undef
br i1 %v9, label %b11, label %b10 br i1 %v9, label %b11, label %b10
b11: ; preds = %b10, %b9, %b5 b11: ; preds = %b10, %b9, %b5
%v10 = phi i1 [ false, %b9 ], [ false, %b5 ], [ %v0, %b10 ] %v10 = phi i1 [ false, %b9 ], [ false, %b5 ], [ %v0, %b10 ]
br i1 undef, label %b16, label %b12 br i1 %c5, label %b16, label %b12
b12: ; preds = %b11 b12: ; preds = %b11
br i1 undef, label %b13, label %b16 br i1 %c6, label %b13, label %b16
b13: ; preds = %b12 b13: ; preds = %b12
br i1 %v10, label %b14, label %b15 br i1 %v10, label %b14, label %b15
b14: ; preds = %b14, %b13 b14: ; preds = %b14, %b13
br i1 undef, label %b15, label %b14 br i1 %c7, label %b15, label %b14
b15: ; preds = %b14, %b13 b15: ; preds = %b14, %b13
br label %b16 br label %b16
b16: ; preds = %b15, %b12, %b11 b16: ; preds = %b15, %b12, %b11
ret void ret void
} }
attributes #0 = { nounwind "target-cpu"="hexagonv55" } attributes #0 = { nounwind "target-cpu"="hexagonv55" }

llvm/test/CodeGen/Hexagon/swp-fix-last-use.ll

; RUN: llc -march=hexagon -enable-pipeliner < %s ; RUN: llc -march=hexagon -enable-pipeliner < %s
; REQUIRES: asserts ; REQUIRES: asserts
; We need to rename uses that occurs after the loop. ; We need to rename uses that occurs after the loop.
define void @f0() #0 { define void @f0(i1 %c0, i1 %c1, i1 %c2) #0 {
b0: b0:
br i1 undef, label %b1, label %b5 br i1 %c0, label %b1, label %b5
b1: ; preds = %b0 b1: ; preds = %b0
br i1 undef, label %b2, label %b4 br i1 %c1, label %b2, label %b4
b2: ; preds = %b2, %b1 b2: ; preds = %b2, %b1
%v0 = phi i32 [ %v1, %b2 ], [ 1, %b1 ] %v0 = phi i32 [ %v1, %b2 ], [ 1, %b1 ]
store i16 0, ptr undef, align 2 store i16 0, ptr undef, align 2
store i16 0, ptr undef, align 2 store i16 0, ptr undef, align 2
%v1 = add nsw i32 %v0, 4 %v1 = add nsw i32 %v0, 4
%v2 = icmp slt i32 %v1, undef %v2 = icmp slt i32 %v1, undef
br i1 %v2, label %b2, label %b3 br i1 %v2, label %b2, label %b3
b3: ; preds = %b2 b3: ; preds = %b2
%v3 = icmp eq i32 %v1, undef %v3 = icmp eq i32 %v1, undef
br i1 %v3, label %b5, label %b4 br i1 %v3, label %b5, label %b4
b4: ; preds = %b4, %b3, %b1 b4: ; preds = %b4, %b3, %b1
br i1 undef, label %b5, label %b4 br i1 %c2, label %b5, label %b4
b5: ; preds = %b4, %b3, %b0 b5: ; preds = %b4, %b3, %b0
ret void ret void
} }
attributes #0 = { nounwind "target-cpu"="hexagonv55" } attributes #0 = { nounwind "target-cpu"="hexagonv55" }

llvm/test/CodeGen/Hexagon/swp-fix-last-use1.ll

; RUN: llc -march=hexagon -enable-pipeliner < %s ; RUN: llc -march=hexagon -enable-pipeliner < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0() #0 { define void @f0(i1 %c0) #0 {
b0: b0:
br i1 undef, label %b1, label %b4 br i1 %c0, label %b1, label %b4
b1: ; preds = %b0 b1: ; preds = %b0
br label %b2 br label %b2
b2: ; preds = %b2, %b1 b2: ; preds = %b2, %b1
%v0 = phi i32 [ undef, %b1 ], [ %v13, %b2 ] %v0 = phi i32 [ undef, %b1 ], [ %v13, %b2 ]
%v1 = phi i32 [ 0, %b1 ], [ %v20, %b2 ] %v1 = phi i32 [ 0, %b1 ], [ %v20, %b2 ]
%v2 = zext i32 %v0 to i64 %v2 = zext i32 %v0 to i64
▲ Show 20 Lines • Show All 53 Lines • Show Last 20 Lines

llvm/test/CodeGen/Hexagon/swp-intreglow8.ll

; RUN: llc -march=hexagon -verify-machineinstrs < %s ; RUN: llc -march=hexagon -verify-machineinstrs < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Test that we constrain the new register operands for instructions ; Test that we constrain the new register operands for instructions
; to be the same as the register class of the original instruction. ; to be the same as the register class of the original instruction.
; In this case, the register class of a valign scalar operand changed ; In this case, the register class of a valign scalar operand changed
; from IntRegsLow8 to IntRegs, which is incorrect. ; from IntRegsLow8 to IntRegs, which is incorrect.
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0() #0 { define void @f0(i1 %c0, i1 %c1) #0 {
b0: b0:
br i1 undef, label %b1, label %b6 br i1 %c0, label %b1, label %b6
b1: ; preds = %b0 b1: ; preds = %b0
br label %b2 br label %b2
b2: ; preds = %b4, %b1 b2: ; preds = %b4, %b1
%v0 = phi <16 x i32> [ undef, %b1 ], [ %v17, %b4 ] %v0 = phi <16 x i32> [ undef, %b1 ], [ %v17, %b4 ]
br label %b3 br label %b3
Show All 16 Linesb3: ; preds = %b3, %b2
%v16 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v14, <16 x i32> %v15) %v16 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v14, <16 x i32> %v15)
%v17 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v3, <16 x i32> %v16) %v17 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v3, <16 x i32> %v16)
%v18 = add nsw i32 %v2, -2 %v18 = add nsw i32 %v2, -2
%v19 = add nsw i32 %v1, 1 %v19 = add nsw i32 %v1, 1
%v20 = icmp eq i32 %v19, 2 %v20 = icmp eq i32 %v19, 2
br i1 %v20, label %b4, label %b3 br i1 %v20, label %b4, label %b3
b4: ; preds = %b3 b4: ; preds = %b3
br i1 undef, label %b5, label %b2 br i1 %c1, label %b5, label %b2
b5: ; preds = %b4 b5: ; preds = %b4
unreachable unreachable
b6: ; preds = %b0 b6: ; preds = %b0
ret void ret void
} }
Show All 38 Lines

llvm/test/CodeGen/Hexagon/swp-kernel-last-use.ll

; RUN: llc -march=hexagon -enable-pipeliner < %s ; RUN: llc -march=hexagon -enable-pipeliner < %s
; REQUIRES: asserts ; REQUIRES: asserts
; This test caused an assert because there was a use of an instruction ; This test caused an assert because there was a use of an instruction
; that was scheduled at stage 0, but no phi were added in the epilog. ; that was scheduled at stage 0, but no phi were added in the epilog.
%s.0 = type <{ ptr, ptr, i16, i8, i8, i8 }> %s.0 = type <{ ptr, ptr, i16, i8, i8, i8 }>
%s.1 = type { [4 x i16], [4 x i16], [4 x i16], [4 x i16], i32, i32, i32, i8, [10 x i32], [10 x [3 x i32]], [4 x i64], i8 } %s.1 = type { [4 x i16], [4 x i16], [4 x i16], [4 x i16], i32, i32, i32, i8, [10 x i32], [10 x [3 x i32]], [4 x i64], i8 }
%s.2 = type { [3 x i16], [4 x i8], i32, [3 x %s.3], [3 x %s.3], [3 x %s.3], [3 x %s.3], [3 x %s.3], [3 x %s.3], [6 x %s.3], [6 x %s.3], [6 x %s.3], i8, [3 x [3 x i16]], [3 x [3 x i16]], [3 x i16], [3 x i16], [6 x i16], [2 x i32], [10 x i32], [2 x i32], [2 x i32], [2 x [3 x i32]], [2 x i32], [2 x [3 x i64]], [2 x [3 x [3 x i32]]], [2 x [3 x i32]] } %s.2 = type { [3 x i16], [4 x i8], i32, [3 x %s.3], [3 x %s.3], [3 x %s.3], [3 x %s.3], [3 x %s.3], [3 x %s.3], [6 x %s.3], [6 x %s.3], [6 x %s.3], i8, [3 x [3 x i16]], [3 x [3 x i16]], [3 x i16], [3 x i16], [6 x i16], [2 x i32], [10 x i32], [2 x i32], [2 x i32], [2 x [3 x i32]], [2 x i32], [2 x [3 x i64]], [2 x [3 x [3 x i32]]], [2 x [3 x i32]] }
%s.3 = type { i8, i8, i8, i8 } %s.3 = type { i8, i8, i8, i8 }
@g0 = external constant %s.0, align 1 @g0 = external constant %s.0, align 1
define void @f0(i8 zeroext %a0, i32 %a1, i32 %a2, i8 zeroext %a3, ptr nocapture %a4, ptr %a5, i8 zeroext %a6) #0 { define void @f0(i8 zeroext %a0, i32 %a1, i32 %a2, i8 zeroext %a3, ptr nocapture %a4, ptr %a5, i8 zeroext %a6, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4) #0 {
b0: b0:
br i1 undef, label %b1, label %b7 br i1 %c0, label %b1, label %b7
b1: ; preds = %b0 b1: ; preds = %b0
br i1 undef, label %b2, label %b3 br i1 %c1, label %b2, label %b3
b2: ; preds = %b1 b2: ; preds = %b1
unreachable unreachable
b3: ; preds = %b1 b3: ; preds = %b1
%v0 = select i1 undef, i32 2, i32 4 %v0 = select i1 undef, i32 2, i32 4
%v1 = load i8, ptr undef, align 1 %v1 = load i8, ptr undef, align 1
%v2 = zext i8 %v1 to i32 %v2 = zext i8 %v1 to i32
%v3 = icmp uge i32 %v2, %v0 %v3 = icmp uge i32 %v2, %v0
br label %b4 br label %b4
b4: ; preds = %b4, %b3 b4: ; preds = %b4, %b3
br i1 undef, label %b4, label %b8 br i1 %c2, label %b4, label %b8
b5: ; preds = %b10 b5: ; preds = %b10
unreachable unreachable
b6: ; preds = %b10 b6: ; preds = %b10
call void @f1(ptr @g0, i32 undef, i32 %v21, i32 undef, i32 undef) call void @f1(ptr @g0, i32 undef, i32 %v21, i32 undef, i32 undef)
unreachable unreachable
Show All 17 Linesb9: ; preds = %b9, %b8
%v14 = phi i32 [ %v21, %b9 ], [ %v11, %b8 ] %v14 = phi i32 [ %v21, %b9 ], [ %v11, %b8 ]
%v15 = icmp ne i32 undef, 1 %v15 = icmp ne i32 undef, 1
%v16 = xor i1 %v15, %v3 %v16 = xor i1 %v15, %v3
%v17 = zext i1 %v16 to i32 %v17 = zext i1 %v16 to i32
%v18 = shl nuw nsw i32 %v17, 1 %v18 = shl nuw nsw i32 %v17, 1
%v19 = shl i32 %v14, 2 %v19 = shl i32 %v14, 2
%v20 = or i32 0, %v19 %v20 = or i32 0, %v19
%v21 = or i32 %v20, %v18 %v21 = or i32 %v20, %v18
br i1 undef, label %b9, label %b10 br i1 %c3, label %b9, label %b10
b10: ; preds = %b9 b10: ; preds = %b9
br i1 undef, label %b6, label %b5 br i1 %c4, label %b6, label %b5
} }
declare void @f1(ptr, i32, i32, i32, i32) declare void @f1(ptr, i32, i32, i32, i32)
attributes #0 = { nounwind "target-cpu"="hexagonv55" } attributes #0 = { nounwind "target-cpu"="hexagonv55" }

llvm/test/CodeGen/Hexagon/swp-large-rec.ll

; RUN: llc -march=hexagon -enable-pipeliner -stats \ ; RUN: llc -march=hexagon -enable-pipeliner -stats \
; RUN: -pipeliner-prune-loop-carried=false -fp-contract=fast \ ; RUN: -pipeliner-prune-loop-carried=false -fp-contract=fast \
; RUN: -o /dev/null < %s 2>&1 -pipeliner-experimental-cg=true | FileCheck %s --check-prefix=STATS ; RUN: -o /dev/null < %s 2>&1 -pipeliner-experimental-cg=true | FileCheck %s --check-prefix=STATS
; REQUIRES: asserts ; REQUIRES: asserts
; That that we do not pipeline this loop. The recurrence is too large. If ; That that we do not pipeline this loop. The recurrence is too large. If
; we pipeline this example, that means we're not checking the complete ; we pipeline this example, that means we're not checking the complete
; chain of dependences. ; chain of dependences.
; STATS-NOT: 1 pipeliner - Number of loops software pipelined ; STATS-NOT: 1 pipeliner - Number of loops software pipelined
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0(i32 %a0, i32 %a1, double %a2, double %a3, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11) #0 { define void @f0(i32 %a0, i32 %a1, double %a2, double %a3, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, i1 %c0, i1 %c1) #0 {
b0: b0:
br i1 undef, label %b1, label %b4 br i1 %c0, label %b1, label %b4
b1: ; preds = %b3, %b0 b1: ; preds = %b3, %b0
br label %b2 br label %b2
b2: ; preds = %b2, %b1 b2: ; preds = %b2, %b1
%v0 = phi ptr [ %v22, %b2 ], [ %a5, %b1 ] %v0 = phi ptr [ %v22, %b2 ], [ %a5, %b1 ]
%v1 = phi ptr [ %v23, %b2 ], [ %a6, %b1 ] %v1 = phi ptr [ %v23, %b2 ], [ %a6, %b1 ]
%v2 = phi ptr [ %v24, %b2 ], [ %a7, %b1 ] %v2 = phi ptr [ %v24, %b2 ], [ %a7, %b1 ]
Show All 21 Linesb2: ; preds = %b2, %b1
%v21 = icmp eq i32 %v20, undef %v21 = icmp eq i32 %v20, undef
%v22 = getelementptr i8, ptr %v0, i32 1 %v22 = getelementptr i8, ptr %v0, i32 1
%v23 = getelementptr i8, ptr %v1, i32 1 %v23 = getelementptr i8, ptr %v1, i32 1
%v24 = getelementptr i8, ptr %v2, i32 1 %v24 = getelementptr i8, ptr %v2, i32 1
br i1 %v21, label %b3, label %b2 br i1 %v21, label %b3, label %b2
b3: ; preds = %b2 b3: ; preds = %b2
tail call void @f1(i32 %a1, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, i8 signext 1) #2 tail call void @f1(i32 %a1, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, i8 signext 1) #2
br i1 undef, label %b4, label %b1 br i1 %c1, label %b4, label %b1
b4: ; preds = %b3, %b0 b4: ; preds = %b3, %b0
ret void ret void
} }
declare void @f1(i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i8 signext) #1 declare void @f1(i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i8 signext) #1
attributes #0 = { nounwind "target-cpu"="hexagonv55" } attributes #0 = { nounwind "target-cpu"="hexagonv55" }
attributes #1 = { "target-cpu"="hexagonv55" } attributes #1 = { "target-cpu"="hexagonv55" }
attributes #2 = { nounwind } attributes #2 = { nounwind }
!0 = !{!1, !1, i64 0} !0 = !{!1, !1, i64 0}
!1 = !{!"omnipotent char", !2, i64 0} !1 = !{!"omnipotent char", !2, i64 0}
!2 = !{!"Simple C/C++ TBAA"} !2 = !{!"Simple C/C++ TBAA"}

llvm/test/CodeGen/Hexagon/swp-loop-carried.ll

; RUN: llc -march=hexagon -fp-contract=fast -enable-pipeliner < %s ; RUN: llc -march=hexagon -fp-contract=fast -enable-pipeliner < %s
; REQUIRES: asserts ; REQUIRES: asserts
; A Phi that depends on another Phi is loop carried. ; A Phi that depends on another Phi is loop carried.
define void @f0() #0 { define void @f0(i1 %c0, i1 %c1, i1 %c2) #0 {
b0: b0:
br label %b1 br label %b1
b1: ; preds = %b1, %b0 b1: ; preds = %b1, %b0
br i1 undef, label %b1, label %b2 br i1 %c0, label %b1, label %b2
b2: ; preds = %b1 b2: ; preds = %b1
br i1 undef, label %b3, label %b8 br i1 %c1, label %b3, label %b8
b3: ; preds = %b2 b3: ; preds = %b2
br i1 undef, label %b4, label %b5 br i1 %c2, label %b4, label %b5
b4: ; preds = %b4, %b3 b4: ; preds = %b4, %b3
%v0 = phi i32 [ %v5, %b4 ], [ 2, %b3 ] %v0 = phi i32 [ %v5, %b4 ], [ 2, %b3 ]
%v1 = phi float [ %v4, %b4 ], [ undef, %b3 ] %v1 = phi float [ %v4, %b4 ], [ undef, %b3 ]
%v2 = phi float [ %v1, %b4 ], [ undef, %b3 ] %v2 = phi float [ %v1, %b4 ], [ undef, %b3 ]
%v3 = fsub float 0.000000e+00, %v2 %v3 = fsub float 0.000000e+00, %v2
%v4 = fadd float %v3, undef %v4 = fadd float %v3, undef
%v5 = add nsw i32 %v0, 1 %v5 = add nsw i32 %v0, 1
Show All 21 Lines

llvm/test/CodeGen/Hexagon/swp-loopval.ll

; RUN: llc -march=hexagon -enable-pipeliner < %s ; RUN: llc -march=hexagon -enable-pipeliner < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Check that we correctly rename instructions that use a Phi's loop value, ; Check that we correctly rename instructions that use a Phi's loop value,
; and the Phi and loop value are defined after the instruction.
%s.0 = type { [4 x i8], i16, i16, i32, [8 x i8], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x %s.1], [4 x i8], i32, i32, [4 x i8], [14 x %s.2] } %s.0 = type { [4 x i8], i16, i16, i32, [8 x i8], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x %s.1], [4 x i8], i32, i32, [4 x i8], [14 x %s.2] }
%s.1 = type { i32, i32 } %s.1 = type { i32, i32 }
%s.2 = type { [4 x i8] } %s.2 = type { [4 x i8] }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0(ptr nocapture %a0) #0 { define void @f0(ptr nocapture %a0, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4) #0 {
b0: b0:
br i1 undef, label %b1, label %b2 br i1 %c0, label %b1, label %b2
b1: ; preds = %b0 b1: ; preds = %b0
unreachable unreachable
b2: ; preds = %b0 b2: ; preds = %b0
br label %b8 br label %b8
b3: ; preds = %b9 b3: ; preds = %b9
unreachable unreachable
b4: ; preds = %b9 b4: ; preds = %b9
br i1 undef, label %b7, label %b5 br i1 %c1, label %b7, label %b5
b5: ; preds = %b4 b5: ; preds = %b4
br i1 undef, label %b6, label %b7 br i1 %c2, label %b6, label %b7
b6: ; preds = %b6, %b5 b6: ; preds = %b6, %b5
%v0 = phi i32 [ %v10, %b6 ], [ 0, %b5 ] %v0 = phi i32 [ %v10, %b6 ], [ 0, %b5 ]
%v1 = load i32, ptr undef, align 4 %v1 = load i32, ptr undef, align 4
%v2 = getelementptr inbounds %s.0, ptr %a0, i32 0, i32 29, i32 %v0 %v2 = getelementptr inbounds %s.0, ptr %a0, i32 0, i32 29, i32 %v0
%v4 = load i32, ptr %v2, align 4 %v4 = load i32, ptr %v2, align 4
%v5 = and i32 %v1, 65535 %v5 = and i32 %v1, 65535
%v6 = and i32 %v4, -65536 %v6 = and i32 %v4, -65536
%v7 = or i32 %v6, %v5 %v7 = or i32 %v6, %v5
%v8 = and i32 %v7, -2031617 %v8 = and i32 %v7, -2031617
%v9 = or i32 %v8, 0 %v9 = or i32 %v8, 0
store i32 %v9, ptr %v2, align 4 store i32 %v9, ptr %v2, align 4
%v10 = add nsw i32 %v0, 1 %v10 = add nsw i32 %v0, 1
%v11 = icmp eq i32 %v10, undef %v11 = icmp eq i32 %v10, undef
br i1 %v11, label %b7, label %b6 br i1 %v11, label %b7, label %b6
b7: ; preds = %b6, %b5, %b4 b7: ; preds = %b6, %b5, %b4
ret void ret void
b8: ; preds = %b8, %b2 b8: ; preds = %b8, %b2
br i1 undef, label %b9, label %b8 br i1 %c3, label %b9, label %b8
b9: ; preds = %b8 b9: ; preds = %b8
br i1 undef, label %b3, label %b4 br i1 %c4, label %b3, label %b4
} }
attributes #0 = { nounwind "target-cpu"="hexagonv55" } attributes #0 = { nounwind "target-cpu"="hexagonv55" }

llvm/test/CodeGen/Hexagon/swp-maxstart.ll

Show All 9 Lines
; CHECK-NOT: r{{[0-9]+}} = memw([[REG0]]+#12) ; CHECK-NOT: r{{[0-9]+}} = memw([[REG0]]+#12)
; CHECK: memw([[REG0]]+#12) = r{{[0-9]+}} ; CHECK: memw([[REG0]]+#12) = r{{[0-9]+}}
%s.0 = type { i64, i32, i32, i32, ptr } %s.0 = type { i64, i32, i32, i32, ptr }
@g0 = external global %s.0, align 8 @g0 = external global %s.0, align 8
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0() #0 { define void @f0(i1 %c0) #0 {
b0: b0:
%v0 = load i32, ptr getelementptr inbounds (%s.0, ptr @g0, i32 0, i32 1), align 8 %v0 = load i32, ptr getelementptr inbounds (%s.0, ptr @g0, i32 0, i32 1), align 8
%v1 = ashr i32 %v0, 3 %v1 = ashr i32 %v0, 3
br i1 undef, label %b1, label %b2 br i1 %c0, label %b1, label %b2
b1: ; preds = %b1, %b0 b1: ; preds = %b1, %b0
%v2 = phi i32 [ %v5, %b1 ], [ 0, %b0 ] %v2 = phi i32 [ %v5, %b1 ], [ 0, %b0 ]
%v3 = load ptr, ptr getelementptr inbounds (%s.0, ptr @g0, i32 0, i32 4), align 4 %v3 = load ptr, ptr getelementptr inbounds (%s.0, ptr @g0, i32 0, i32 4), align 4
%v4 = getelementptr inbounds i8, ptr %v3, i32 -1 %v4 = getelementptr inbounds i8, ptr %v3, i32 -1
store ptr %v4, ptr getelementptr inbounds (%s.0, ptr @g0, i32 0, i32 4), align 4 store ptr %v4, ptr getelementptr inbounds (%s.0, ptr @g0, i32 0, i32 4), align 4
store i8 0, ptr %v4, align 1 store i8 0, ptr %v4, align 1
%v5 = add nsw i32 %v2, 1 %v5 = add nsw i32 %v2, 1
%v6 = icmp eq i32 %v5, %v1 %v6 = icmp eq i32 %v5, %v1
br i1 %v6, label %b2, label %b1 br i1 %v6, label %b2, label %b1
b2: ; preds = %b1, %b0 b2: ; preds = %b1, %b0
ret void ret void
} }
attributes #0 = { nounwind "target-cpu"="hexagonv60" } attributes #0 = { nounwind "target-cpu"="hexagonv60" }

llvm/test/CodeGen/Hexagon/swp-more-phi.ll

; RUN: llc -march=hexagon --enable-pipeliner -hexagon-expand-condsets=0 < %s ; RUN: llc -march=hexagon --enable-pipeliner -hexagon-expand-condsets=0 < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Disable expand-condsets because it will assert on undefined registers.
define void @f0() #0 { define void @f0(i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6) #0 {
b0: b0:
br i1 undef, label %b1, label %b2 br i1 %c0, label %b1, label %b2
b1: ; preds = %b0 b1: ; preds = %b0
unreachable unreachable
b2: ; preds = %b0 b2: ; preds = %b0
br i1 undef, label %b3, label %b4 br i1 %c1, label %b3, label %b4
b3: ; preds = %b3, %b2 b3: ; preds = %b3, %b2
br i1 undef, label %b4, label %b3 br i1 %c2, label %b4, label %b3
b4: ; preds = %b3, %b2 b4: ; preds = %b3, %b2
%v0 = ashr i32 undef, 25 %v0 = ashr i32 undef, 25
%v1 = mul nsw i32 %v0, 2 %v1 = mul nsw i32 %v0, 2
%v2 = load i8, ptr undef, align 1 %v2 = load i8, ptr undef, align 1
br i1 undef, label %b5, label %b10 br i1 %c3, label %b5, label %b10
b5: ; preds = %b4 b5: ; preds = %b4
br i1 undef, label %b6, label %b9 br i1 %c4, label %b6, label %b9
b6: ; preds = %b5 b6: ; preds = %b5
br label %b7 br label %b7
b7: ; preds = %b7, %b6 b7: ; preds = %b7, %b6
br i1 undef, label %b7, label %b8 br i1 %c5, label %b7, label %b8
b8: ; preds = %b7 b8: ; preds = %b7
br i1 undef, label %b10, label %b9 br i1 %c6, label %b10, label %b9
b9: ; preds = %b9, %b8, %b5 b9: ; preds = %b9, %b8, %b5
%v3 = phi i8 [ %v7, %b9 ], [ undef, %b8 ], [ %v2, %b5 ] %v3 = phi i8 [ %v7, %b9 ], [ undef, %b8 ], [ %v2, %b5 ]
%v4 = phi i32 [ %v8, %b9 ], [ undef, %b8 ], [ 1, %b5 ] %v4 = phi i32 [ %v8, %b9 ], [ undef, %b8 ], [ 1, %b5 ]
%v5 = add i32 %v4, undef %v5 = add i32 %v4, undef
%v6 = load i8, ptr undef, align 1 %v6 = load i8, ptr undef, align 1
%v7 = select i1 undef, i8 %v6, i8 %v3 %v7 = select i1 undef, i8 %v6, i8 %v3
%v8 = add nsw i32 %v4, 1 %v8 = add nsw i32 %v4, 1
Show All 18 Lines

llvm/test/CodeGen/Hexagon/swp-multi-phi-refs.ll

; RUN: llc -march=hexagon -O3 < %s ; RUN: llc -march=hexagon -O3 < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Test that we generate the correct names for Phis when there is ; Test that we generate the correct names for Phis when there is
; a Phi that references a Phi that references another Phi. For example, ; a Phi that references a Phi that references another Phi. For example,
; v6 = phi(v1, v9) ; v6 = phi(v1, v9)
; v7 = phi(v0, v6) ; v7 = phi(v0, v6)
; v8 = phi(v2, v7) ; v8 = phi(v2, v7)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0(ptr noalias nocapture readonly %a0, i32 %a1, i32 %a2, ptr noalias nocapture %a3, i32 %a4) #0 { define void @f0(ptr noalias nocapture readonly %a0, i32 %a1, i32 %a2, ptr noalias nocapture %a3, i32 %a4, i1 %c0, i1 %c1) #0 {
b0: b0:
%v0 = add i32 %a1, -1 %v0 = add i32 %a1, -1
%v2 = getelementptr inbounds i8, ptr %a0, i32 undef %v2 = getelementptr inbounds i8, ptr %a0, i32 undef
br i1 undef, label %b1, label %b4 br i1 %c0, label %b1, label %b4
b1: ; preds = %b1, %b0 b1: ; preds = %b1, %b0
br i1 undef, label %b1, label %b2 br i1 %c1, label %b1, label %b2
b2: ; preds = %b1 b2: ; preds = %b1
%v4 = getelementptr inbounds i8, ptr %a0, i32 undef %v4 = getelementptr inbounds i8, ptr %a0, i32 undef
br label %b3 br label %b3
b3: ; preds = %b3, %b2 b3: ; preds = %b3, %b2
%v5 = phi ptr [ %v10, %b3 ], [ %a3, %b2 ] %v5 = phi ptr [ %v10, %b3 ], [ %a3, %b2 ]
%v6 = phi ptr [ %v25, %b3 ], [ %v4, %b2 ] %v6 = phi ptr [ %v25, %b3 ], [ %v4, %b2 ]
Show All 33 Lines

llvm/test/CodeGen/Hexagon/swp-order-carried.ll

; RUN: llc -march=hexagon < %s ; RUN: llc -march=hexagon < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Test that we order instruction within a packet correctly. In this case, ; Test that we order instruction within a packet correctly. In this case,
; we added a definition of a value after the use in a packet, which ; we added a definition of a value after the use in a packet, which
; caused an assert. ; caused an assert.
define void @f0(i32 %a0) { define void @f0(i32 %a0, i1 %c0) {
b0: b0:
%v0 = ashr i32 %a0, 1 %v0 = ashr i32 %a0, 1
br i1 undef, label %b3, label %b1 br i1 %c0, label %b3, label %b1
b1: ; preds = %b1, %b0 b1: ; preds = %b1, %b0
%v1 = phi i32 [ %v23, %b1 ], [ undef, %b0 ] %v1 = phi i32 [ %v23, %b1 ], [ undef, %b0 ]
%v2 = phi i64 [ %v14, %b1 ], [ 0, %b0 ] %v2 = phi i64 [ %v14, %b1 ], [ 0, %b0 ]
%v3 = phi i64 [ %v11, %b1 ], [ 0, %b0 ] %v3 = phi i64 [ %v11, %b1 ], [ 0, %b0 ]
%v4 = phi i32 [ %v25, %b1 ], [ 0, %b0 ] %v4 = phi i32 [ %v25, %b1 ], [ 0, %b0 ]
%v5 = phi i32 [ %v6, %b1 ], [ undef, %b0 ] %v5 = phi i32 [ %v6, %b1 ], [ undef, %b0 ]
%v6 = phi i32 [ %v20, %b1 ], [ undef, %b0 ] %v6 = phi i32 [ %v20, %b1 ], [ undef, %b0 ]
▲ Show 20 Lines • Show All 64 Lines • Show Last 20 Lines

llvm/test/CodeGen/Hexagon/swp-order-deps1.ll

; RUN: llc -march=hexagon -enable-pipeliner < %s ; RUN: llc -march=hexagon -enable-pipeliner < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Check that the dependences are order correctly, and the list can be ; Check that the dependences are order correctly, and the list can be
; updated when the instruction to insert has a def and use conflict. ; updated when the instruction to insert has a def and use conflict.
; Function Attrs: nounwind ; Function Attrs: nounwind
define fastcc void @f0() #0 { define fastcc void @f0(i1 %c0, i1 %c1) #0 {
b0: b0:
br i1 undef, label %b7, label %b1 br i1 %c0, label %b7, label %b1
b1: ; preds = %b0 b1: ; preds = %b0
br i1 undef, label %b2, label %b4 br i1 %c1, label %b2, label %b4
b2: ; preds = %b1 b2: ; preds = %b1
%v0 = load i16, ptr undef, align 2 %v0 = load i16, ptr undef, align 2
br label %b5 br label %b5
b3: ; preds = %b5 b3: ; preds = %b5
br label %b4 br label %b4
Show All 27 Lines

llvm/test/CodeGen/Hexagon/swp-order-deps3.ll

; RUN: llc -march=hexagon -O2 -simplifycfg-require-and-preserve-domtree=1 < %s ; RUN: llc -march=hexagon -O2 -simplifycfg-require-and-preserve-domtree=1 < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Function Attrs: noinline nounwind ssp ; Function Attrs: noinline nounwind ssp
define fastcc void @f0() #0 { define fastcc void @f0(i1 %c0) #0 {
b0: b0:
%v0 = add i32 0, 39 %v0 = add i32 0, 39
%v1 = and i32 %v0, -8 %v1 = and i32 %v0, -8
br i1 undef, label %b1, label %b2 br i1 %c0, label %b1, label %b2
b1: ; preds = %b1, %b0 b1: ; preds = %b1, %b0
%v2 = phi i32 [ %v10, %b1 ], [ undef, %b0 ] %v2 = phi i32 [ %v10, %b1 ], [ undef, %b0 ]
%v3 = phi ptr [ %v7, %b1 ], [ undef, %b0 ] %v3 = phi ptr [ %v7, %b1 ], [ undef, %b0 ]
%v4 = ptrtoint ptr %v3 to i32 %v4 = ptrtoint ptr %v3 to i32
%v5 = add i32 %v4, %v1 %v5 = add i32 %v4, %v1
store i32 %v5, ptr %v3, align 4 store i32 %v5, ptr %v3, align 4
%v7 = getelementptr inbounds i8, ptr %v3, i32 %v1 %v7 = getelementptr inbounds i8, ptr %v3, i32 %v1
Show All 10 Lines

llvm/test/CodeGen/Hexagon/swp-order-prec.ll

; RUN: llc -march=hexagon < %s ; RUN: llc -march=hexagon < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Test that the pipeliner doesn't assert in orderDependence because ; Test that the pipeliner doesn't assert in orderDependence because
; the check for OrderAfterDef precedeence is in the wrong spot. ; the check for OrderAfterDef precedeence is in the wrong spot.
%s.0 = type <{ i8, [20 x %s.1] }> %s.0 = type <{ i8, [20 x %s.1] }>
%s.1 = type { i16, i16 } %s.1 = type { i16, i16 }
; Function Attrs: nounwind optsize ssp ; Function Attrs: nounwind optsize ssp
define void @f0() #0 { define void @f0(i1 %c0) #0 {
b0: b0:
br i1 undef, label %b1, label %b2 br i1 %c0, label %b1, label %b2
b1: ; preds = %b1, %b0 b1: ; preds = %b1, %b0
%v0 = phi i32 [ %v3, %b1 ], [ 0, %b0 ] %v0 = phi i32 [ %v3, %b1 ], [ 0, %b0 ]
%v1 = getelementptr inbounds %s.0, ptr undef, i32 0, i32 1, i32 %v0, i32 0 %v1 = getelementptr inbounds %s.0, ptr undef, i32 0, i32 1, i32 %v0, i32 0
store i16 0, ptr %v1, align 1 store i16 0, ptr %v1, align 1
%v2 = getelementptr inbounds %s.0, ptr undef, i32 0, i32 1, i32 %v0, i32 1 %v2 = getelementptr inbounds %s.0, ptr undef, i32 0, i32 1, i32 %v0, i32 1
store i16 -1, ptr %v2, align 1 store i16 -1, ptr %v2, align 1
%v3 = add nsw i32 %v0, 1 %v3 = add nsw i32 %v0, 1
%v4 = icmp eq i32 %v3, 20 %v4 = icmp eq i32 %v3, 20
br i1 %v4, label %b2, label %b1 br i1 %v4, label %b2, label %b1
b2: ; preds = %b1, %b0 b2: ; preds = %b1, %b0
ret void ret void
} }
attributes #0 = { nounwind optsize ssp "target-cpu"="hexagonv55" } attributes #0 = { nounwind optsize ssp "target-cpu"="hexagonv55" }

llvm/test/CodeGen/Hexagon/swp-phi-def-use.ll

Show All 11 Lines
%s.5 = type { [0 x i32], [0 x ptr] } %s.5 = type { [0 x i32], [0 x ptr] }
@g0 = external global i32, align 4 @g0 = external global i32, align 4
@g1 = external global %s.0, align 4 @g1 = external global %s.0, align 4
@g2 = external global i32, align 4 @g2 = external global i32, align 4
@g3 = external global i32, align 4 @g3 = external global i32, align 4
@g4 = external global ptr, align 4 @g4 = external global ptr, align 4
define void @f0(ptr nocapture readonly %a0) #0 { define void @f0(ptr nocapture readonly %a0, i1 %c0) #0 {
b0: b0:
%v0 = alloca [0 x i32], align 4 %v0 = alloca [0 x i32], align 4
%v1 = load i32, ptr @g0, align 4 %v1 = load i32, ptr @g0, align 4
%v2 = load i32, ptr undef, align 4 %v2 = load i32, ptr undef, align 4
%v3 = load ptr, ptr getelementptr inbounds (%s.0, ptr @g1, i32 0, i32 1), align 4 %v3 = load ptr, ptr getelementptr inbounds (%s.0, ptr @g1, i32 0, i32 1), align 4
%v4 = load i32, ptr @g2, align 4 %v4 = load i32, ptr @g2, align 4
%v5 = sub i32 0, %v4 %v5 = sub i32 0, %v4
%v6 = getelementptr inbounds i32, ptr %v3, i32 %v5 %v6 = getelementptr inbounds i32, ptr %v3, i32 %v5
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
b6: ; preds = %b4 b6: ; preds = %b4
br i1 %v9, label %b8, label %b7 br i1 %v9, label %b8, label %b7
b7: ; preds = %b6 b7: ; preds = %b6
store i32 0, ptr @g3, align 4 store i32 0, ptr @g3, align 4
br label %b11 br label %b11
b8: ; preds = %b6 b8: ; preds = %b6
br i1 undef, label %b9, label %b11 br i1 %c0, label %b9, label %b11
b9: ; preds = %b8 b9: ; preds = %b8
%v31 = load ptr, ptr @g4, align 4 %v31 = load ptr, ptr @g4, align 4
br label %b10 br label %b10
b10: ; preds = %b10, %b9 b10: ; preds = %b10, %b9
%v32 = phi i32 [ %v22, %b9 ], [ %v39, %b10 ] %v32 = phi i32 [ %v22, %b9 ], [ %v39, %b10 ]
%v33 = phi i32 [ %v29, %b9 ], [ %v38, %b10 ] %v33 = phi i32 [ %v29, %b9 ], [ %v38, %b10 ]
Show All 30 Lines

llvm/test/CodeGen/Hexagon/swp-phi-dep.ll

; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 -enable-pipeliner -pipeliner-max-stages=2 < %s -pipeliner-experimental-cg=true | FileCheck %s ; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 -enable-pipeliner -pipeliner-max-stages=2 < %s -pipeliner-experimental-cg=true | FileCheck %s
; Check that the pipelined code uses the proper address in the ; Check that the pipelined code uses the proper address in the
; prolog and the kernel. The bug occurs when the address computation ; prolog and the kernel. The bug occurs when the address computation
; computes the same value twice. ; computes the same value twice.
; CHECK: = addasl(r{{[0-9]+}},[[REG0:(r[0-9]+)]],#1) ; CHECK: = addasl(r{{[0-9]+}},[[REG0:(r[0-9]+)]],#1)
; CHECK-NOT: = addasl(r{{[0-9]+}},[[REG0]],#1) ; CHECK-NOT: = addasl(r{{[0-9]+}},[[REG0]],#1)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0(i32 %a0, ptr nocapture %a1) #0 { define void @f0(i32 %a0, ptr nocapture %a1, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6) #0 {
b0: b0:
br i1 undef, label %b2, label %b1 br i1 %c0, label %b2, label %b1
b1: ; preds = %b0 b1: ; preds = %b0
unreachable unreachable
b2: ; preds = %b0 b2: ; preds = %b0
br label %b3 br label %b3
b3: ; preds = %b4, %b2 b3: ; preds = %b4, %b2
br i1 undef, label %b4, label %b5 br i1 %c1, label %b4, label %b5
b4: ; preds = %b3 b4: ; preds = %b3
br label %b3 br label %b3
b5: ; preds = %b3 b5: ; preds = %b3
br i1 undef, label %b6, label %b7 br i1 %c2, label %b6, label %b7
b6: ; preds = %b5 b6: ; preds = %b5
unreachable unreachable
b7: ; preds = %b5 b7: ; preds = %b5
br i1 undef, label %b8, label %b12 br i1 %c3, label %b8, label %b12
b8: ; preds = %b7 b8: ; preds = %b7
br i1 undef, label %b9, label %b11 br i1 %c4, label %b9, label %b11
b9: ; preds = %b9, %b8 b9: ; preds = %b9, %b8
br i1 undef, label %b9, label %b10 br i1 %c5, label %b9, label %b10
b10: ; preds = %b9 b10: ; preds = %b9
br i1 undef, label %b12, label %b11 br i1 %c6, label %b12, label %b11
b11: ; preds = %b11, %b10, %b8 b11: ; preds = %b11, %b10, %b8
%v0 = phi i32 [ %v6, %b11 ], [ undef, %b8 ], [ undef, %b10 ] %v0 = phi i32 [ %v6, %b11 ], [ undef, %b8 ], [ undef, %b10 ]
%v1 = phi i32 [ %v0, %b11 ], [ %a0, %b8 ], [ undef, %b10 ] %v1 = phi i32 [ %v0, %b11 ], [ %a0, %b8 ], [ undef, %b10 ]
%v2 = add nsw i32 %v1, -2 %v2 = add nsw i32 %v1, -2
%v3 = getelementptr inbounds i16, ptr %a1, i32 %v2 %v3 = getelementptr inbounds i16, ptr %a1, i32 %v2
%v4 = load i16, ptr %v3, align 2, !tbaa !0 %v4 = load i16, ptr %v3, align 2, !tbaa !0
%v5 = getelementptr inbounds i16, ptr %a1, i32 %v0 %v5 = getelementptr inbounds i16, ptr %a1, i32 %v0
Show All 15 Lines

llvm/test/CodeGen/Hexagon/swp-phi-order.ll

; RUN: llc -march=hexagon -enable-pipeliner < %s ; RUN: llc -march=hexagon -enable-pipeliner < %s
; REQUIRES: asserts ; REQUIRES: asserts
%s.0 = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, [49 x i8], [49 x i8], [25 x i8], [6 x i8], [29 x i8], i8, [6 x i8], [6 x i8] } %s.0 = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, [49 x i8], [49 x i8], [25 x i8], [6 x i8], [29 x i8], i8, [6 x i8], [6 x i8] }
define void @f0(ptr nocapture %a0) { define void @f0(ptr nocapture %a0, i1 %c0) {
b0: b0:
br i1 undef, label %b2, label %b1 br i1 %c0, label %b2, label %b1
b1: ; preds = %b1, %b0 b1: ; preds = %b1, %b0
%v0 = phi i32 [ %v6, %b1 ], [ undef, %b0 ] %v0 = phi i32 [ %v6, %b1 ], [ undef, %b0 ]
%v1 = phi i32 [ %v8, %b1 ], [ 1, %b0 ] %v1 = phi i32 [ %v8, %b1 ], [ 1, %b0 ]
%v2 = and i32 %v0, 255 %v2 = and i32 %v0, 255
%v3 = getelementptr inbounds %s.0, ptr %a0, i32 0, i32 9, i32 %v1 %v3 = getelementptr inbounds %s.0, ptr %a0, i32 0, i32 9, i32 %v1
%v4 = load i8, ptr %v3, align 1 %v4 = load i8, ptr %v3, align 1
%v5 = zext i8 %v4 to i32 %v5 = zext i8 %v4 to i32
Show All 10 Lines

llvm/test/CodeGen/Hexagon/swp-phi-ref.ll

Show All 9 Lines
; CHECK: v[[REG0:[0-9]+]] = v[[REG1:[0-9]+]] ; CHECK: v[[REG0:[0-9]+]] = v[[REG1:[0-9]+]]
; CHECK: loop0 ; CHECK: loop0
; Check for copy REG0 = REG1 (via vcombine): ; Check for copy REG0 = REG1 (via vcombine):
; CHECK: v{{[0-9]+}}:[[REG0]] = vcombine(v{{[0-9]+}},v[[REG1]]) ; CHECK: v{{[0-9]+}}:[[REG0]] = vcombine(v{{[0-9]+}},v[[REG1]])
; CHECK: endloop0 ; CHECK: endloop0
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0() #0 { define void @f0(i1 %c0) #0 {
b0: b0:
br i1 undef, label %b1, label %b2 br i1 %c0, label %b1, label %b2
b1: ; preds = %b1, %b0 b1: ; preds = %b1, %b0
%v0 = phi i32 [ %v7, %b1 ], [ 0, %b0 ] %v0 = phi i32 [ %v7, %b1 ], [ 0, %b0 ]
%v1 = phi <16 x i32> [ %v4, %b1 ], [ undef, %b0 ] %v1 = phi <16 x i32> [ %v4, %b1 ], [ undef, %b0 ]
%v2 = phi <16 x i32> [ %v1, %b1 ], [ undef, %b0 ] %v2 = phi <16 x i32> [ %v1, %b1 ], [ undef, %b0 ]
%v3 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v1, <16 x i32> %v2, i32 62) %v3 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v1, <16 x i32> %v2, i32 62)
%v4 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> undef, <16 x i32> undef) %v4 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> undef, <16 x i32> undef)
%v5 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v4, <16 x i32> %v1, i32 2) %v5 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v4, <16 x i32> %v1, i32 2)
Show All 21 Lines

llvm/test/CodeGen/Hexagon/swp-phi-ref1.ll

; RUN: llc -march=hexagon -mno-pairing -mno-compound < %s ; RUN: llc -march=hexagon -mno-pairing -mno-compound < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Test that the SWP doesn't assert when generating new phis. In this example, a ; Test that the SWP doesn't assert when generating new phis. In this example, a
; phi references another phi and phi as well as the phi loop value are all ; phi references another phi and phi as well as the phi loop value are all
; defined in different stages.
; v3 = stage 2 ; v3 = stage 2
; v2 = phi(vb, v3) stage 1 ; v2 = phi(vb, v3) stage 1
; v1 = phi(va, v2) stage 0 ; v1 = phi(va, v2) stage 0
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0() #0 { define void @f0(i1 %c0, i1 %c1) #0 {
b0: b0:
br label %b1 br label %b1
b1: ; preds = %b1, %b0 b1: ; preds = %b1, %b0
br i1 undef, label %b2, label %b1 br i1 %c0, label %b2, label %b1
b2: ; preds = %b1 b2: ; preds = %b1
br label %b3 br label %b3
b3: ; preds = %b3, %b2 b3: ; preds = %b3, %b2
br i1 undef, label %b3, label %b4 br i1 %c1, label %b3, label %b4
b4: ; preds = %b4, %b3 b4: ; preds = %b4, %b3
%v0 = phi i32 [ %v17, %b4 ], [ undef, %b3 ] %v0 = phi i32 [ %v17, %b4 ], [ undef, %b3 ]
%v1 = phi i64 [ %v13, %b4 ], [ undef, %b3 ] %v1 = phi i64 [ %v13, %b4 ], [ undef, %b3 ]
%v2 = phi i32 [ %v19, %b4 ], [ undef, %b3 ] %v2 = phi i32 [ %v19, %b4 ], [ undef, %b3 ]
%v3 = phi i32 [ %v4, %b4 ], [ undef, %b3 ] %v3 = phi i32 [ %v4, %b4 ], [ undef, %b3 ]
%v4 = phi i32 [ %v14, %b4 ], [ undef, %b3 ] %v4 = phi i32 [ %v14, %b4 ], [ undef, %b3 ]
%v5 = phi i32 [ %v18, %b4 ], [ undef, %b3 ] %v5 = phi i32 [ %v18, %b4 ], [ undef, %b3 ]
▲ Show 20 Lines • Show All 41 Lines • Show Last 20 Lines

llvm/test/CodeGen/Hexagon/swp-phi-start.ll

; RUN: llc -march=hexagon -enable-pipeliner -pipeliner-max-stages=2 -disable-packetizer < %s | FileCheck %s ; RUN: llc -march=hexagon -enable-pipeliner -pipeliner-max-stages=2 -disable-packetizer < %s | FileCheck %s
; Test that the early start and late start values are computed correctly ; Test that the early start and late start values are computed correctly
; when a Phi depends on another Phi. In this case, they should occur in ; when a Phi depends on another Phi. In this case, they should occur in
; the same stage. ; the same stage.
; CHECK-DAG: [[REG3:(r[0-9]+)]] = add([[REG1:(r[0-9]+)]],#-1) ; CHECK-DAG: [[REG3:(r[0-9]+)]] = add([[REG1:(r[0-9]+)]],#-1)
; CHECK-DAG: [[REG2:(r[0-9]+)]] = add([[REG1]],#-1) ; CHECK-DAG: [[REG2:(r[0-9]+)]] = add([[REG1]],#-1)
; CHECK-DAG: loop0(.LBB0_[[LOOP:.]],[[REG3]]) ; CHECK-DAG: loop0(.LBB0_[[LOOP:.]],[[REG3]])
; CHECK-NOT: = [[REG2]] ; CHECK-NOT: = [[REG2]]
; CHECK: .LBB0_[[LOOP]]: ; CHECK: .LBB0_[[LOOP]]:
; CHECK: }{{[ \t]*}}:endloop ; CHECK: }{{[ \t]*}}:endloop
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0(i32 %a0, ptr nocapture %a1) #0 { define void @f0(i32 %a0, ptr nocapture %a1, i1 %c0, i1 %c1) #0 {
b0: b0:
br i1 undef, label %b1, label %b2 br i1 %c0, label %b1, label %b2
b1: ; preds = %b0 b1: ; preds = %b0
%v0 = add nsw i32 undef, -8 %v0 = add nsw i32 undef, -8
br i1 undef, label %b3, label %b2 br i1 %c1, label %b3, label %b2
b2: ; preds = %b2, %b1, %b0 b2: ; preds = %b2, %b1, %b0
%v1 = phi i32 [ %v7, %b2 ], [ undef, %b0 ], [ %v0, %b1 ] %v1 = phi i32 [ %v7, %b2 ], [ undef, %b0 ], [ %v0, %b1 ]
%v2 = phi i32 [ %v1, %b2 ], [ %a0, %b0 ], [ undef, %b1 ] %v2 = phi i32 [ %v1, %b2 ], [ %a0, %b0 ], [ undef, %b1 ]
%v3 = add nsw i32 %v2, -2 %v3 = add nsw i32 %v2, -2
%v4 = getelementptr inbounds i16, ptr %a1, i32 %v3 %v4 = getelementptr inbounds i16, ptr %a1, i32 %v3
%v5 = load i16, ptr %v4, align 2, !tbaa !0 %v5 = load i16, ptr %v4, align 2, !tbaa !0
%v6 = getelementptr inbounds i16, ptr %a1, i32 %v1 %v6 = getelementptr inbounds i16, ptr %a1, i32 %v1
Show All 15 Lines

llvm/test/CodeGen/Hexagon/swp-physreg.ll

; RUN: llc -march=hexagon -enable-pipeliner < %s ; RUN: llc -march=hexagon -enable-pipeliner < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Make sure pipeliner handle physical registers (e.g., used in ; Make sure pipeliner handle physical registers (e.g., used in
; inline asm ; inline asm
@g0 = external global ptr, align 4 @g0 = external global ptr, align 4
; Function Attrs: nounwind ; Function Attrs: nounwind
define i32 @f0(i32 %a0, ptr nocapture %a1) #0 { define i32 @f0(i32 %a0, ptr nocapture %a1, i1 %c0, i1 %c1, i1 %c2) #0 {
b0: b0:
br i1 undef, label %b1, label %b2 br i1 %c0, label %b1, label %b2
b1: ; preds = %b0 b1: ; preds = %b0
unreachable unreachable
b2: ; preds = %b0 b2: ; preds = %b0
br label %b3 br label %b3
b3: ; preds = %b3, %b2 b3: ; preds = %b3, %b2
br i1 undef, label %b4, label %b3 br i1 %c1, label %b4, label %b3
b4: ; preds = %b3 b4: ; preds = %b3
br label %b5 br label %b5
b5: ; preds = %b5, %b4 b5: ; preds = %b5, %b4
%v0 = phi ptr [ inttoptr (i32 33554432 to ptr), %b4 ], [ %v4, %b5 ] %v0 = phi ptr [ inttoptr (i32 33554432 to ptr), %b4 ], [ %v4, %b5 ]
%v1 = phi i32 [ 0, %b4 ], [ %v5, %b5 ] %v1 = phi i32 [ 0, %b4 ], [ %v5, %b5 ]
%v2 = ptrtoint ptr %v0 to i32 %v2 = ptrtoint ptr %v0 to i32
tail call void asm sideeffect " r1 = $1\0A r0 = $0\0A memw(r0) = r1\0A dcfetch(r0)\0A", "r,r,~{r0},~{r1}"(i32 %v2, i32 %v1) #0 tail call void asm sideeffect " r1 = $1\0A r0 = $0\0A memw(r0) = r1\0A dcfetch(r0)\0A", "r,r,~{r0},~{r1}"(i32 %v2, i32 %v1) #0
%v3 = load ptr, ptr @g0, align 4 %v3 = load ptr, ptr @g0, align 4
%v4 = getelementptr inbounds i32, ptr %v3, i32 1 %v4 = getelementptr inbounds i32, ptr %v3, i32 1
store ptr %v4, ptr @g0, align 4 store ptr %v4, ptr @g0, align 4
%v5 = add nsw i32 %v1, 1 %v5 = add nsw i32 %v1, 1
%v6 = icmp eq i32 %v5, 200 %v6 = icmp eq i32 %v5, 200
br i1 %v6, label %b6, label %b5 br i1 %v6, label %b6, label %b5
b6: ; preds = %b5 b6: ; preds = %b5
br label %b7 br label %b7
b7: ; preds = %b7, %b6 b7: ; preds = %b7, %b6
br i1 undef, label %b8, label %b7 br i1 %c2, label %b8, label %b7
b8: ; preds = %b7 b8: ; preds = %b7
ret i32 0 ret i32 0
} }
attributes #0 = { nounwind "target-cpu"="hexagonv55" } attributes #0 = { nounwind "target-cpu"="hexagonv55" }

llvm/test/CodeGen/Hexagon/swp-prolog-phi.ll

; RUN: llc -march=hexagon -rdf-opt=0 < %s -pipeliner-experimental-cg=true | FileCheck %s ; RUN: llc -march=hexagon -rdf-opt=0 < %s -pipeliner-experimental-cg=true | FileCheck %s
; Test that we generate the correct name for a value in a prolog block. The ; Test that we generate the correct name for a value in a prolog block. The
; pipeliner was using an incorrect value for an instruction in the 2nd prolog ; pipeliner was using an incorrect value for an instruction in the 2nd prolog
; block for a value defined by a Phi. The result was that an instruction in
; the 1st and 2nd prolog blocks contain the same operands. ; the 1st and 2nd prolog blocks contain the same operands.
; CHECK: vcmp.gt([[VREG:(v[0-9]+)]].uh,v{{[0-9]+}}.uh) ; CHECK: vcmp.gt([[VREG:(v[0-9]+)]].uh,v{{[0-9]+}}.uh)
; CHECK-NOT: vcmp.gt([[VREG]].uh,v{{[0-9]+}}.uh) ; CHECK-NOT: vcmp.gt([[VREG]].uh,v{{[0-9]+}}.uh)
; CHECK: loop0 ; CHECK: loop0
define void @f0(<64 x i32> %a0, <32 x i32> %a1, i32 %a2) #0 { define void @f0(<64 x i32> %a0, <32 x i32> %a1, i32 %a2, i1 %c0, i1 %c1) #0 {
b0: b0:
br i1 undef, label %b1, label %b5 br i1 %c0, label %b1, label %b5
b1: ; preds = %b0 b1: ; preds = %b0
%v0 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %a0) %v0 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %a0)
br label %b2 br label %b2
b2: ; preds = %b4, %b1 b2: ; preds = %b4, %b1
%v1 = phi <32 x i32> [ %a1, %b1 ], [ %v7, %b4 ] %v1 = phi <32 x i32> [ %a1, %b1 ], [ %v7, %b4 ]
br label %b3 br label %b3
b3: ; preds = %b3, %b2 b3: ; preds = %b3, %b2
%v2 = phi i32 [ 0, %b2 ], [ %v8, %b3 ] %v2 = phi i32 [ 0, %b2 ], [ %v8, %b3 ]
%v3 = phi <32 x i32> [ zeroinitializer, %b2 ], [ %v0, %b3 ] %v3 = phi <32 x i32> [ zeroinitializer, %b2 ], [ %v0, %b3 ]
%v4 = phi <32 x i32> [ %v1, %b2 ], [ %v7, %b3 ] %v4 = phi <32 x i32> [ %v1, %b2 ], [ %v7, %b3 ]
%v5 = tail call <128 x i1> @llvm.hexagon.V6.vgtuh.128B(<32 x i32> %v3, <32 x i32> undef) %v5 = tail call <128 x i1> @llvm.hexagon.V6.vgtuh.128B(<32 x i32> %v3, <32 x i32> undef)
%v6 = tail call <128 x i1> @llvm.hexagon.V6.veqh.and.128B(<128 x i1> %v5, <32 x i32> undef, <32 x i32> undef) %v6 = tail call <128 x i1> @llvm.hexagon.V6.veqh.and.128B(<128 x i1> %v5, <32 x i32> undef, <32 x i32> undef)
%v7 = tail call <32 x i32> @llvm.hexagon.V6.vaddhq.128B(<128 x i1> %v6, <32 x i32> %v4, <32 x i32> undef) %v7 = tail call <32 x i32> @llvm.hexagon.V6.vaddhq.128B(<128 x i1> %v6, <32 x i32> %v4, <32 x i32> undef)
%v8 = add nsw i32 %v2, 1 %v8 = add nsw i32 %v2, 1
%v9 = icmp slt i32 %v8, %a2 %v9 = icmp slt i32 %v8, %a2
br i1 %v9, label %b3, label %b4 br i1 %v9, label %b3, label %b4
b4: ; preds = %b3 b4: ; preds = %b3
br i1 undef, label %b5, label %b2 br i1 %c1, label %b5, label %b2
b5: ; preds = %b4, %b0 b5: ; preds = %b4, %b0
ret void ret void
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <128 x i1> @llvm.hexagon.V6.vgtuh.128B(<32 x i32>, <32 x i32>) #1 declare <128 x i1> @llvm.hexagon.V6.vgtuh.128B(<32 x i32>, <32 x i32>) #1
Show All 11 Lines

llvm/test/CodeGen/Hexagon/swp-prolog-phi4.ll

; RUN: llc -march=hexagon -mcpu=hexagonv5 -verify-machineinstrs < %s ; RUN: llc -march=hexagon -mcpu=hexagonv5 -verify-machineinstrs < %s
; Test that the name rewriter code doesn't chase the Phi operands for ; Test that the name rewriter code doesn't chase the Phi operands for
; Phis that do not occur in the loop that is being pipelined. ; Phis that do not occur in the loop that is being pipelined.
define void @test(i32 %srcStride) local_unnamed_addr #0 { define void @test(i32 %srcStride, i1 %c0) local_unnamed_addr #0 {
entry: entry:
br label %for.body br label %for.body
for.body: for.body:
%add.ptr3.pn = phi ptr [ undef, %entry ], [ %src4.0394, %for.end ] %add.ptr3.pn = phi ptr [ undef, %entry ], [ %src4.0394, %for.end ]
%src2.0390 = phi ptr [ undef, %entry ], [ %add.ptr3.pn, %for.end ] %src2.0390 = phi ptr [ undef, %entry ], [ %add.ptr3.pn, %for.end ]
%src4.0394 = getelementptr inbounds i8, ptr %add.ptr3.pn, i32 %srcStride %src4.0394 = getelementptr inbounds i8, ptr %add.ptr3.pn, i32 %srcStride
%sri414 = load i8, ptr undef, align 1 %sri414 = load i8, ptr undef, align 1
br i1 undef, label %for.body9.epil, label %for.body9.preheader.new br i1 %c0, label %for.body9.epil, label %for.body9.preheader.new
for.body9.preheader.new: for.body9.preheader.new:
br label %for.body9.epil br label %for.body9.epil
for.body9.epil: for.body9.epil:
%inc.sink385.epil = phi i32 [ %add17.epil, %for.body9.epil ], [ 2, %for.body ], [ undef, %for.body9.preheader.new ] %inc.sink385.epil = phi i32 [ %add17.epil, %for.body9.epil ], [ 2, %for.body ], [ undef, %for.body9.preheader.new ]
%sr420.epil = phi i8 [ undef, %for.body9.epil ], [ %sri414, %for.body ], [ undef, %for.body9.preheader.new ] %sr420.epil = phi i8 [ undef, %for.body9.epil ], [ %sri414, %for.body ], [ undef, %for.body9.preheader.new ]
%sr421.epil = phi i8 [ %sr420.epil, %for.body9.epil ], [ undef, %for.body ], [ undef, %for.body9.preheader.new ] %sr421.epil = phi i8 [ %sr420.epil, %for.body9.epil ], [ undef, %for.body ], [ undef, %for.body9.preheader.new ]
▲ Show 20 Lines • Show All 42 Lines • Show Last 20 Lines

llvm/test/CodeGen/Hexagon/swp-regseq.ll

; RUN: llc -march=hexagon -enable-pipeliner < %s ; RUN: llc -march=hexagon -enable-pipeliner < %s
; REQUIRES: asserts ; REQUIRES: asserts
%s.0 = type { i64 } %s.0 = type { i64 }
define i64 @f0(ptr nocapture %a0, i32 %a1) { define i64 @f0(ptr nocapture %a0, i32 %a1, i1 %c0) {
b0: b0:
br i1 undef, label %b1, label %b2 br i1 %c0, label %b1, label %b2
b1: ; preds = %b1, %b0 b1: ; preds = %b1, %b0
%v0 = phi i32 [ %v6, %b1 ], [ 0, %b0 ] %v0 = phi i32 [ %v6, %b1 ], [ 0, %b0 ]
%v1 = phi i64 [ %v5, %b1 ], [ undef, %b0 ] %v1 = phi i64 [ %v5, %b1 ], [ undef, %b0 ]
%v2 = load i16, ptr undef, align 2 %v2 = load i16, ptr undef, align 2
%v3 = zext i16 %v2 to i64 %v3 = zext i16 %v2 to i64
%v4 = and i64 %v1, -4294967296 %v4 = and i64 %v1, -4294967296
%v5 = or i64 %v3, %v4 %v5 = or i64 %v3, %v4
%v6 = add nsw i32 %v0, 1 %v6 = add nsw i32 %v0, 1
%v7 = icmp eq i32 %v6, %a1 %v7 = icmp eq i32 %v6, %a1
br i1 %v7, label %b2, label %b1 br i1 %v7, label %b2, label %b1
b2: ; preds = %b1, %b0 b2: ; preds = %b1, %b0
%v8 = phi i64 [ undef, %b0 ], [ %v5, %b1 ] %v8 = phi i64 [ undef, %b0 ], [ %v5, %b1 ]
ret i64 %v8 ret i64 %v8
} }

llvm/test/CodeGen/Hexagon/swp-rename-dead-phi.ll

; RUN: llc -march=hexagon -fp-contract=fast -enable-pipeliner < %s ; RUN: llc -march=hexagon -fp-contract=fast -enable-pipeliner < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Pipelining can eliminate the need for a Phi if the loop carried use ; Pipelining can eliminate the need for a Phi if the loop carried use
; is scheduled first. We need to rename register uses of the Phi ; is scheduled first. We need to rename register uses of the Phi
; that may occur after the loop. ; that may occur after the loop.
define void @f0() #0 { define void @f0(i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5) #0 {
b0: b0:
br i1 undef, label %b1, label %b12 br i1 %c0, label %b1, label %b12
b1: ; preds = %b0 b1: ; preds = %b0
%v0 = load float, ptr undef, align 4 %v0 = load float, ptr undef, align 4
br i1 undef, label %b2, label %b5 br i1 %c1, label %b2, label %b5
b2: ; preds = %b1 b2: ; preds = %b1
br i1 undef, label %b3, label %b4 br i1 %c2, label %b3, label %b4
b3: ; preds = %b3, %b2 b3: ; preds = %b3, %b2
br label %b3 br label %b3
b4: ; preds = %b4, %b2 b4: ; preds = %b4, %b2
br i1 undef, label %b5, label %b4 br i1 %c3, label %b5, label %b4
b5: ; preds = %b4, %b1 b5: ; preds = %b4, %b1
br i1 undef, label %b6, label %b9 br i1 %c4, label %b6, label %b9
b6: ; preds = %b5 b6: ; preds = %b5
br i1 undef, label %b7, label %b8 br i1 %c5, label %b7, label %b8
b7: ; preds = %b7, %b6 b7: ; preds = %b7, %b6
br label %b7 br label %b7
b8: ; preds = %b8, %b6 b8: ; preds = %b8, %b6
%v1 = phi i32 [ %v7, %b8 ], [ 2, %b6 ] %v1 = phi i32 [ %v7, %b8 ], [ 2, %b6 ]
%v2 = phi float [ %v6, %b8 ], [ undef, %b6 ] %v2 = phi float [ %v6, %b8 ], [ undef, %b6 ]
%v3 = phi float [ %v2, %b8 ], [ undef, %b6 ] %v3 = phi float [ %v2, %b8 ], [ undef, %b6 ]
Show All 31 Lines

llvm/test/CodeGen/Hexagon/swp-reuse-phi-1.ll

; RUN: llc -march=hexagon -enable-pipeliner < %s ; RUN: llc -march=hexagon -enable-pipeliner < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0() #0 { define void @f0(i1 %c0) #0 {
b0: b0:
br i1 undef, label %b1, label %b3 br i1 %c0, label %b1, label %b3
b1: ; preds = %b0 b1: ; preds = %b0
br label %b2 br label %b2
b2: ; preds = %b2, %b1 b2: ; preds = %b2, %b1
%v0 = phi i32 [ 0, %b1 ], [ %v9, %b2 ] %v0 = phi i32 [ 0, %b1 ], [ %v9, %b2 ]
%v1 = phi <16 x i32> [ undef, %b1 ], [ %v2, %b2 ] %v1 = phi <16 x i32> [ undef, %b1 ], [ %v2, %b2 ]
%v2 = phi <16 x i32> [ undef, %b1 ], [ %v4, %b2 ] %v2 = phi <16 x i32> [ undef, %b1 ], [ %v4, %b2 ]
Show All 29 Lines

llvm/test/CodeGen/Hexagon/swp-reuse-phi-2.ll

; RUN: llc -march=hexagon -enable-pipeliner < %s ; RUN: llc -march=hexagon -enable-pipeliner < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Test that causes an assert when the phi reuse code does not set ; Test that causes an assert when the phi reuse code does not set
; PhiOp2 correctly for use in the next stage. This occurs when the ; PhiOp2 correctly for use in the next stage. This occurs when the
; number of stages is two or more. ; number of stages is two or more.
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0(ptr noalias nocapture %a0) #0 { define void @f0(ptr noalias nocapture %a0, i1 %c0) #0 {
b0: b0:
br i1 undef, label %b1, label %b3 br i1 %c0, label %b1, label %b3
b1: ; preds = %b0 b1: ; preds = %b0
br label %b2 br label %b2
b2: ; preds = %b2, %b1 b2: ; preds = %b2, %b1
%v1 = phi i32 [ 0, %b1 ], [ %v15, %b2 ] %v1 = phi i32 [ 0, %b1 ], [ %v15, %b2 ]
%v2 = phi ptr [ %a0, %b1 ], [ %v14, %b2 ] %v2 = phi ptr [ %a0, %b1 ], [ %v14, %b2 ]
%v3 = phi ptr [ undef, %b1 ], [ %v6, %b2 ] %v3 = phi ptr [ undef, %b1 ], [ %v6, %b2 ]
Show All 32 Lines

llvm/test/CodeGen/Hexagon/swp-reuse-phi-4.ll

Show All 31 Lines
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <16 x i32> @llvm.hexagon.V6.vmpyiwb.acc(<16 x i32>, <16 x i32>, i32) #0 declare <16 x i32> @llvm.hexagon.V6.vmpyiwb.acc(<16 x i32>, <16 x i32>, i32) #0
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <16 x i32> @llvm.hexagon.V6.vshuffob(<16 x i32>, <16 x i32>) #0 declare <16 x i32> @llvm.hexagon.V6.vshuffob(<16 x i32>, <16 x i32>) #0
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0(ptr noalias nocapture readonly %a0, i32 %a1, i32 %a2) #1 { define void @f0(ptr noalias nocapture readonly %a0, i32 %a1, i32 %a2, i1 %c0) #1 {
b0: b0:
%v0 = mul nsw i32 %a1, 2 %v0 = mul nsw i32 %a1, 2
br i1 undef, label %b1, label %b5 br i1 %c0, label %b1, label %b5
b1: ; preds = %b0 b1: ; preds = %b0
%v1 = getelementptr inbounds i8, ptr %a0, i32 %v0 %v1 = getelementptr inbounds i8, ptr %a0, i32 %v0
%v2 = icmp sgt i32 %a2, 64 %v2 = icmp sgt i32 %a2, 64
%v3 = add i32 %v0, 64 %v3 = add i32 %v0, 64
%v4 = add i32 %a1, 64 %v4 = add i32 %a1, 64
%v5 = sub i32 64, %a1 %v5 = sub i32 64, %a1
%v6 = sub i32 64, %v0 %v6 = sub i32 64, %v0
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
b4: ; preds = %b3, %b1 b4: ; preds = %b3, %b1
unreachable unreachable
b5: ; preds = %b0 b5: ; preds = %b0
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f1(i32 %a0, ptr %a1) #1 { define void @f1(i32 %a0, ptr %a1, i1 %c0, i1 %c1) #1 {
b0: b0:
%v0 = ptrtoint ptr %a1 to i32 %v0 = ptrtoint ptr %a1 to i32
%v1 = ashr i32 %a0, 1 %v1 = ashr i32 %a0, 1
%v2 = tail call i32 @llvm.hexagon.A2.combine.ll(i32 undef, i32 undef) %v2 = tail call i32 @llvm.hexagon.A2.combine.ll(i32 undef, i32 undef)
br i1 undef, label %b1, label %b2 br i1 %c0, label %b1, label %b2
b1: ; preds = %b1, %b0 b1: ; preds = %b1, %b0
br i1 undef, label %b1, label %b2 br i1 %c1, label %b1, label %b2
b2: ; preds = %b2, %b1, %b0 b2: ; preds = %b2, %b1, %b0
%v3 = phi i64 [ %v11, %b2 ], [ undef, %b0 ], [ undef, %b1 ] %v3 = phi i64 [ %v11, %b2 ], [ undef, %b0 ], [ undef, %b1 ]
%v4 = phi i32 [ %v12, %b2 ], [ 0, %b0 ], [ undef, %b1 ] %v4 = phi i32 [ %v12, %b2 ], [ 0, %b0 ], [ undef, %b1 ]
%v5 = phi i32 [ %v6, %b2 ], [ %v2, %b0 ], [ undef, %b1 ] %v5 = phi i32 [ %v6, %b2 ], [ %v2, %b0 ], [ undef, %b1 ]
%v6 = phi i32 [ %v10, %b2 ], [ undef, %b0 ], [ undef, %b1 ] %v6 = phi i32 [ %v10, %b2 ], [ undef, %b0 ], [ undef, %b1 ]
%v7 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 undef, i64 %v3, i64 undef) %v7 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 undef, i64 %v3, i64 undef)
%v8 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v5, i32 %v5) %v8 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v5, i32 %v5)
Show All 35 Lines

llvm/test/CodeGen/Hexagon/swp-stages.ll

; RUN: llc -march=hexagon -enable-aa-sched-mi -enable-pipeliner \ ; RUN: llc -march=hexagon -enable-aa-sched-mi -enable-pipeliner \
; RUN: -hexagon-expand-condsets=0 -pipeliner-max-stages=2 < %s ; RUN: -hexagon-expand-condsets=0 -pipeliner-max-stages=2 < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Disable expand-condsets because it will assert on undefined registers.
; Test that we generate pipelines with multiple stages correctly. ; Test that we generate pipelines with multiple stages correctly.
%s.0 = type { [194 x i32], ptr, [10 x i32], [10 x i32], i32, i32, i32, i32, i32, [9 x i32], [9 x i32], i16, i16, i16, i16, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr } %s.0 = type { [194 x i32], ptr, [10 x i32], [10 x i32], i32, i32, i32, i32, i32, [9 x i32], [9 x i32], i16, i16, i16, i16, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr }
%s.1 = type { [60 x i32], i16 } %s.1 = type { [60 x i32], i16 }
%s.2 = type { i32, [7 x i32], i16 } %s.2 = type { i32, [7 x i32], i16 }
%s.3 = type { [10 x i32] } %s.3 = type { [10 x i32] }
%s.4 = type { [10 x i32], [10 x i32] } %s.4 = type { [10 x i32], [10 x i32] }
%s.5 = type { [5 x i32], i32, i32 } %s.5 = type { [5 x i32], i32, i32 }
%s.6 = type { [5 x i32], i32, i32 } %s.6 = type { [5 x i32], i32, i32 }
%s.7 = type { [4 x i32], [4 x i32] } %s.7 = type { [4 x i32], [4 x i32] }
%s.8 = type { [5 x i32], i32, i32, i16, i16 } %s.8 = type { [5 x i32], i32, i32, i16, i16 }
%s.9 = type { i8, i32, i32, i32, [10 x i32], [10 x i32], [80 x i32], [80 x i32], [8 x i32], i32, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16 } %s.9 = type { i8, i32, i32, i32, [10 x i32], [10 x i32], [80 x i32], [80 x i32], [8 x i32], i32, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16 }
; Function Attrs: nounwind ; Function Attrs: nounwind
define fastcc void @f0(ptr %a0) #0 { define fastcc void @f0(ptr %a0, i1 %c0) #0 {
b0: b0:
%v0 = alloca [40 x i32], align 8 %v0 = alloca [40 x i32], align 8
%v1 = getelementptr inbounds %s.0, ptr %a0, i32 0, i32 5 %v1 = getelementptr inbounds %s.0, ptr %a0, i32 0, i32 5
%v2 = getelementptr inbounds %s.0, ptr %a0, i32 0, i32 6 %v2 = getelementptr inbounds %s.0, ptr %a0, i32 0, i32 6
%v3 = getelementptr inbounds %s.0, ptr %a0, i32 0, i32 4 %v3 = getelementptr inbounds %s.0, ptr %a0, i32 0, i32 4
%v4 = select i1 undef, ptr %v2, ptr %v1 %v4 = select i1 undef, ptr %v2, ptr %v1
%v5 = load i32, ptr %v4, align 4 %v5 = load i32, ptr %v4, align 4
br i1 false, label %b2, label %b1 br i1 false, label %b2, label %b1
b1: ; preds = %b0 b1: ; preds = %b0
%v6 = load i32, ptr %v3, align 4 %v6 = load i32, ptr %v3, align 4
br label %b2 br label %b2
b2: ; preds = %b1, %b0 b2: ; preds = %b1, %b0
%v7 = phi i32 [ %v6, %b1 ], [ undef, %b0 ] %v7 = phi i32 [ %v6, %b1 ], [ undef, %b0 ]
%v8 = shl i32 %v7, 1 %v8 = shl i32 %v7, 1
br i1 undef, label %b3, label %b4 br i1 %c0, label %b3, label %b4
b3: ; preds = %b3, %b2 b3: ; preds = %b3, %b2
%v9 = phi i32 [ %v34, %b3 ], [ %v5, %b2 ] %v9 = phi i32 [ %v34, %b3 ], [ %v5, %b2 ]
%v10 = add nsw i32 %v9, 2 %v10 = add nsw i32 %v9, 2
%v11 = getelementptr inbounds [40 x i32], ptr %v0, i32 0, i32 undef %v11 = getelementptr inbounds [40 x i32], ptr %v0, i32 0, i32 undef
%v12 = load i32, ptr %v11, align 4 %v12 = load i32, ptr %v11, align 4
%v13 = mul nsw i32 %v12, %v8 %v13 = mul nsw i32 %v12, %v8
%v14 = ashr i32 %v13, 15 %v14 = ashr i32 %v13, 15
Show All 31 Lines

llvm/test/CodeGen/Hexagon/swp-tfri.ll

; RUN: llc -march=hexagon -enable-pipeliner -hexagon-initial-cfg-cleanup=0 -stats -o /dev/null < %s 2>&1 -pipeliner-experimental-cg=true | FileCheck %s --check-prefix=STATS ; RUN: llc -march=hexagon -enable-pipeliner -hexagon-initial-cfg-cleanup=0 -stats -o /dev/null < %s 2>&1 -pipeliner-experimental-cg=true | FileCheck %s --check-prefix=STATS
; REQUIRES: asserts ; REQUIRES: asserts
; Check that we handle the case when a value is first defined in the loop.
; STATS: 1 pipeliner - Number of loops software pipelined ; STATS: 1 pipeliner - Number of loops software pipelined
; Function Attrs: nounwind ; Function Attrs: nounwind
define fastcc void @f0() #0 { define fastcc void @f0(i1 %c0, i1 %c1, i1 %c2, i1 %c3) #0 {
b0: b0:
br i1 undef, label %b7, label %b1 br i1 %c0, label %b7, label %b1
b1: ; preds = %b0 b1: ; preds = %b0
br i1 undef, label %b2, label %b4 br i1 %c1, label %b2, label %b4
b2: ; preds = %b1 b2: ; preds = %b1
%v0 = load i16, ptr undef, align 2 %v0 = load i16, ptr undef, align 2
%v1 = load i16, ptr undef, align 2 %v1 = load i16, ptr undef, align 2
br i1 undef, label %b5, label %b3 br i1 %c2, label %b5, label %b3
b3: ; preds = %b5, %b2 b3: ; preds = %b5, %b2
%v2 = phi i16 [ 0, %b2 ], [ %v14, %b5 ] %v2 = phi i16 [ 0, %b2 ], [ %v14, %b5 ]
br label %b4 br label %b4
b4: ; preds = %b3, %b1 b4: ; preds = %b3, %b1
br i1 undef, label %b7, label %b6 br i1 %c3, label %b7, label %b6
b5: ; preds = %b5, %b2 b5: ; preds = %b5, %b2
%v3 = phi i16 [ %v5, %b5 ], [ undef, %b2 ] %v3 = phi i16 [ %v5, %b5 ], [ undef, %b2 ]
%v4 = phi i16 [ 0, %b5 ], [ %v1, %b2 ] %v4 = phi i16 [ 0, %b5 ], [ %v1, %b2 ]
%v5 = phi i16 [ 0, %b5 ], [ %v0, %b2 ] %v5 = phi i16 [ 0, %b5 ], [ %v0, %b2 ]
%v6 = phi i16 [ %v4, %b5 ], [ undef, %b2 ] %v6 = phi i16 [ %v4, %b5 ], [ undef, %b2 ]
%v7 = phi i16 [ %v14, %b5 ], [ 0, %b2 ] %v7 = phi i16 [ %v14, %b5 ], [ 0, %b2 ]
%v8 = phi i32 [ %v15, %b5 ], [ undef, %b2 ] %v8 = phi i32 [ %v15, %b5 ], [ undef, %b2 ]
Show All 18 Lines

llvm/test/CodeGen/Hexagon/tail-dup-subreg-map.ll

; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s ; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s
; REQUIRES: asserts ; REQUIRES: asserts
; When tail-duplicating a block with PHI nodes that use subregisters, the ; When tail-duplicating a block with PHI nodes that use subregisters, the
; subregisters were dropped by the tail duplicator, resulting in invalid ; subregisters were dropped by the tail duplicator, resulting in invalid
; COPY instructions being generated. ; COPY instructions being generated.
; CHECK: = asl(r{{[0-9]+}}:{{[0-9]+}},#15) ; CHECK: = asl(r{{[0-9]+}}:{{[0-9]+}},#15)
target triple = "hexagon" target triple = "hexagon"
%struct.0 = type { i64, i16 } %struct.0 = type { i64, i16 }
%struct.1 = type { i64, i64 } %struct.1 = type { i64, i64 }
declare hidden fastcc void @foo(ptr noalias nocapture, i8 signext, i8 zeroext, i32, i64, i64) unnamed_addr #0 declare hidden fastcc void @foo(ptr noalias nocapture, i8 signext, i8 zeroext, i32, i64, i64) unnamed_addr #0
define void @fred(ptr noalias nocapture sret(%struct.0) %agg.result, ptr byval(%struct.1) nocapture readonly align 8 %a, i32 %a0) #1 { define void @fred(ptr noalias nocapture sret(%struct.0) %agg.result, ptr byval(%struct.1) nocapture readonly align 8 %a, i32 %a0, i1 %c0, i1 %c1) #1 {
entry: entry:
%0 = load i64, ptr undef, align 8 %0 = load i64, ptr undef, align 8
switch i32 %a0, label %if.else [ switch i32 %a0, label %if.else [
i32 32767, label %if.then i32 32767, label %if.then
i32 0, label %if.then7 i32 0, label %if.then7
] ]
if.then: ; preds = %entry if.then: ; preds = %entry
ret void ret void
if.then7: ; preds = %entry if.then7: ; preds = %entry
br i1 undef, label %if.then.i, label %if.else16.i br i1 %c0, label %if.then.i, label %if.else16.i
if.then.i: ; preds = %if.then7 if.then.i: ; preds = %if.then7
br i1 undef, label %if.then5.i, label %if.else.i br i1 %c1, label %if.then5.i, label %if.else.i
if.then5.i: ; preds = %if.then.i if.then5.i: ; preds = %if.then.i
%shl.i21 = shl i64 %0, 0 %shl.i21 = shl i64 %0, 0
br label %if.end.i br label %if.end.i
if.else.i: ; preds = %if.then.i if.else.i: ; preds = %if.then.i
%shl12.i = shl i64 %0, 7 %shl12.i = shl i64 %0, 7
br label %if.end.i br label %if.end.i
Show All 27 Lines

llvm/test/CodeGen/Hexagon/tied_oper.ll

; RUN: llc -march=hexagon -O3 -verify-machineinstrs -disable-hexagon-peephole < %s ; RUN: llc -march=hexagon -O3 -verify-machineinstrs -disable-hexagon-peephole < %s
; REQUIRES: asserts ; REQUIRES: asserts
; This test checks if tied operands are consistent. ; This test checks if tied operands are consistent.
target triple = "hexagon-unknown--elf" target triple = "hexagon-unknown--elf"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0(ptr nocapture %a0) #0 { define void @f0(ptr nocapture %a0, i1 %c0) #0 {
b0: b0:
br label %b1 br label %b1
b1: ; preds = %b5, %b0 b1: ; preds = %b5, %b0
%v0 = phi ptr [ %a0, %b0 ], [ %v5, %b5 ] %v0 = phi ptr [ %a0, %b0 ], [ %v5, %b5 ]
%v1 = phi i16 [ undef, %b0 ], [ %v10, %b5 ] %v1 = phi i16 [ undef, %b0 ], [ %v10, %b5 ]
br i1 undef, label %b2, label %b3 br i1 %c0, label %b2, label %b3
b2: ; preds = %b1 b2: ; preds = %b1
%v2 = getelementptr inbounds i16, ptr %v0, i32 1 %v2 = getelementptr inbounds i16, ptr %v0, i32 1
%v3 = load i16, ptr %v0, align 2, !tbaa !0 %v3 = load i16, ptr %v0, align 2, !tbaa !0
br label %b3 br label %b3
b3: ; preds = %b2, %b1 b3: ; preds = %b2, %b1
%v4 = phi i16 [ %v3, %b2 ], [ %v1, %b1 ] %v4 = phi i16 [ %v3, %b2 ], [ %v1, %b1 ]
Show All 26 Lines

llvm/test/CodeGen/Hexagon/trunc-mpy.ll

; RUN: llc -march=hexagon -disable-hexagon-peephole < %s | FileCheck %s ; RUN: llc -march=hexagon -disable-hexagon-peephole < %s | FileCheck %s
; Test that we're generating a 32-bit multiply high instead of a 64-bit version, ; Test that we're generating a 32-bit multiply high instead of a 64-bit version,
; when using the high 32-bits only. ; when using the high 32-bits only.
; CHECK-LABEL: f0: ; CHECK-LABEL: f0:
; CHECK-NOT: r{{[0-9]+}}:{{[0-9]+}} = mpy( ; CHECK-NOT: r{{[0-9]+}}:{{[0-9]+}} = mpy(
define void @f0(ptr nocapture readonly %a0, ptr nocapture %a1) #0 { define void @f0(ptr nocapture readonly %a0, ptr nocapture %a1, i1 %c0) #0 {
b0: b0:
%v0 = getelementptr i32, ptr %a1, i32 448 %v0 = getelementptr i32, ptr %a1, i32 448
br label %b1 br label %b1
b1: ; preds = %b1, %b0 b1: ; preds = %b1, %b0
br i1 undef, label %b2, label %b1 br i1 %c0, label %b2, label %b1
b2: ; preds = %b1 b2: ; preds = %b1
%v1 = getelementptr inbounds i32, ptr %a0, i32 64 %v1 = getelementptr inbounds i32, ptr %a0, i32 64
%v2 = load i32, ptr %a0, align 4 %v2 = load i32, ptr %a0, align 4
%v3 = getelementptr inbounds i32, ptr %a0, i32 2 %v3 = getelementptr inbounds i32, ptr %a0, i32 2
%v4 = load i32, ptr %v1, align 4 %v4 = load i32, ptr %v1, align 4
%v5 = sext i32 %v2 to i64 %v5 = sext i32 %v2 to i64
%v6 = sext i32 %v4 to i64 %v6 = sext i32 %v4 to i64
%v7 = mul nsw i64 %v6, %v5 %v7 = mul nsw i64 %v6, %v5
%v8 = lshr i64 %v7, 32 %v8 = lshr i64 %v7, 32
%v9 = trunc i64 %v8 to i32 %v9 = trunc i64 %v8 to i32
%v10 = sub nsw i32 0, %v9 %v10 = sub nsw i32 0, %v9
%v11 = getelementptr inbounds i32, ptr %v0, i32 1 %v11 = getelementptr inbounds i32, ptr %v0, i32 1
store i32 %v10, ptr %v1, align 4 store i32 %v10, ptr %v1, align 4
ret void ret void
} }
; Similar to above, but using the operands of the multiply are expressions. ; Similar to above, but using the operands of the multiply are expressions.
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: r{{[0-9]+}} = mpy( ; CHECK: r{{[0-9]+}} = mpy(
define void @f1(i32 %a0, i32 %a1, ptr nocapture readonly %a2, ptr nocapture %a3) #0 { define void @f1(i32 %a0, i32 %a1, ptr nocapture readonly %a2, ptr nocapture %a3, i1 %c0) #0 {
b0: b0:
%v0 = getelementptr i32, ptr %a3, i32 448 %v0 = getelementptr i32, ptr %a3, i32 448
br label %b1 br label %b1
b1: ; preds = %b1, %b0 b1: ; preds = %b1, %b0
br i1 undef, label %b2, label %b1 br i1 %c0, label %b2, label %b1
b2: ; preds = %b1 b2: ; preds = %b1
%v1 = getelementptr inbounds i32, ptr %a2, i32 64 %v1 = getelementptr inbounds i32, ptr %a2, i32 64
%v2 = sext i32 %a0 to i64 %v2 = sext i32 %a0 to i64
%v3 = sext i32 %a1 to i64 %v3 = sext i32 %a1 to i64
%v4 = mul nsw i64 %v3, %v2 %v4 = mul nsw i64 %v3, %v2
%v5 = lshr i64 %v4, 32 %v5 = lshr i64 %v4, 32
%v6 = trunc i64 %v5 to i32 %v6 = trunc i64 %v5 to i32
Show All 38 Lines

llvm/test/CodeGen/Hexagon/v6-unaligned-spill.ll

; RUN: llc -march=hexagon < %s | FileCheck %s ; RUN: llc -march=hexagon < %s | FileCheck %s
; Test that we no longer generate an unaligned vector store for a spill when ; Test that we no longer generate an unaligned vector store for a spill when
; a function has an alloca. ; a function has an alloca.
; CHECK: vmem({{.*}}) = ; CHECK: vmem({{.*}}) =
%s.0 = type { [5 x [4 x i8]], i32, i32, i32, i32 } %s.0 = type { [5 x [4 x i8]], i32, i32, i32, i32 }
; Function Attrs: nounwind ; Function Attrs: nounwind
define i32 @f0(ptr nocapture readonly %a0, ptr nocapture %a1, ptr nocapture readonly %a2, ptr nocapture readonly %a3, i32 %a4, i32 %a5, i32 %a6, ptr nocapture readonly %a7) #0 { define i32 @f0(ptr nocapture readonly %a0, ptr nocapture %a1, ptr nocapture readonly %a2, ptr nocapture readonly %a3, i32 %a4, i32 %a5, i32 %a6, ptr nocapture readonly %a7, i1 %c0, i1 %c1) #0 {
b0: b0:
%v0 = alloca i8, i32 %a4, align 128 %v0 = alloca i8, i32 %a4, align 128
br i1 undef, label %b1, label %b5 br i1 %c0, label %b1, label %b5
b1: ; preds = %b0 b1: ; preds = %b0
%v1 = icmp sgt i32 %a5, 2 %v1 = icmp sgt i32 %a5, 2
br label %b2 br label %b2
b2: ; preds = %b3, %b2, %b1 b2: ; preds = %b3, %b2, %b1
br i1 undef, label %b3, label %b2 br i1 %c1, label %b3, label %b2
b3: ; preds = %b2 b3: ; preds = %b2
call void @f1(ptr undef, ptr undef, ptr nonnull %v0, i32 %a4, i32 %a5, ptr %a7) call void @f1(ptr undef, ptr undef, ptr nonnull %v0, i32 %a4, i32 %a5, ptr %a7)
%v2 = tail call <32 x i32> @llvm.hexagon.V6.vd0.128B() #2 %v2 = tail call <32 x i32> @llvm.hexagon.V6.vd0.128B() #2
br i1 %v1, label %b4, label %b2 br i1 %v1, label %b4, label %b2
b4: ; preds = %b4, %b3 b4: ; preds = %b4, %b3
%v3 = phi <32 x i32> [ %v5, %b4 ], [ undef, %b3 ] %v3 = phi <32 x i32> [ %v5, %b4 ], [ undef, %b3 ]
Show All 23 Lines

llvm/test/CodeGen/Hexagon/v60-cur.ll

; RUN: llc -march=hexagon < %s | FileCheck %s ; RUN: llc -march=hexagon < %s | FileCheck %s
; Test that we generate a .cur ; Test that we generate a .cur
; CHECK: v{{[0-9]*}}.cur ; CHECK: v{{[0-9]*}}.cur
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0(ptr noalias nocapture readonly %a0, i32 %a1, i32 %a2, ptr %a3, ptr %a4) #0 { define void @f0(ptr noalias nocapture readonly %a0, i32 %a1, i32 %a2, ptr %a3, ptr %a4, i1 %c0) #0 {
b0: b0:
br i1 undef, label %b1, label %b3 br i1 %c0, label %b1, label %b3
b1: ; preds = %b0 b1: ; preds = %b0
br label %b2 br label %b2
b2: ; preds = %b2, %b1 b2: ; preds = %b2, %b1
%v0 = phi ptr [ %a0, %b1 ], [ %v4, %b2 ] %v0 = phi ptr [ %a0, %b1 ], [ %v4, %b2 ]
%v1 = phi i32 [ 0, %b1 ], [ %v23, %b2 ] %v1 = phi i32 [ 0, %b1 ], [ %v23, %b2 ]
%v2 = phi <16 x i32> [ zeroinitializer, %b1 ], [ %v6, %b2 ] %v2 = phi <16 x i32> [ zeroinitializer, %b1 ], [ %v6, %b2 ]
▲ Show 20 Lines • Show All 43 Lines • Show Last 20 Lines

llvm/test/CodeGen/Hexagon/v6vec_zero.ll

; RUN: llc -march=hexagon < %s ; RUN: llc -march=hexagon < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Test that we do not ICE with a cannot select message when ; Test that we do not ICE with a cannot select message when
; generating a v16i32 constant pool node. ; generating a v16i32 constant pool node.
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0() #0 { define void @f0(i1 %c0) #0 {
b0: b0:
br i1 undef, label %b1, label %b2 br i1 %c0, label %b1, label %b2
b1: ; preds = %b1, %b0 b1: ; preds = %b1, %b0
%v0 = phi i32 [ 0, %b1 ], [ 0, %b0 ] %v0 = phi i32 [ 0, %b1 ], [ 0, %b0 ]
store <16 x i32> zeroinitializer, ptr null, align 64 store <16 x i32> zeroinitializer, ptr null, align 64
br i1 false, label %b1, label %b2 br i1 false, label %b1, label %b2
b2: ; preds = %b1, %b0 b2: ; preds = %b1, %b0
ret void ret void
} }
attributes #0 = { nounwind "target-cpu"="hexagonv60" } attributes #0 = { nounwind "target-cpu"="hexagonv60" }

llvm/test/CodeGen/Hexagon/vassign-to-combine.ll

Show All 10 Lines
declare <32 x i32> @llvm.hexagon.V6.vabsdiffuh.128B(<32 x i32>, <32 x i32>) #0 declare <32 x i32> @llvm.hexagon.V6.vabsdiffuh.128B(<32 x i32>, <32 x i32>) #0
declare <32 x i32> @llvm.hexagon.V6.vlalignbi.128B(<32 x i32>, <32 x i32>, i32) #0 declare <32 x i32> @llvm.hexagon.V6.vlalignbi.128B(<32 x i32>, <32 x i32>, i32) #0
declare <32 x i32> @llvm.hexagon.V6.vsathub.128B(<32 x i32>, <32 x i32>) #0 declare <32 x i32> @llvm.hexagon.V6.vsathub.128B(<32 x i32>, <32 x i32>) #0
declare <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32>, <64 x i32>) #0 declare <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32>, <64 x i32>) #0
declare <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32>, <64 x i32>) #0 declare <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32>, <64 x i32>) #0
declare <64 x i32> @llvm.hexagon.V6.vaddubh.128B(<32 x i32>, <32 x i32>) #0 declare <64 x i32> @llvm.hexagon.V6.vaddubh.128B(<32 x i32>, <32 x i32>) #0
declare <64 x i32> @llvm.hexagon.V6.vmpyub.128B(<32 x i32>, i32) #0 declare <64 x i32> @llvm.hexagon.V6.vmpyub.128B(<32 x i32>, i32) #0
define void @f0(ptr %a0, ptr %a1) local_unnamed_addr #1 { define void @f0(ptr %a0, ptr %a1, i1 %c0) local_unnamed_addr #1 {
b0: b0:
%v0 = load <32 x i32>, ptr %a0, align 128 %v0 = load <32 x i32>, ptr %a0, align 128
%v1 = load <32 x i32>, ptr %a1, align 128 %v1 = load <32 x i32>, ptr %a1, align 128
br i1 undef, label %b2, label %b1 br i1 %c0, label %b2, label %b1
b1: ; preds = %b0 b1: ; preds = %b0
%v2 = tail call <32 x i32> @llvm.hexagon.V6.vlalignbi.128B(<32 x i32> %v0, <32 x i32> %v1, i32 1) %v2 = tail call <32 x i32> @llvm.hexagon.V6.vlalignbi.128B(<32 x i32> %v0, <32 x i32> %v1, i32 1)
%v3 = tail call <64 x i32> @llvm.hexagon.V6.vmpyub.128B(<32 x i32> %v2, i32 33686018) #1 %v3 = tail call <64 x i32> @llvm.hexagon.V6.vmpyub.128B(<32 x i32> %v2, i32 33686018) #1
%v4 = tail call <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32> undef, <64 x i32> %v3) #1 %v4 = tail call <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32> undef, <64 x i32> %v3) #1
%v5 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v4) %v5 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v4)
%v6 = tail call <32 x i32> @llvm.hexagon.V6.vabsdiffuh.128B(<32 x i32> %v5, <32 x i32> undef) #1 %v6 = tail call <32 x i32> @llvm.hexagon.V6.vabsdiffuh.128B(<32 x i32> %v5, <32 x i32> undef) #1
%v7 = tail call <64 x i32> @llvm.hexagon.V6.vaddubh.128B(<32 x i32> %v6, <32 x i32> undef) %v7 = tail call <64 x i32> @llvm.hexagon.V6.vaddubh.128B(<32 x i32> %v6, <32 x i32> undef)
Show All 24 Lines

llvm/test/CodeGen/Hexagon/vcombine128_to_req_seq.ll

Show All 23 Linesb0:
%v18 = getelementptr inbounds i8, ptr %a3, i32 32 %v18 = getelementptr inbounds i8, ptr %a3, i32 32
store <32 x i32> %v15, ptr %v18, align 128 store <32 x i32> %v15, ptr %v18, align 128
store <32 x i32> %v17, ptr %a3, align 128 store <32 x i32> %v17, ptr %a3, align 128
ret void ret void
} }
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK-NOT: vcombine ; CHECK-NOT: vcombine
define void @f1() #0 { define void @f1(i1 %c0) #0 {
b0: b0:
br i1 undef, label %b1, label %b3 br i1 %c0, label %b1, label %b3
b1: ; preds = %b1, %b0 b1: ; preds = %b1, %b0
%v0 = phi <64 x i32> [ %v6, %b1 ], [ undef, %b0 ] %v0 = phi <64 x i32> [ %v6, %b1 ], [ undef, %b0 ]
%v1 = tail call <64 x i32> @llvm.hexagon.V6.vmpybus.acc.128B(<64 x i32> %v0, <32 x i32> undef, i32 16843009) %v1 = tail call <64 x i32> @llvm.hexagon.V6.vmpybus.acc.128B(<64 x i32> %v0, <32 x i32> undef, i32 16843009)
%v2 = tail call <64 x i32> @llvm.hexagon.V6.vmpabus.acc.128B(<64 x i32> %v1, <64 x i32> undef, i32 16843009) %v2 = tail call <64 x i32> @llvm.hexagon.V6.vmpabus.acc.128B(<64 x i32> %v1, <64 x i32> undef, i32 16843009)
%v3 = tail call <64 x i32> @llvm.hexagon.V6.vmpabus.acc.128B(<64 x i32> %v2, <64 x i32> undef, i32 16843009) %v3 = tail call <64 x i32> @llvm.hexagon.V6.vmpabus.acc.128B(<64 x i32> %v2, <64 x i32> undef, i32 16843009)
%v4 = tail call <64 x i32> @llvm.hexagon.V6.vmpabus.acc.128B(<64 x i32> %v3, <64 x i32> undef, i32 16843009) %v4 = tail call <64 x i32> @llvm.hexagon.V6.vmpabus.acc.128B(<64 x i32> %v3, <64 x i32> undef, i32 16843009)
%v5 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> undef, <32 x i32> undef) %v5 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> undef, <32 x i32> undef)
Show All 34 Lines

llvm/test/CodeGen/Hexagon/vect-zero_extend.ll

; RUN: llc -march=hexagon < %s ; RUN: llc -march=hexagon < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Used to fail with "Cannot select: 0x16cb2d0: v4i16 = zero_extend" ; Used to fail with "Cannot select: 0x16cb2d0: v4i16 = zero_extend"
target triple = "hexagon-unknown-linux-gnu" target triple = "hexagon-unknown-linux-gnu"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f0() #0 { define void @f0(i1 %c0) #0 {
b0: b0:
br i1 undef, label %b1, label %b3 br i1 %c0, label %b1, label %b3
b1: ; preds = %b0 b1: ; preds = %b0
br label %b2 br label %b2
b2: ; preds = %b2, %b1 b2: ; preds = %b2, %b1
%v0 = load <3 x i8>, ptr undef, align 8 %v0 = load <3 x i8>, ptr undef, align 8
%v1 = zext <3 x i8> %v0 to <3 x i16> %v1 = zext <3 x i8> %v0 to <3 x i16>
store <3 x i16> %v1, ptr undef, align 8 store <3 x i16> %v1, ptr undef, align 8
br label %b2 br label %b2
b3: ; preds = %b0 b3: ; preds = %b0
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

llvm/test/CodeGen/Hexagon/vect/vect-bitcast-1.ll

; RUN: llc -march=hexagon < %s ; RUN: llc -march=hexagon < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Used to fail with: Assertion `VT.getSizeInBits() == Operand.getValueType().getSizeInBits() && "Cannot BITCAST between types of different sizes!"' failed. ; Used to fail with: Assertion `VT.getSizeInBits() == Operand.getValueType().getSizeInBits() && "Cannot BITCAST between types of different sizes!"' failed.
target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32" target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32"
target triple = "hexagon-unknown-linux-gnu" target triple = "hexagon-unknown-linux-gnu"
define void @foo() nounwind { define void @foo(i1 %c0) nounwind {
entry: entry:
br label %while.body br label %while.body
while.body: ; preds = %if.then155, %if.then12, %entry while.body: ; preds = %if.then155, %if.then12, %entry
%cmp.i = icmp eq ptr undef, null %cmp.i = icmp eq ptr undef, null
br i1 %cmp.i, label %lab_ci.exit, label %if.end.i br i1 %cmp.i, label %lab_ci.exit, label %if.end.i
if.end.i: ; preds = %while.body if.end.i: ; preds = %while.body
unreachable unreachable
lab_ci.exit: ; preds = %while.body lab_ci.exit: ; preds = %while.body
br i1 false, label %if.then, label %if.else br i1 false, label %if.then, label %if.else
if.then: ; preds = %lab_ci.exit if.then: ; preds = %lab_ci.exit
unreachable unreachable
if.else: ; preds = %lab_ci.exit if.else: ; preds = %lab_ci.exit
br i1 undef, label %if.then12, label %if.else17 br i1 %c0, label %if.then12, label %if.else17
if.then12: ; preds = %if.else if.then12: ; preds = %if.else
br label %while.body br label %while.body
if.else17: ; preds = %if.else if.else17: ; preds = %if.else
br i1 false, label %if.then22, label %if.else35 br i1 false, label %if.then22, label %if.else35
if.then22: ; preds = %if.else17 if.then22: ; preds = %if.else17
Show All 34 Lines

llvm/test/CodeGen/Hexagon/vect/vect-bitcast.ll

; RUN: llc -march=hexagon < %s ; RUN: llc -march=hexagon < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Used to fail with "Cannot BITCAST between types of different sizes!" ; Used to fail with "Cannot BITCAST between types of different sizes!"
target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
target triple = "hexagon" target triple = "hexagon"
define void @foo() nounwind { define void @foo(i1 %c0, i1 %c1) nounwind {
entry: entry:
br label %while.body br label %while.body
while.body: ; preds = %if.then155, %if.then12, %if.then, %entry while.body: ; preds = %if.then155, %if.then12, %if.then, %entry
br i1 undef, label %if.then, label %if.else br i1 %c0, label %if.then, label %if.else
if.then: ; preds = %while.body if.then: ; preds = %while.body
br label %while.body br label %while.body
if.else: ; preds = %while.body if.else: ; preds = %while.body
br i1 undef, label %if.then12, label %if.else17 br i1 %c1, label %if.then12, label %if.else17
if.then12: ; preds = %if.else if.then12: ; preds = %if.else
br label %while.body br label %while.body
if.else17: ; preds = %if.else if.else17: ; preds = %if.else
br i1 false, label %if.then22, label %if.else35 br i1 false, label %if.then22, label %if.else35
if.then22: ; preds = %if.else17 if.then22: ; preds = %if.else17
Show All 29 Lines

llvm/test/CodeGen/Hexagon/vect/vect-illegal-type.ll

; RUN: llc -march=hexagon < %s ; RUN: llc -march=hexagon < %s
; REQUIRES: asserts ; REQUIRES: asserts
; Used to fail with "Unexpected illegal type!" ; Used to fail with "Unexpected illegal type!"
; Used to fail with "Cannot select: ch = store x,x,x,<ST4[undef](align=8), trunc to v4i8>" ; Used to fail with "Cannot select: ch = store x,x,x,<ST4[undef](align=8), trunc to v4i8>"
; ModuleID = 'bugpoint-reduced-simplified.bc' ; ModuleID = 'bugpoint-reduced-simplified.bc'
target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32" target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32"
target triple = "hexagon-unknown-linux-gnu" target triple = "hexagon-unknown-linux-gnu"
define void @foo() nounwind { define void @foo(i1 %c0, i1 %c1, i1 %c2) nounwind {
entry: entry:
br label %for.body br label %for.body
for.body: ; preds = %for.body, %entry for.body: ; preds = %for.body, %entry
br i1 undef, label %for.end, label %for.body br i1 %c0, label %for.end, label %for.body
for.end: ; preds = %for.body for.end: ; preds = %for.body
br label %for.body71 br label %for.body71
for.body71: ; preds = %for.body71, %for.end for.body71: ; preds = %for.body71, %for.end
br i1 undef, label %for.end96, label %for.body71 br i1 %c1, label %for.end96, label %for.body71
for.end96: ; preds = %for.body71 for.end96: ; preds = %for.body71
switch i32 undef, label %sw.epilog [ switch i32 undef, label %sw.epilog [
i32 1, label %for.cond375.preheader i32 1, label %for.cond375.preheader
i32 8, label %for.cond591 i32 8, label %for.cond591
] ]
for.cond375.preheader: ; preds = %for.end96 for.cond375.preheader: ; preds = %for.end96
br label %polly.loop_header228 br label %polly.loop_header228
for.cond591: ; preds = %for.end96 for.cond591: ; preds = %for.end96
br label %for.body664 br label %for.body664
for.body664: ; preds = %for.body664, %for.cond591 for.body664: ; preds = %for.body664, %for.cond591
br i1 undef, label %for.end670, label %for.body664 br i1 %c2, label %for.end670, label %for.body664
for.end670: ; preds = %for.body664 for.end670: ; preds = %for.body664
br label %sw.epilog br label %sw.epilog
sw.epilog: ; preds = %for.end670, %for.end96 sw.epilog: ; preds = %for.end670, %for.end96
ret void ret void
polly.loop_header228: ; preds = %polly.loop_header228, %for.cond375.preheader polly.loop_header228: ; preds = %polly.loop_header228, %for.cond375.preheader
%_p_splat_one = load <1 x i16>, ptr undef, align 8 %_p_splat_one = load <1 x i16>, ptr undef, align 8
%_p_splat = shufflevector <1 x i16> %_p_splat_one, <1 x i16> %_p_splat_one, <4 x i32> zeroinitializer %_p_splat = shufflevector <1 x i16> %_p_splat_one, <1 x i16> %_p_splat_one, <4 x i32> zeroinitializer
%0 = trunc <4 x i16> %_p_splat to <4 x i8> %0 = trunc <4 x i16> %_p_splat to <4 x i8>
store <4 x i8> %0, ptr undef, align 8 store <4 x i8> %0, ptr undef, align 8
br label %polly.loop_header228 br label %polly.loop_header228
} }

llvm/test/CodeGen/Hexagon/vect/vect-load.ll

; RUN: llc -march=hexagon < %s ; RUN: llc -march=hexagon < %s
; Used to fail with "Cannot select: 0x16cf370: v2i16,ch = load" ; Used to fail with "Cannot select: 0x16cf370: v2i16,ch = load"
; ModuleID = 'bugpoint-reduced-simplified.bc' ; ModuleID = 'bugpoint-reduced-simplified.bc'
target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32" target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32"
target triple = "hexagon-unknown-linux-gnu" target triple = "hexagon-unknown-linux-gnu"
%struct.ext_hdrs.10.65.142.274.307.318.329.681.692.703.714.725.736.758.791.802.846.857.868.879.890.901.945.956.958 = type { i8, i8, i8, i8, i8, i8, i16, i32, [8 x %struct.hcdc_ext_vec.9.64.141.273.306.317.328.680.691.702.713.724.735.757.790.801.845.856.867.878.889.900.944.955.957] } %struct.ext_hdrs.10.65.142.274.307.318.329.681.692.703.714.725.736.758.791.802.846.857.868.879.890.901.945.956.958 = type { i8, i8, i8, i8, i8, i8, i16, i32, [8 x %struct.hcdc_ext_vec.9.64.141.273.306.317.328.680.691.702.713.724.735.757.790.801.845.856.867.878.889.900.944.955.957] }
%struct.hcdc_ext_vec.9.64.141.273.306.317.328.680.691.702.713.724.735.757.790.801.845.856.867.878.889.900.944.955.957 = type { i8, i8, i16 } %struct.hcdc_ext_vec.9.64.141.273.306.317.328.680.691.702.713.724.735.757.790.801.845.856.867.878.889.900.944.955.957 = type { i8, i8, i16 }
define void @foo(ptr %hc_ext_info) nounwind { define void @foo(ptr %hc_ext_info, i1 %c0, i1 %c1, i1 %c2, i1 %c3) nounwind {
entry: entry:
br i1 undef, label %if.end, label %if.then br i1 %c0, label %if.end, label %if.then
if.then: ; preds = %entry if.then: ; preds = %entry
unreachable unreachable
if.end: ; preds = %entry if.end: ; preds = %entry
br i1 undef, label %if.end5, label %if.then3 br i1 %c1, label %if.end5, label %if.then3
if.then3: ; preds = %if.end if.then3: ; preds = %if.end
br label %if.end5 br label %if.end5
if.end5: ; preds = %if.then3, %if.end if.end5: ; preds = %if.then3, %if.end
%add.ptr = getelementptr inbounds %struct.ext_hdrs.10.65.142.274.307.318.329.681.692.703.714.725.736.758.791.802.846.857.868.879.890.901.945.956.958, ptr %hc_ext_info, i32 0, i32 8, i32 0 %add.ptr = getelementptr inbounds %struct.ext_hdrs.10.65.142.274.307.318.329.681.692.703.714.725.736.758.791.802.846.857.868.879.890.901.945.956.958, ptr %hc_ext_info, i32 0, i32 8, i32 0
%add.ptr22 = getelementptr inbounds %struct.ext_hdrs.10.65.142.274.307.318.329.681.692.703.714.725.736.758.791.802.846.857.868.879.890.901.945.956.958, ptr null, i32 0, i32 8, i32 undef %add.ptr22 = getelementptr inbounds %struct.ext_hdrs.10.65.142.274.307.318.329.681.692.703.714.725.736.758.791.802.846.857.868.879.890.901.945.956.958, ptr null, i32 0, i32 8, i32 undef
br label %while.cond br label %while.cond
Show All 18 Lines
if.then70: ; preds = %while.body, %while.body, %while.body, %while.body, %while.body if.then70: ; preds = %while.body, %while.body, %while.body, %while.body, %while.body
unreachable unreachable
if.then93: ; preds = %while.body if.then93: ; preds = %while.body
unreachable unreachable
if.then195: ; preds = %while.body if.then195: ; preds = %while.body
br i1 undef, label %if.end274, label %if.then202 br i1 %c2, label %if.end274, label %if.then202
if.then202: ; preds = %if.then195 if.then202: ; preds = %if.then195
br label %while.body222 br label %while.body222
while.body222: ; preds = %while.body222, %if.then202 while.body222: ; preds = %while.body222, %if.then202
br i1 undef, label %if.end240, label %while.body222 br i1 %c3, label %if.end240, label %while.body222
if.end240: ; preds = %while.body222 if.end240: ; preds = %while.body222
%_p_vec_full100 = load <2 x i8>, ptr undef, align 8 %_p_vec_full100 = load <2 x i8>, ptr undef, align 8
br label %if.end274 br label %if.end274
if.end274: ; preds = %if.end240, %if.then195 if.end274: ; preds = %if.end240, %if.then195
%gre_chksum.1 = phi <2 x i8> [ %gre_chksum.0, %if.then195 ], [ %_p_vec_full100, %if.end240 ] %gre_chksum.1 = phi <2 x i8> [ %gre_chksum.0, %if.then195 ], [ %_p_vec_full100, %if.end240 ]
br label %if.end419 br label %if.end419
if.end419: ; preds = %if.end274, %while.body if.end419: ; preds = %if.end274, %while.body
%gre_chksum.2 = phi <2 x i8> [ %gre_chksum.0, %while.body ], [ %gre_chksum.1, %if.end274 ] %gre_chksum.2 = phi <2 x i8> [ %gre_chksum.0, %while.body ], [ %gre_chksum.1, %if.end274 ]
br label %while.cond br label %while.cond
while.end422: ; preds = %while.cond while.end422: ; preds = %while.cond
ret void ret void
} }

llvm/test/CodeGen/Hexagon/vect/vect-store-v2i16.ll

; RUN: llc -march=hexagon < %s ; RUN: llc -march=hexagon < %s
; Used to fail with: "Cannot select: 0x3bab680: ch = store <ST4[%lsr.iv522525], trunc to v2i16> ; Used to fail with: "Cannot select: 0x3bab680: ch = store <ST4[%lsr.iv522525], trunc to v2i16>
; ModuleID = 'bugpoint-reduced-simplified.bc' ; ModuleID = 'bugpoint-reduced-simplified.bc'
target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32" target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32"
target triple = "hexagon-unknown-linux-gnu" target triple = "hexagon-unknown-linux-gnu"
define void @foobar() nounwind { define void @foobar(i1 %c0, i1 %c1, i1 %c2, i1 %c3) nounwind {
entry: entry:
br label %for.cond7.preheader.single_entry.i br label %for.cond7.preheader.single_entry.i
for.cond7.preheader.single_entry.i: ; preds = %for.cond7.preheader.single_entry.i, %entry for.cond7.preheader.single_entry.i: ; preds = %for.cond7.preheader.single_entry.i, %entry
%exitcond72.i = icmp eq i32 undef, 64 %exitcond72.i = icmp eq i32 undef, 64
br i1 %exitcond72.i, label %foo_32.exit, label %for.cond7.preheader.single_entry.i br i1 %exitcond72.i, label %foo_32.exit, label %for.cond7.preheader.single_entry.i
foo_32.exit: ; preds = %for.cond7.preheader.single_entry.i foo_32.exit: ; preds = %for.cond7.preheader.single_entry.i
br label %for.body.i428 br label %for.body.i428
for.body.i428: ; preds = %for.body.i428, %foo_32.exit for.body.i428: ; preds = %for.body.i428, %foo_32.exit
br i1 undef, label %foo_12.exit, label %for.body.i428 br i1 %c0, label %foo_12.exit, label %for.body.i428
foo_12.exit: ; preds = %for.body.i428 foo_12.exit: ; preds = %for.body.i428
br label %for.body.i.i br label %for.body.i.i
for.body.i.i: ; preds = %for.body.i.i, %foo_12.exit for.body.i.i: ; preds = %for.body.i.i, %foo_12.exit
br i1 undef, label %foo_14.exit, label %for.body.i.i br i1 %c1, label %foo_14.exit, label %for.body.i.i
foo_14.exit: ; preds = %for.body.i.i foo_14.exit: ; preds = %for.body.i.i
br label %for.body br label %for.body
for.body: ; preds = %for.body, %foo_14.exit for.body: ; preds = %for.body, %foo_14.exit
br i1 undef, label %for.end, label %for.body br i1 %c2, label %for.end, label %for.body
for.end: ; preds = %for.body for.end: ; preds = %for.body
%storemerge294 = select i1 undef, i32 32767, i32 undef %storemerge294 = select i1 undef, i32 32767, i32 undef
%_p_splat_one386 = insertelement <1 x i32> undef, i32 %storemerge294, i32 0 %_p_splat_one386 = insertelement <1 x i32> undef, i32 %storemerge294, i32 0
%_p_splat387 = shufflevector <1 x i32> %_p_splat_one386, <1 x i32> undef, <2 x i32> zeroinitializer %_p_splat387 = shufflevector <1 x i32> %_p_splat_one386, <1 x i32> undef, <2 x i32> zeroinitializer
br label %polly.loop_body377 br label %polly.loop_body377
polly.loop_after378: ; preds = %polly.loop_body377 polly.loop_after378: ; preds = %polly.loop_body377
unreachable unreachable
polly.loop_body377: ; preds = %polly.loop_body377, %for.end polly.loop_body377: ; preds = %polly.loop_body377, %for.end
%_p_vec_full384 = load <2 x i16>, ptr undef, align 4 %_p_vec_full384 = load <2 x i16>, ptr undef, align 4
%0 = sext <2 x i16> %_p_vec_full384 to <2 x i32> %0 = sext <2 x i16> %_p_vec_full384 to <2 x i32>
%mulp_vec = mul <2 x i32> %0, %_p_splat387 %mulp_vec = mul <2 x i32> %0, %_p_splat387
%shr100293p_vec = lshr <2 x i32> %mulp_vec, <i32 15, i32 15> %shr100293p_vec = lshr <2 x i32> %mulp_vec, <i32 15, i32 15>
%1 = trunc <2 x i32> %shr100293p_vec to <2 x i16> %1 = trunc <2 x i32> %shr100293p_vec to <2 x i16>
store <2 x i16> %1, ptr undef, align 4 store <2 x i16> %1, ptr undef, align 4
br i1 undef, label %polly.loop_body377, label %polly.loop_after378 br i1 %c3, label %polly.loop_body377, label %polly.loop_after378
} }

llvm/test/CodeGen/Hexagon/vect/vect-truncate.ll

; RUN: llc -march=hexagon < %s ; RUN: llc -march=hexagon < %s
; Used to fail with "Cannot select: 0x16cb7f0: v2i16 = truncate" ; Used to fail with "Cannot select: 0x16cb7f0: v2i16 = truncate"
; ModuleID = 'bugpoint-reduced-simplified.bc' ; ModuleID = 'bugpoint-reduced-simplified.bc'
target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32" target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32"
target triple = "hexagon-unknown-linux-gnu" target triple = "hexagon-unknown-linux-gnu"
define void @Autocorr() nounwind { define void @Autocorr(i1 %c0, i1 %c1, i1 %c2) nounwind {
entry: entry:
br label %for.body br label %for.body
for.body: ; preds = %for.body, %entry for.body: ; preds = %for.body, %entry
br i1 undef, label %polly.loop_header43, label %for.body br i1 %c0, label %polly.loop_header43, label %for.body
do.cond: ; preds = %polly.loop_header do.cond: ; preds = %polly.loop_header
unreachable unreachable
do.end: ; preds = %polly.loop_after45 do.end: ; preds = %polly.loop_after45
ret void ret void
polly.loop_header: ; preds = %polly.loop_after45, %polly.loop_body polly.loop_header: ; preds = %polly.loop_after45, %polly.loop_body
%0 = icmp sle i32 undef, 239 %0 = icmp sle i32 undef, 239
br i1 %0, label %polly.loop_body, label %do.cond br i1 %0, label %polly.loop_body, label %do.cond
polly.loop_body: ; preds = %polly.loop_header polly.loop_body: ; preds = %polly.loop_header
%p_25 = call i32 @llvm.hexagon.A2.asrh(i32 undef) %p_25 = call i32 @llvm.hexagon.A2.asrh(i32 undef)
%1 = insertelement <4 x i32> undef, i32 %p_25, i32 3 %1 = insertelement <4 x i32> undef, i32 %p_25, i32 3
%2 = trunc <4 x i32> %1 to <4 x i16> %2 = trunc <4 x i32> %1 to <4 x i16>
store <4 x i16> %2, ptr undef, align 8 store <4 x i16> %2, ptr undef, align 8
br label %polly.loop_header br label %polly.loop_header
polly.loop_after45: ; preds = %polly.loop_header43 polly.loop_after45: ; preds = %polly.loop_header43
br i1 undef, label %polly.loop_header, label %do.end br i1 %c1, label %polly.loop_header, label %do.end
polly.loop_header43: ; preds = %polly.loop_body44, %for.body polly.loop_header43: ; preds = %polly.loop_body44, %for.body
br i1 undef, label %polly.loop_body44, label %polly.loop_after45 br i1 %c2, label %polly.loop_body44, label %polly.loop_after45
polly.loop_body44: ; preds = %polly.loop_header43 polly.loop_body44: ; preds = %polly.loop_header43
br label %polly.loop_header43 br label %polly.loop_header43
} }
declare i32 @llvm.hexagon.A2.asrh(i32) nounwind readnone declare i32 @llvm.hexagon.A2.asrh(i32) nounwind readnone

llvm/test/CodeGen/Hexagon/vect/vect-zeroextend.ll

; RUN: llc -march=hexagon < %s ; RUN: llc -march=hexagon < %s
; Used to fail with "Cannot select: 0x16cb2d0: v4i16 = zero_extend" ; Used to fail with "Cannot select: 0x16cb2d0: v4i16 = zero_extend"
; ModuleID = 'bugpoint-reduced-simplified.bc' ; ModuleID = 'bugpoint-reduced-simplified.bc'
target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32" target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32"
target triple = "hexagon-unknown-linux-gnu" target triple = "hexagon-unknown-linux-gnu"
define void @foo() nounwind { define void @foo(i1 %c0) nounwind {
entry: entry:
br i1 undef, label %for.cond30.preheader.lr.ph, label %for.end425 br i1 %c0, label %for.cond30.preheader.lr.ph, label %for.end425
for.cond30.preheader.lr.ph: ; preds = %entry for.cond30.preheader.lr.ph: ; preds = %entry
br label %for.cond37.preheader br label %for.cond37.preheader
for.cond37.preheader: ; preds = %for.cond37.preheader, %for.cond30.preheader.lr.ph for.cond37.preheader: ; preds = %for.cond37.preheader, %for.cond30.preheader.lr.ph
%_p_vec_full = load <3 x i8>, ptr undef, align 8 %_p_vec_full = load <3 x i8>, ptr undef, align 8
%0 = zext <3 x i8> %_p_vec_full to <3 x i16> %0 = zext <3 x i8> %_p_vec_full to <3 x i16>
store <3 x i16> %0, ptr undef, align 8 store <3 x i16> %0, ptr undef, align 8
br label %for.cond37.preheader br label %for.cond37.preheader
for.end425: ; preds = %entry for.end425: ; preds = %entry
ret void ret void
} }

llvm/test/CodeGen/Hexagon/vect/vsplat-v8i8.ll

; RUN: llc -march=hexagon < %s | FileCheck %s ; RUN: llc -march=hexagon < %s | FileCheck %s
; Check that this compiles successfully. Used to crash with "cannot select ; Check that this compiles successfully. Used to crash with "cannot select
; v8i8 = vsplat ..." ; v8i8 = vsplat ..."
; CHECK: jumpr r31 ; CHECK: jumpr r31
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon" target triple = "hexagon"
; Function Attrs: nounwind ; Function Attrs: nounwind
define i32 @fred() #0 { define i32 @fred(i1 %c0) #0 {
b0: b0:
br label %b1 br label %b1
b1: ; preds = %b1, %b0 b1: ; preds = %b1, %b0
%v2 = xor <16 x i8> undef, undef %v2 = xor <16 x i8> undef, undef
%v3 = icmp eq i32 undef, undef %v3 = icmp eq i32 undef, undef
br i1 %v3, label %b4, label %b1 br i1 %v3, label %b4, label %b1
b4: ; preds = %b1 b4: ; preds = %b1
%v5 = xor <16 x i8> %v2, zeroinitializer %v5 = xor <16 x i8> %v2, zeroinitializer
%v6 = xor <16 x i8> %v5, zeroinitializer %v6 = xor <16 x i8> %v5, zeroinitializer
%v7 = xor <16 x i8> %v6, zeroinitializer %v7 = xor <16 x i8> %v6, zeroinitializer
%v8 = xor <16 x i8> %v7, zeroinitializer %v8 = xor <16 x i8> %v7, zeroinitializer
%v9 = shufflevector <16 x i8> %v8, <16 x i8> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %v9 = shufflevector <16 x i8> %v8, <16 x i8> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%v10 = xor <16 x i8> %v8, %v9 %v10 = xor <16 x i8> %v8, %v9
%v11 = extractelement <16 x i8> %v10, i32 0 %v11 = extractelement <16 x i8> %v10, i32 0
br i1 undef, label %b14, label %b12 br i1 %c0, label %b14, label %b12
b12: ; preds = %b4 b12: ; preds = %b4
%v13 = xor i8 undef, %v11 %v13 = xor i8 undef, %v11
br label %b14 br label %b14
b14: ; preds = %b12, %b4 b14: ; preds = %b12, %b4
%v15 = phi i8 [ %v11, %b4 ], [ %v13, %b12 ] %v15 = phi i8 [ %v11, %b4 ], [ %v13, %b12 ]
%v16 = zext i8 %v15 to i32 %v16 = zext i8 %v15 to i32
ret i32 %v16 ret i32 %v16
} }
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" } attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" }

llvm/test/CodeGen/Hexagon/vselect-pseudo.ll

; RUN: llc -march=hexagon -mattr="+hvxv60,+hvx-length64b" < %s ; RUN: llc -march=hexagon -mattr="+hvxv60,+hvx-length64b" < %s
; REQUIRES: asserts ; REQUIRES: asserts
target triple = "hexagon" target triple = "hexagon"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @fred() #0 { define void @fred(i1 %c0) #0 {
entry: entry:
br label %for.body9.us br label %for.body9.us
for.body9.us: for.body9.us:
%cmp10.us = icmp eq i32 0, undef %cmp10.us = icmp eq i32 0, undef
%.h63h32.2.us = select i1 %cmp10.us, <16 x i32> zeroinitializer, <16 x i32> undef %.h63h32.2.us = select i1 %cmp10.us, <16 x i32> zeroinitializer, <16 x i32> undef
%0 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %.h63h32.2.us, <16 x i32> undef, i32 2) %0 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %.h63h32.2.us, <16 x i32> undef, i32 2)
%1 = tail call <32 x i32> @llvm.hexagon.V6.vswap(<64 x i1> undef, <16 x i32> undef, <16 x i32> %0) %1 = tail call <32 x i32> @llvm.hexagon.V6.vswap(<64 x i1> undef, <16 x i32> undef, <16 x i32> %0)
%2 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %1) %2 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %1)
%3 = tail call <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32> undef, <16 x i32> %2, i32 62) %3 = tail call <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32> undef, <16 x i32> %2, i32 62)
%4 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %3) %4 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %3)
store <16 x i32> %4, ptr undef, align 64 store <16 x i32> %4, ptr undef, align 64
br i1 undef, label %for.body9.us, label %for.body43.us.preheader br i1 %c0, label %for.body9.us, label %for.body43.us.preheader
for.body43.us.preheader: ; preds = %for.body9.us for.body43.us.preheader: ; preds = %for.body9.us
ret void ret void
} }
declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #1 declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #1
declare <32 x i32> @llvm.hexagon.V6.vswap(<64 x i1>, <16 x i32>, <16 x i32>) #1 declare <32 x i32> @llvm.hexagon.V6.vswap(<64 x i1>, <16 x i32>, <16 x i32>) #1
declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
declare <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32>, <16 x i32>, i32) #1 declare <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32>, <16 x i32>, i32) #1
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }