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[mips] Define patterns for the atomic_{load,store}_{8,16,32,64} nodes.
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Authored by vkalintiris on Nov 5 2015, 2:30 PM.

Details

Summary

Without these patterns we would generate a complete LL/SC sequence.
This would be problematic for memory regions marked as WRITE-only or
READ-only, as the instructions LL/SC would read/write to the protected
memory regions correspondingly.

Diff Detail

Event Timeline

vkalintiris updated this revision to Diff 39419.Nov 5 2015, 2:30 PM
vkalintiris retitled this revision from to [mips] Define patterns for the atomic_{load,store}_{8,16,32,64} nodes..
vkalintiris updated this object.
vkalintiris added a reviewer: dsanders.
vkalintiris added a subscriber: llvm-commits.
dsanders accepted this revision.Nov 6 2015, 3:43 AM
dsanders edited edge metadata.

LGTM with some minor changes

lib/Target/Mips/MipsISelLowering.cpp
394

This ought to be a check for N32/N64 but I'm planning to change the predicate itself later so no need to change this now.

lib/Target/Mips/MipsInstrInfo.td
2087–2092

The multiclass doesn't provide a noticeable benefit here. It's just distributing the RC argument. I'd prefer loads/stores to be defined separately.

test/CodeGen/Mips/atomic-load-store.ll
1

(filename): This kind of minimal single-statement test is what I had in mind when creating the test/CodeGen/Mips/llvm-ir directory. Could you split the load/stores into test/CodeGen/Mips/llvm-ir/{store,load}-atomic.ll

test/CodeGen/Mips/atomicSCr6.ll
1

(filename): Similarly here but with atomicrmx.ll

Thanks for tidying this test.

This revision is now accepted and ready to land.Nov 6 2015, 3:43 AM
This revision was automatically updated to reflect the committed changes.
vkalintiris marked 3 inline comments as done.

This bug is resolved in rL252293. In detail it is explained in comment: https://dmz-portal.mips.com/bugz/show_bug.cgi?id=2231