Add Printable class to simplify the construction of Print helpers.

[MatzeB]

Summary

Printable objects simply hold a function reference to a function that
does the printing. It allows the construction of Print helpers.

This would also be a good base to transform several MyClass::print(raw_ostream &OS, more arguments); function in llvm to a more C++-style interface (though I do not plan to do this refactoring myself at the moment).

Example:

Printable PrintLaneMask(unsigned LaneMask) {
  return Printable([LaneMask](raw_ostream &OS) {
    OS << format("%08X", LaneMask);
  });
}

// Usage:
OS << PrintLaneMask(Mask);

[MatzeB]

ping

[MatzeB]

ping2.

Adding some reviewers that might care about the printers here or proper C++ usage.

[dblaikie]

Perhaps we could skip the Printable type and make this more like IO manipulators in the standard streams ( http://www.cplusplus.com/reference/ostream/ostream/operator%3C%3C/ )

Which is to say, add a "operator<<(std::function<void(raw_ostream&)>)" to raw_ostream, and it just calls it on itself.

Seem reasonable?

[MatzeB]

Updated version which uses std::function<void(raw_ostream&)> similar to C++ IO manipulators directly instead of adding a pointless shim class around the std::function.
I still found the code slightly easier to read when giving the concept an explicit name with "typedef std::function<void(raw_ostream&)> Printable", though I have no strong opinion here and can change that if you prefer the plain form without typedef.

[dblaikie]

Seems good to me

Don't mind the typedef one way or another terribly much (I usually err towards not typedef'ing relatively obvious/clear things, so the code is less opaque, but it seems OK-ish here)

[MatzeB]

I had to revert this patch because two gcc buildbots and all the msvc bots choke on ambiguous operator<< overloads. Examples:

http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-autoconf/builds/12622/steps/build%20fresh%20clang/logs/stdio
http://lab.llvm.org:8011/builders/polly-amd64-linux/builds/36852/steps/build_polly/logs/stdio
http://lab.llvm.org:8011/builders/lld-x86_64-win7/builds/27400/steps/build_Lld/logs/stdio

My current guess is that std::function implicitely converts to void* or void* implicitely converts to std::function on these systems. So I guess to get this working I have to go back to the shim class after all :-(

llvm/trunk/include/llvm/Support/raw_ostream.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_SUPPORT_RAW_OSTREAM_H
 #define LLVM_SUPPORT_RAW_OSTREAM_H
 
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/Support/DataTypes.h"
+#include <functional>
 #include <system_error>
 
 namespace llvm {
 class format_object_base;
 class FormattedString;
 class FormattedNumber;
+class raw_ostream;
 template <typename T> class SmallVectorImpl;
 
 namespace sys {
 namespace fs {
 enum OpenFlags : unsigned;
 }
 }
 
+/// Type of function that prints to raw_ostream.
+///
+/// Typical usage:
+///     Printable PrintFoo(Foo x) {
+///       return [] (raw_ostream &os) { os << /* ... */; };
+///     }
+///     os << "Foo: " << PrintFoo(foo) << '\n';
+typedef std::function<void(raw_ostream&)> Printable;
+
 /// This class implements an extremely fast bulk output stream that can *only*
 /// output to a stream.  It does not support seeking, reopening, rewinding, line
 /// buffered disciplines etc. It is a simple buffer that outputs
 /// a chunk at a time.
 class raw_ostream {
 private:
   void operator=(const raw_ostream &) = delete;
   raw_ostream(const raw_ostream &) = delete;
public:
   }
 
   raw_ostream &operator<<(int N) {
     return this->operator<<(static_cast<long>(N));
   }
 
   raw_ostream &operator<<(double N);
 
+  /// IO manipulator, \see Printable.
+  raw_ostream &operator<<(Printable P);
+
   /// Output \p N in hexadecimal, without any prefix or padding.
   raw_ostream &write_hex(unsigned long long N);
 
   /// Output \p Str, turning '\\', '\t', '\n', '"', and anything that doesn't
   /// satisfy std::isprint into an escape sequence.
   raw_ostream &write_escaped(StringRef Str, bool UseHexEscapes = false);
 
   raw_ostream &write(unsigned char C);

llvm/trunk/include/llvm/Target/TargetRegisterInfo.h

 
 // This is useful when building IndexedMaps keyed on virtual registers
 struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> {
   unsigned operator()(unsigned Reg) const {
     return TargetRegisterInfo::virtReg2Index(Reg);
   }
 };
 
-/// Helper class for printing registers on a raw_ostream.
 /// Prints virtual and physical registers with or without a TRI instance.
 ///
 /// The format is:
 ///   %noreg          - NoRegister
 ///   %vreg5          - a virtual register.
 ///   %vreg5:sub_8bit - a virtual register with sub-register index (with TRI).
 ///   %EAX            - a physical register
 ///   %physreg17      - a physical register when no TRI instance given.
 ///
 /// Usage: OS << PrintReg(Reg, TRI) << '\n';
-///
-class PrintReg {
-  const TargetRegisterInfo *TRI;
-  unsigned Reg;
-  unsigned SubIdx;
-public:
-  explicit PrintReg(unsigned reg, const TargetRegisterInfo *tri = nullptr,
-                    unsigned subidx = 0)
-    : TRI(tri), Reg(reg), SubIdx(subidx) {}
-  void print(raw_ostream&) const;
-};
+Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI = nullptr,
+                   unsigned SubRegIdx = 0);
 
-static inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) {
-  PR.print(OS);
-  return OS;
-}
-
-/// Helper class for printing register units on a raw_ostream.
+/// Create Printable object to print register units on a \ref raw_ostream.
 ///
 /// Register units are named after their root registers:
 ///
 ///   AL      - Single root.
 ///   FP0~ST7 - Dual roots.
 ///
 /// Usage: OS << PrintRegUnit(Unit, TRI) << '\n';
-///
-class PrintRegUnit {
-protected:
-  const TargetRegisterInfo *TRI;
-  unsigned Unit;
-public:
-  PrintRegUnit(unsigned unit, const TargetRegisterInfo *tri)
-    : TRI(tri), Unit(unit) {}
-  void print(raw_ostream&) const;
-};
+Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI);
 
-static inline raw_ostream &operator<<(raw_ostream &OS, const PrintRegUnit &PR) {
-  PR.print(OS);
-  return OS;
-}
+/// \brief Create Printable object to print virtual registers and physical
+/// registers on a \ref raw_ostream.
+Printable PrintVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI);
 
-/// It is often convenient to track virtual registers and
-/// physical register units in the same list.
-class PrintVRegOrUnit : protected PrintRegUnit {
-public:
-  PrintVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *tri)
-    : PrintRegUnit(VRegOrUnit, tri) {}
-  void print(raw_ostream&) const;
-};
-
-static inline raw_ostream &operator<<(raw_ostream &OS,
-                                      const PrintVRegOrUnit &PR) {
-  PR.print(OS);
-  return OS;
-}
-
-/// Helper class for printing lane masks.
-///
-/// They are currently printed out as hexadecimal numbers.
-/// Usage: OS << PrintLaneMask(Mask);
-class PrintLaneMask {
-protected:
-  LaneBitmask LaneMask;
-public:
-  PrintLaneMask(LaneBitmask LaneMask)
-    : LaneMask(LaneMask) {}
-  void print(raw_ostream&) const;
-};
-
-static inline raw_ostream &operator<<(raw_ostream &OS, const PrintLaneMask &P) {
-  P.print(OS);
-  return OS;
-}
+/// Create Printable object to print LaneBitmasks on a \ref raw_ostream.
+Printable PrintLaneMask(LaneBitmask LaneMask);
 
 } // End llvm namespace
 
 #endif

llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp

#endif
   VRegsToAlloc.clear();
   EmptyIntervalVRegs.clear();
 
   DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << VRM << "\n");
 
   return true;
 }
 
-namespace {
-// A helper class for printing node and register info in a consistent way
-class PrintNodeInfo {
-public:
-  typedef PBQP::RegAlloc::PBQPRAGraph Graph;
-  typedef PBQP::RegAlloc::PBQPRAGraph::NodeId NodeId;
-
-  PrintNodeInfo(NodeId NId, const Graph &G) : G(G), NId(NId) {}
-
-  void print(raw_ostream &OS) const {
+/// Create Printable object for node and register info.
+static Printable PrintNodeInfo(PBQP::RegAlloc::PBQPRAGraph::NodeId NId,
+                               const PBQP::RegAlloc::PBQPRAGraph &G) {
+  return [NId, &G](raw_ostream &OS) {
     const MachineRegisterInfo &MRI = G.getMetadata().MF.getRegInfo();
     const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
     unsigned VReg = G.getNodeMetadata(NId).getVReg();
     const char *RegClassName = TRI->getRegClassName(MRI.getRegClass(VReg));
     OS << NId << " (" << RegClassName << ':' << PrintReg(VReg, TRI) << ')';
-  }
-
-private:
-  const Graph &G;
-  NodeId NId;
   };
-
-inline raw_ostream &operator<<(raw_ostream &OS, const PrintNodeInfo &PR) {
-  PR.print(OS);
-  return OS;
 }
-} // anonymous namespace
 
 void PBQP::RegAlloc::PBQPRAGraph::dump(raw_ostream &OS) const {
   for (auto NId : nodeIds()) {
     const Vector &Costs = getNodeCosts(NId);
     assert(Costs.getLength() != 0 && "Empty vector in graph.");
     OS << PrintNodeInfo(NId, *this) << ": " << Costs << '\n';
   }
   OS << '\n';

llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) {
   default:              return "";
   case ISD::PRE_INC:    return "<pre-inc>";
   case ISD::PRE_DEC:    return "<pre-dec>";
   case ISD::POST_INC:   return "<post-inc>";
   case ISD::POST_DEC:   return "<post-dec>";
   }
 }
 
-namespace {
-class PrintNodeId {
-  const SDNode &Node;
-public:
-  explicit PrintNodeId(const SDNode &Node)
-      : Node(Node) {}
-  void print(raw_ostream &OS) const {
+static Printable PrintNodeId(const SDNode &Node) {
+  return [&Node](raw_ostream &OS) {
 #ifndef NDEBUG
     OS << 't' << Node.PersistentId;
 #else
     OS << (const void*)&Node;
 #endif
-  }
   };
-
-static inline raw_ostream &operator<<(raw_ostream &OS, const PrintNodeId &P) {
-  P.print(OS);
-  return OS;
-}
 }
 
 void SDNode::dump() const { dump(nullptr); }
 void SDNode::dump(const SelectionDAG *G) const {
   print(dbgs(), G);
   dbgs() << '\n';
 }
 

llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp

TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
   : InfoDesc(ID), SubRegIndexNames(SRINames),
     SubRegIndexLaneMasks(SRILaneMasks),
     RegClassBegin(RCB), RegClassEnd(RCE),
     CoveringLanes(SRICoveringLanes) {
 }
 
 TargetRegisterInfo::~TargetRegisterInfo() {}
 
-void PrintReg::print(raw_ostream &OS) const {
+namespace llvm {
+
+Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI,
+                   unsigned SubIdx) {
+  return [Reg, TRI, SubIdx](raw_ostream &OS) {
     if (!Reg)
       OS << "%noreg";
     else if (TargetRegisterInfo::isStackSlot(Reg))
       OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
     else if (TargetRegisterInfo::isVirtualRegister(Reg))
       OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg);
     else if (TRI && Reg < TRI->getNumRegs())
       OS << '%' << TRI->getName(Reg);
     else
       OS << "%physreg" << Reg;
     if (SubIdx) {
       if (TRI)
         OS << ':' << TRI->getSubRegIndexName(SubIdx);
       else
         OS << ":sub(" << SubIdx << ')';
     }
+  };
 }
 
-void PrintRegUnit::print(raw_ostream &OS) const {
+Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
+  return [Unit, TRI](raw_ostream &OS) {
     // Generic printout when TRI is missing.
     if (!TRI) {
       OS << "Unit~" << Unit;
       return;
     }
 
     // Check for invalid register units.
     if (Unit >= TRI->getNumRegUnits()) {
       OS << "BadUnit~" << Unit;
       return;
     }
 
     // Normal units have at least one root.
     MCRegUnitRootIterator Roots(Unit, TRI);
     assert(Roots.isValid() && "Unit has no roots.");
     OS << TRI->getName(*Roots);
     for (++Roots; Roots.isValid(); ++Roots)
       OS << '~' << TRI->getName(*Roots);
+  };
 }
 
-void PrintVRegOrUnit::print(raw_ostream &OS) const {
+Printable PrintVRegOrUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
+  return [Unit, TRI](raw_ostream &OS) {
     if (TRI && TRI->isVirtualRegister(Unit)) {
       OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Unit);
-    return;
+    } else {
+      OS << PrintRegUnit(Unit, TRI);
     }
-  PrintRegUnit::print(OS);
+  };
 }
 
-void PrintLaneMask::print(raw_ostream &OS) const {
+Printable PrintLaneMask(LaneBitmask LaneMask) {
+  return [LaneMask](raw_ostream &OS) {
     OS << format("%08X", LaneMask);
+  };
 }
 
+} // End of llvm namespace
+
 /// getAllocatableClass - Return the maximal subclass of the given register
 /// class that is alloctable, or NULL.
 const TargetRegisterClass *
 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
   if (!RC || RC->isAllocatable())
     return RC;
 
   const unsigned *SubClass = RC->getSubClassMask();

llvm/trunk/lib/Support/raw_ostream.cpp

if (len >= 5 && buf[len - 5] == 'e' && buf[len - 3] == '0') {
       }
     }
     return this->operator<<(buf);
   }
 #endif
   return this->operator<<(format("%e", N));
 }
 
+raw_ostream &raw_ostream::operator<<(Printable P) {
+  P(*this);
+  return *this;
+}
 
 
 void raw_ostream::flush_nonempty() {
   assert(OutBufCur > OutBufStart && "Invalid call to flush_nonempty.");
   size_t Length = OutBufCur - OutBufStart;
   OutBufCur = OutBufStart;
   write_impl(OutBufStart, Length);
 }