AMDGPU/SI: Emit relocations for constant arrays when targeting HSA

[arsenm]

lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

106

You should be able to get the Triple object from the TargetMachine with TM.getTargetTriple()

lib/Target/AMDGPU/AMDGPUMCInstLower.cpp

46–49

returns on separate lines

lib/Target/AMDGPU/SIISelLowering.cpp

35–36

Out of alphabetical order

975–976

A comment about how globals are handled in HSA vs. not would be helpful

lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

 //===----------------------------------------------------------------------===//
 //
 
 #include "AMDGPUAsmPrinter.h"
 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
 #include "InstPrinter/AMDGPUInstPrinter.h"
 #include "Utils/AMDGPUBaseInfo.h"
 #include "AMDGPU.h"
+#include "AMDGPUHSATargetObjectFile.h"
 #include "AMDKernelCodeT.h"
 #include "AMDGPUSubtarget.h"
 #include "R600Defines.h"
 #include "R600MachineFunctionInfo.h"
 #include "R600RegisterInfo.h"
 #include "SIDefines.h"
 #include "SIMachineFunctionInfo.h"
 #include "SIRegisterInfo.h"
void AMDGPUAsmPrinter::EmitFunctionBodyStart() {
   if (STM.isAmdHsaOS()) {
     getSIProgramInfo(KernelInfo, *MF);
     EmitAmdKernelCodeT(*MF, KernelInfo);
   }
 }
 
 void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) {
 
+  if (Triple(M.getTargetTriple()).getOS() != Triple::AMDHSA) {
     // This label is used to mark the end of the .text section.
     const TargetLoweringObjectFile &TLOF = getObjFileLowering();
     OutStreamer->SwitchSection(TLOF.getTextSection());
     MCSymbol *EndOfTextLabel =
         OutContext.getOrCreateSymbol(StringRef(END_OF_TEXT_LABEL_NAME));
     OutStreamer->EmitLabel(EndOfTextLabel);
   }
+}
 
 void AMDGPUAsmPrinter::EmitFunctionEntryLabel() {
   const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
   if (MFI->isKernel() && STM.isAmdHsaOS()) {
     AMDGPUTargetStreamer *TS =
         static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
     TS->EmitAMDGPUSymbolType(CurrentFnSym->getName(),

lib/Target/AMDGPU/AMDGPUMCInstLower.cpp

 #include "llvm/IR/Function.h"
 #include "llvm/IR/GlobalVariable.h"
 #include "llvm/MC/MCCodeEmitter.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCObjectStreamer.h"
 #include "llvm/MC/MCStreamer.h"
+#include "llvm/Support/ELF.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/Format.h"
 #include <algorithm>
 
 using namespace llvm;
 
 AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx, const AMDGPUSubtarget &st):
   Ctx(ctx), ST(st)
 { }
 
+static MCSymbolRefExpr::VariantKind getVariantKind(unsigned RT) {
+  switch (RT) {
+  default: return MCSymbolRefExpr::VK_None;
+  case ELF::R_AMDGPU_32_LO: return MCSymbolRefExpr::VK_AMDGPU_32_LO;
+  case ELF::R_AMDGPU_32_HI: return MCSymbolRefExpr::VK_AMDGPU_32_HI;
+  case ELF::R_AMDGPU_64:    return MCSymbolRefExpr::VK_AMDGPU_64;
+  case ELF::R_AMDGPU_INIT_SAMPLER:
+    return MCSymbolRefExpr::VK_AMDGPU_INIT_SAMPLER;
+  case ELF::R_AMDGPU_INIT_IMAGE:
+    return MCSymbolRefExpr::VK_AMDGPU_INIT_IMAGE;
+  }
+}
+
 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
 
   int MCOpcode = ST.getInstrInfo()->pseudoToMCOpcode(MI->getOpcode());
 
   if (MCOpcode == -1) {
     LLVMContext &C = MI->getParent()->getParent()->getFunction()->getContext();
     C.emitError("AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "
                 "a target-specific version: " + Twine(MI->getOpcode()));
case MachineOperand::MO_Register:
       break;
     case MachineOperand::MO_MachineBasicBlock:
       MCOp = MCOperand::createExpr(MCSymbolRefExpr::create(
                                    MO.getMBB()->getSymbol(), Ctx));
       break;
     case MachineOperand::MO_GlobalAddress: {
       const GlobalValue *GV = MO.getGlobal();
       MCSymbol *Sym = Ctx.getOrCreateSymbol(StringRef(GV->getName()));
-      MCOp = MCOperand::createExpr(MCSymbolRefExpr::create(Sym, Ctx));
+      MCOp = MCOperand::createExpr(MCSymbolRefExpr::create(Sym,
+                                   getVariantKind(MO.getTargetFlags()), Ctx));
       break;
     }
     case MachineOperand::MO_TargetIndex: {
       assert(MO.getIndex() == AMDGPU::TI_CONSTDATA_START);
       MCSymbol *Sym = Ctx.getOrCreateSymbol(StringRef(END_OF_TEXT_LABEL_NAME));
       const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(Sym, Ctx);
       MCOp = MCOperand::createExpr(Expr);
       break;

lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp

case FK_Data_1:
     return 1;
   case FK_Data_2:
     return 2;
   case FK_Data_4:
     return 4;
   case FK_Data_8:
     return 8;
   default:
-    llvm_unreachable("Unknown fixup kind!");
+    return 0;
   }
 }
 
 void AMDGPUAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
                                   unsigned DataSize, uint64_t Value,
                                   bool IsPCRel) const {
 
   switch ((unsigned)Fixup.getKind()) {

lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp

 //===-- AMDGPUELFObjectWriter.cpp - AMDGPU ELF Writer ----------------------==//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 /// \file
 //===----------------------------------------------------------------------===//
 
 #include "AMDGPUMCTargetDesc.h"
+#include "AMDGPU.h"
+#include "AMDGPUFixupKinds.h"
 #include "llvm/MC/MCELFObjectWriter.h"
 #include "llvm/MC/MCFixup.h"
 
 using namespace llvm;
 
 namespace {
 
 class AMDGPUELFObjectWriter : public MCELFObjectTargetWriter {
 public:
   AMDGPUELFObjectWriter(bool Is64Bit);
+  virtual bool needsRelocateWithSymbol(const MCSymbol &Sym,
+                                       unsigned Type) const override {
+    switch (Type) {
+    default: return false;
+    case ELF::R_AMDGPU_32_LO:
+    case ELF::R_AMDGPU_32_HI: return true;
+    }
+  }
 protected:
   unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup,
                         bool IsPCRel) const override {
-    return Fixup.getKind();
+    switch ((unsigned)Fixup.getKind()) {
+      default:  return Fixup.getKind();
+      case AMDGPU::fixup_amdgpu_lo32: return ELF::R_AMDGPU_32_LO;
+      case AMDGPU::fixup_amdgpu_hi32: return ELF::R_AMDGPU_32_HI;
+    }
   }
-
 };
 
 
 } // End anonymous namespace
 
 AMDGPUELFObjectWriter::AMDGPUELFObjectWriter(bool Is64Bit)
   : MCELFObjectTargetWriter(Is64Bit, ELF::ELFOSABI_AMDGPU_HSA,
                             ELF::EM_AMDGPU, false) { }
 
 MCObjectWriter *llvm::createAMDGPUELFObjectWriter(bool Is64Bit, raw_pwrite_stream &OS) {
   MCELFObjectTargetWriter *MOTW = new AMDGPUELFObjectWriter(Is64Bit);
   return createELFObjectWriter(MOTW, OS, true);
 }

lib/Target/AMDGPU/MCTargetDesc/AMDGPUFixupKinds.h

enum Fixups {
   fixup_si_sopp_br = FirstTargetFixupKind,
 
   /// fixup for global addresses with constant initializers
   fixup_si_rodata,
 
   /// fixup for offset from instruction to end of text section
   fixup_si_end_of_text,
 
+  fixup_amdgpu_lo32,
+  fixup_amdgpu_hi32,
+
   // Marker
   LastTargetFixupKind,
   NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
 };
 }
 }
 
 #endif

lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp

if (MO.isReg())
     return MRI.getEncodingValue(MO.getReg());
 
   if (MO.isExpr()) {
     const MCSymbolRefExpr *Expr = cast<MCSymbolRefExpr>(MO.getExpr());
     MCFixupKind Kind;
     const MCSymbol *Sym =
         Ctx.getOrCreateSymbol(StringRef(END_OF_TEXT_LABEL_NAME));
 
+    switch (Expr->getKind()) {
+      case MCSymbolRefExpr::VK_AMDGPU_32_LO:
+        Kind = (MCFixupKind)AMDGPU::fixup_amdgpu_lo32;
+        break;
+      case MCSymbolRefExpr::VK_AMDGPU_32_HI:
+        Kind = (MCFixupKind)AMDGPU::fixup_amdgpu_hi32;
+        break;
+      default:
         if (&Expr->getSymbol() == Sym) {
           // Add the offset to the beginning of the constant values.
           Kind = (MCFixupKind)AMDGPU::fixup_si_end_of_text;
         } else {
           // This is used for constant data stored in .rodata.
          Kind = (MCFixupKind)AMDGPU::fixup_si_rodata;
         }
+      }
     Fixups.push_back(MCFixup::create(4, Expr, Kind, MI.getLoc()));
   }
 
   // Figure out the operand number, needed for isSrcOperand check
   unsigned OpNo = 0;
   for (unsigned e = MI.getNumOperands(); OpNo < e; ++OpNo) {
     if (&MO == &MI.getOperand(OpNo))
       break;

lib/Target/AMDGPU/SIISelLowering.cpp

 #include "SIMachineFunctionInfo.h"
 #include "SIRegisterInfo.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/CodeGen/CallingConvLower.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/IR/Function.h"
+#include "llvm/Support/ELF.h"
 #include "llvm/ADT/SmallString.h"
 
 using namespace llvm;
 
 SITargetLowering::SITargetLowering(TargetMachine &TM,
                                    const AMDGPUSubtarget &STI)
     : AMDGPUTargetLowering(TM, STI) {
   addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
   addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);

 SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
                                              SDValue Op,
                                              SelectionDAG &DAG) const {
   GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Op);
 
   if (GSD->getAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
     return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG);
 
-  SDLoc DL(GSD);
   const GlobalValue *GV = GSD->getGlobal();
+  SDLoc DL(GSD);
+
+  if (Subtarget->isAmdHsaOS()) {
+    SDValue Lo = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, GSD->getOffset(),
+                                            ELF::R_AMDGPU_32_LO);
+    SDValue Hi = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, GSD->getOffset(),
+                                            ELF::R_AMDGPU_32_HI);
+
+    // We need to insert S_MOV_B32 nodes, because the InstEmitter will crash
+    // if a global address ends up in a target independent node.
+    Lo = SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, Lo), 0);
+    Hi = SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, Hi), 0);
+    return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
+  }
+
   MVT PtrVT = getPointerTy(DAG.getDataLayout(), GSD->getAddressSpace());
 
   SDValue Ptr = DAG.getNode(AMDGPUISD::CONST_DATA_PTR, DL, PtrVT);
   SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32);
 
   SDValue PtrLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Ptr,
                               DAG.getConstant(0, DL, MVT::i32));
   SDValue PtrHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Ptr,

test/CodeGen/AMDGPU/hsa-globals.ll

 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | FileCheck --check-prefix=HSA-CI --check-prefix=HSA %s
 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo | FileCheck --check-prefix=HSA-VI --check-prefix=HSA %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -filetype=obj  | llvm-readobj -symbols -s -sd | FileCheck --check-prefix=ELF %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -filetype=obj  | llvm-readobj -symbols -s -sd -relocations | FileCheck --check-prefix=ELF %s
 
-; FIXME: Add assembler support for globals
-; FIXME-XUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri | llvm-readobj -symbols -s -sd | FileCheck %s --check-prefix=ELF
+; FIXME: Add assembler support for globals and relocations
+; FIXME-XUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri | llvm-readobj -symbols -s -sd -relocations | FileCheck %s --check-prefix=ELF
 
 @const_array = internal unnamed_addr addrspace(2) constant [64 x i8] c"abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789<>", align 1
 
 ; ELF: Section {
 ; ELF: Name: .hsarodata_readonly_agent
 ; ELF: Type: SHT_PROGBITS (0x1)
 ; ELF: Flags [ (0xA00002)
 ; ELF: SHF_ALLOC (0x2)
 ; ELF: SHF_AMDGPU_HSA_AGENT (0x800000)
 ; ELF: SHF_AMDGPU_HSA_READONLY (0x200000)
 ; ELF: ]
 
+; ELF: Relocations [
+; ELF: Section ({{[0-9]+}}) .rel.hsatext {
+; ELF-DAG: R_AMDGPU_32_LO const_array
+; ELF-DAG: R_AMDGPU_32_HI const_array
+; ELF: }
+
 ; ELF: Symbol {
 ; ELF: Name: const_array
 ; ELF: Binding: Local (0x0)
 ; ELF: Type: Object (0x1)
 ; ELF: Section: .hsarodata_readonly_agent (0x6)
 ; ELF: }
 
+; HSA-LABEL: {{^}}test:
+; HSA-DAG: s_mov_b32 s[[LORELOC:[0-9]+]], const_array@LO
+; HSA-DAG: s_mov_b32 s[[HIRELOC:[0-9]+]], const_array@HI
+; HSA-VI: s_add_u32 s[[SPTRLO:[0-9]+]], s[[LORELOC]], s{{[0-9]+}}
+; HSA-VI: s_addc_u32 s[[SPTRHI:[0-9]+]], s[[HIRELOC]], s{{[0-9]+}}
+; HSA-VI-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[SPTRLO]]
+; HSA-VI-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[SPTRHI]]
+; HSA-VI: flat_load_ubyte v{{[0-9]+}}, v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}}
+; HSA-CI: buffer_load_ubyte v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s{{\[}}[[LORELOC]]:{{[0-9]+}}]
+; HSA: s_endpgm
 ; HSA: .amdgpu_hsa_module_global const_array
 ; HSA: .hsarodata_readonly_agent
 ; HSA: const_array:
 ; HSA: .ascii  "abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789<>"
 
-
+; HSA-NOT: EndOfTextLabel
 define void @test(i8 addrspace(1) *%out, i32 %offset) {
 entry:
   %ptr = getelementptr [64 x i8], [64 x i8] addrspace(2)* @const_array, i32 0, i32 %offset
 ;  %0 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(3)* @local_mem, i32 0, i32 %index
   %val = load i8, i8 addrspace(2)* %ptr
   store i8 %val, i8 addrspace(1)* %out
   ret void
 }