[mips] wrong opcode for ll/sc instructions on mipsr6 when -integrated-as is used

[Jelena.Losic]

Summary

This commit resolves wrong opcode of instructions ll and sc for r6 architecutres, which was generated in method MipsTargetLowering::emitAtomicBinary.

[dsanders]

The code change looks correct but the test needs a couple changes.

test/Object/Mips/at.ll

1–2 ↗

(On Diff #36945)

This isn't an Object test, it's a CodeGen test and should be added to the appropriate test/CodeGen/Mips/*atomic*.ll.

The test can't distinguish the pre-R6 sc from the R6 sc. The patch needs to use FileCheck (http://llvm.org/docs/CommandGuide/FileCheck.html) instead of grep and should check the encoding to be sure the right instruction was used.

Also, please check for the correct ll, lld, and scd.

[Jelena.Losic]

Test implementation given in the patch is able to detect situation when pre-R6 opcode is generated for sc instruction.
Object code is generated by llc, disassembled by llvm-objdump (command line option -mattr=+mips64r6 is used) and llvm-objdump output is searched (by using grep - it is used in Object tests) for occurrence of sc mnemonic.
Because -mattr=+mips64r6 option is used llvm-objdump is not able to disassemble pre-R6 instruction opcodes and reports warning instead of instruction mnemonic.

llvm-objdump output - WITHOUT patch applied:
Disassembly of section .text:
atomic_load_test:

0:     f0 ff bd 67            daddiu  $sp, $sp, -16
4:     08 00 a3 df           ld            $3, 8($sp)
8:     00 00 04 24          addiu     $4, $zero, 0

llvm/llvm2/build/bin/llvm-objdump: warning: invalid instruction encoding <- without patch opcode is not recognized

10:    05 00 44 14          bne        $2, $4, 24
14:    00 00 00 00          nop
18:    00 00 05 24          addiu     $5, $zero, 0

llvm/llvm2/build/bin/llvm-objdump: warning: invalid instruction encoding <- without patch opcode is not recognized

20:    fa ff a0 10            beqz      $5, -20
24:    00 00 00 00          nop
28:    0f 00 00 00           sync
2c:    04 00 a2 af           sw          $2, 4($sp)
30:    09 00 e0 03          jr             $ra
34:    10 00 bd 67          daddiu  $sp, $sp, 16

llvm-objdump output - WITH patch applied:
Disassembly of section .text:
atomic_load_test:

 0:     f0 ff bd 67            daddiu  $sp, $sp, -16
 4:     08 00 a3 df           ld            $3, 8($sp)
 8:     00 00 04 24          addiu     $4, $zero, 0
 c:      36 00 62 7c           ll              $2, 0($3)
10:    05 00 44 14          bne        $2, $4, 24
14:    00 00 00 00          nop
18:    00 00 05 24          addiu     $5, $zero, 0
1c:    26 00 65 7c           sc            $5, 0($3)                   <- with patch opcode is recognized
20:    fa ff a0 10            beqz      $5, -20
24:    00 00 00 00          nop
28:    0f 00 00 00           sync
2c:    04 00 a2 af           sw          $2, 4($sp)
30:    09 00 e0 03          jr             $ra
34:    10 00 bd 67          daddiu  $sp, $sp, 16

Is it OK with you if I move test in CodeGen and modify it to use FileCheck instead of grep or some other approach is needed to check generated opcodes?
Having in mind that existing (non micromips) atomic tests do not check instruction opcodes is it OK to create new test in this case?

I will add checks for ll, lld and scd opcodes.

[dsanders]

In D13593#265806, @Jelena.Losic wrote:

Test implementation given in the patch is able to detect situation when pre-R6 opcode is generated for sc instruction.
Object code is generated by llc, disassembled by llvm-objdump (command line option -mattr=+mips64r6 is used) and llvm-objdump output is searched (by using grep - it is used in Object tests) for occurrence of sc mnemonic.
Because -mattr=+mips64r6 option is used llvm-objdump is not able to disassemble pre-R6 instruction opcodes and reports warning instead of instruction mnemonic.

That makes sense. So long as the tablegen-erated disassembler table has the encoding correct (and we test this elsewhere) then it can tell the difference. However, we can't rely on this in the long term since the invalid opcode will be re-used at some point and we don't know what the mnemonic will be.

Is it OK with you if I move test in CodeGen and modify it to use FileCheck instead of grep or some other approach is needed to check generated opcodes?

Moving the test to CodeGen and using FileCheck and a directive like 'CHECK: 26 00 65 7c sc $5, 0($3)' makes sense to me. If you update this review once you've made the change then I'll take a look at the new test.

It might be worth seeing if the -asm-show-inst to llc makes it possible to avoid assembling and disassembling in a CodeGen test. This option causes llc to emit the internal representation in a comment like so:

move $fp, $sp  # <MCInst #1480 OR
               #  <MCOperand Reg:8>
               #  <MCOperand Reg:20>
               #  <MCOperand Reg:21>>

In the case of 'sc', we should see 'SC' or 'SC_R6' depending on which was selected.

Having in mind that existing (non micromips) atomic tests do not check instruction opcodes is it OK to create new test in this case?

Generally speaking, we don't need to check opcodes in CodeGen tests. It should be sufficient to check the mnemonic. sc/scd/ll/lld are a bit trickier since we have multiple copies of these instructions and we need to make sure we selected the correct 'sc'. I'd prefer to use -asm-show-inst if possible but if we need to check opcodes to tell them apart then we'll have to do that.

I will add checks for ll, lld and scd opcodes.

Thanks

[Jelena.Losic]

Option -asm-show-inst enables writting test without disassembling as Daniel mentioned.

[dsanders]

Thanks. This patch is nearly there.

I will add checks for ll, lld and scd opcodes.

You haven't added these checks yet.

lib/Target/Mips/MipsISelLowering.cpp

1550

Nit: Remove unnecessary blank line

test/CodeGen/Mips/at1.ll

1

(about filename): Please rename at1.ll to something meaningful. There are some existing tests named atomic*.ll. Something similar would make sense to me.

[Jelena.Losic]

The test is changed, now there is checking for all instructions required, also test name is changed.

[dsanders]

Thanks. LGTM

lib/Target/Mips/MipsISelLowering.cpp

MachineBasicBlock * MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
   MachineFunction *MF = BB->getParent();
   MachineRegisterInfo &RegInfo = MF->getRegInfo();
   const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
   DebugLoc DL = MI->getDebugLoc();
   unsigned LL, SC, ZERO, BNE, BEQ;
 
   if (Size == 4) {
-    LL = isMicroMips ? Mips::LL_MM : Mips::LL;
-    SC = isMicroMips ? Mips::SC_MM : Mips::SC;
+     if (isMicroMips) {
+       LL = Mips::LL_MM;
+       SC = Mips::SC_MM;
+     } else {
+       LL = Subtarget.hasMips32r6() ? Mips::LL_R6 : Mips::LL;
+       SC = Subtarget.hasMips32r6() ? Mips::SC_R6 : Mips::SC;
+     }
     ZERO = Mips::ZERO;
     BNE = Mips::BNE;
     BEQ = Mips::BEQ;
   } else {
-    LL = Mips::LLD;
-    SC = Mips::SCD;
+    LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
+    SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
     ZERO = Mips::ZERO_64;
     BNE = Mips::BNE64;
     BEQ = Mips::BEQ64;
   }
 
   unsigned Dest    = MI->getOperand(0).getReg();
   unsigned Ptr     = MI->getOperand(1).getReg();
   unsigned OldVal  = MI->getOperand(2).getReg();
MachineBasicBlock * MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
   BuildMI(BB, DL, TII->get(BEQ))
     .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
 
   MI->eraseFromParent(); // The instruction is gone now.
 
   return exitMBB;
 }
 
  MachineBasicBlock *
  MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI,
                                                MachineBasicBlock *BB,
                                                unsigned Size) const {
    assert((Size == 1 || Size == 2) &&
        "Unsupported size for EmitAtomicCmpSwapPartial.");
  
    MachineFunction *MF = BB->getParent();
    MachineRegisterInfo &RegInfo = MF->getRegInfo();
    const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
    const TargetInstrInfo *TII = Subtarget.getInstrInfo();
    DebugLoc DL = MI->getDebugLoc();
  
    unsigned Dest    = MI->getOperand(0).getReg();
    unsigned Ptr     = MI->getOperand(1).getReg();
    unsigned CmpVal  = MI->getOperand(2).getReg();
    unsigned NewVal  = MI->getOperand(3).getReg();
  
    unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
    unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
    unsigned Mask = RegInfo.createVirtualRegister(RC);
    unsigned Mask2 = RegInfo.createVirtualRegister(RC);
    unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
    unsigned OldVal = RegInfo.createVirtualRegister(RC);
    unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
    unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
    unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
    unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
    unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
    unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
    unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
    unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
    unsigned StoreVal = RegInfo.createVirtualRegister(RC);
    unsigned SrlRes = RegInfo.createVirtualRegister(RC);
    unsigned Success = RegInfo.createVirtualRegister(RC);
  
    // insert new blocks after the current block
    const BasicBlock *LLVM_BB = BB->getBasicBlock();
    MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
    MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
    MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
    MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
    MachineFunction::iterator It = BB;
    ++It;
    MF->insert(It, loop1MBB);
    MF->insert(It, loop2MBB);
    MF->insert(It, sinkMBB);
    MF->insert(It, exitMBB);
  
    // Transfer the remainder of BB and its successor edges to exitMBB.
    exitMBB->splice(exitMBB->begin(), BB,
                    std::next(MachineBasicBlock::iterator(MI)), BB->end());
    exitMBB->transferSuccessorsAndUpdatePHIs(BB);
  
    BB->addSuccessor(loop1MBB);
    loop1MBB->addSuccessor(sinkMBB);
    loop1MBB->addSuccessor(loop2MBB);
    loop2MBB->addSuccessor(loop1MBB);
    loop2MBB->addSuccessor(sinkMBB);
    sinkMBB->addSuccessor(exitMBB);
  
    // FIXME: computation of newval2 can be moved to loop2MBB.
    //  thisMBB:
    //    addiu   masklsb2,$0,-4                # 0xfffffffc
    //    and     alignedaddr,ptr,masklsb2
    //    andi    ptrlsb2,ptr,3
    //    sll     shiftamt,ptrlsb2,3
    //    ori     maskupper,$0,255               # 0xff
    //    sll     mask,maskupper,shiftamt
    //    nor     mask2,$0,mask
    //    andi    maskedcmpval,cmpval,255
    //    sll     shiftedcmpval,maskedcmpval,shiftamt
    //    andi    maskednewval,newval,255
    //    sll     shiftednewval,maskednewval,shiftamt
    int64_t MaskImm = (Size == 1) ? 255 : 65535;
    BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
      .addReg(Mips::ZERO).addImm(-4);
    BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
      .addReg(Ptr).addReg(MaskLSB2);
    BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
    if (Subtarget.isLittle()) {
      BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
    } else {
      unsigned Off = RegInfo.createVirtualRegister(RC);
      BuildMI(BB, DL, TII->get(Mips::XORi), Off)
        .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
      BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
    }
    BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
      .addReg(Mips::ZERO).addImm(MaskImm);
    BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
      .addReg(MaskUpper).addReg(ShiftAmt);
    BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
    BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
      .addReg(CmpVal).addImm(MaskImm);
    BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
      .addReg(MaskedCmpVal).addReg(ShiftAmt);
    BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
      .addReg(NewVal).addImm(MaskImm);
    BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
      .addReg(MaskedNewVal).addReg(ShiftAmt);
  
    //  loop1MBB:
    //    ll      oldval,0(alginedaddr)
    //    and     maskedoldval0,oldval,mask
    //    bne     maskedoldval0,shiftedcmpval,sinkMBB
    BB = loop1MBB;
    unsigned LL = isMicroMips ? Mips::LL_MM : Mips::LL;
    BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
    BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
      .addReg(OldVal).addReg(Mask);
    BuildMI(BB, DL, TII->get(Mips::BNE))
      .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
  
    //  loop2MBB:
    //    and     maskedoldval1,oldval,mask2
    //    or      storeval,maskedoldval1,shiftednewval
    //    sc      success,storeval,0(alignedaddr)
    //    beq     success,$0,loop1MBB
    BB = loop2MBB;
    BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
      .addReg(OldVal).addReg(Mask2);
    BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
      .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
    unsigned SC = isMicroMips ? Mips::SC_MM : Mips::SC;
    BuildMI(BB, DL, TII->get(SC), Success)
        .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
    BuildMI(BB, DL, TII->get(Mips::BEQ))
        .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
  
    //  sinkMBB:
    //    srl     srlres,maskedoldval0,shiftamt
    //    sign_extend dest,srlres
    BB = sinkMBB;
  
    BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
        .addReg(MaskedOldVal0).addReg(ShiftAmt);
    BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
  
    MI->eraseFromParent();   // The instruction is gone now.
  
    return exitMBB;
  }
 
+
 MachineBasicBlock *MipsTargetLowering::emitSEL_D(MachineInstr *MI,
                                                  MachineBasicBlock *BB) const {
   MachineFunction *MF = BB->getParent();
   const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
   MachineRegisterInfo &RegInfo = MF->getRegInfo();
   DebugLoc DL = MI->getDebugLoc();
   MachineBasicBlock::iterator II(MI);

test/CodeGen/Mips/at1.ll

+; RUN: llc -asm-show-inst  -march=mips64el -mcpu=mips64r6 < %s -filetype=asm -o - \
+; RUN:   | FileCheck %s 
+
+define internal i32 @atomic_load_test() #0 {
+entry:
+
+  %load_add = alloca i32*, align 8
+  %.atomicdst = alloca i32, align 4
+  %0 = load i32*, i32** %load_add, align 8
+  %1 = load atomic i32, i32* %0 acquire, align 4
+  store i32 %1, i32* %.atomicdst, align 4
+  %2 = load i32, i32* %.atomicdst, align 4
+  
+  ret i32 %2
+}
+;CHECK:  LL_R6
 No newline at end of file