error for INT64_MIN / -1; clarify signed division; simplify errors

llvm/docs/TableGen/ProgRef.rst

``!dag(``\ *op*\ ``,`` *arguments*\ ``,`` *names*\ ``)``
     of a common type. In practice, this means that they should either have the
     same type or be records with a common parent class. Mixing ``dag`` and
     non-``dag`` items is not possible. However, ``?`` can be used.
 
     Example: ``!dag(op, [a1, a2, ?], ["name1", "name2", "name3"])`` results in
     ``(op a1-value:$name1, a2-value:$name2, ?:$name3)``.
 
 ``!div(``\ *a*\ ``,`` *b*\ ``)``
-    This operator divides *a* and *b*, and produces the quotient.
-    Division by 0 produces an error.
+    This operator preforms signed division of *a* by *b*, and produces the quotient.
+    Division by 0 produces an error. Division by INT64_MIN produces an error.
 
 ``!empty(``\ *a*\ ``)``
     This operator produces 1 if the string, list, or DAG *a* is empty; 0 otherwise.
     A dag is empty if it has no arguments; the operator does not count.
 
 ``!eq(`` *a*\ `,` *b*\ ``)``
     This operator produces 1 if *a* is equal to *b*; 0 otherwise.
     The arguments must be ``bit``, ``bits``, ``int``, ``string``, or

llvm/lib/TableGen/Record.cpp

if (LHSi && RHSi) {
       switch (getOpcode()) {
       default: llvm_unreachable("Bad opcode!");
       case ADD: Result = LHSv + RHSv; break;
       case SUB: Result = LHSv - RHSv; break;
       case MUL: Result = LHSv * RHSv; break;
       case DIV:
         if (RHSv == 0)
           PrintFatalError(CurRec->getLoc(),
-                          Twine("Illegal operation: division by zero"));
+                          "Illegal operation: division by zero");
+        else if (LHSv == INT64_MIN && RHSv == -1)
+          PrintFatalError(CurRec->getLoc(),
+                          "Illegal operation: INT64_MIN / -1");
         else
           Result = LHSv / RHSv;
         break;
       case AND: Result = LHSv & RHSv; break;
       case OR:  Result = LHSv | RHSv; break;
       case XOR: Result = LHSv ^ RHSv; break;
       case SHL: Result = (uint64_t)LHSv << (uint64_t)RHSv; break;
       case SRA: Result = LHSv >> RHSv; break;

llvm/test/TableGen/math.td

 // RUN: llvm-tblgen %s | FileCheck %s
 // RUN: not llvm-tblgen -DERROR1 %s 2>&1 | FileCheck --check-prefix=ERROR1 %s
+// RUN: not llvm-tblgen -DERROR2 %s 2>&1 | FileCheck --check-prefix=ERROR2 %s
 // XFAIL: vg_leak
 
 // CHECK: def shifts
 // CHECK: shifted_b = 8
 // CHECK: shifted_i = 8
 def shifts {
     bits<2> b = 0b10;
     int i = 2;

 // CHECK: Value = -2
 def v17 : Int<!div(-8, 4)>;
 
 #ifdef ERROR1
 // ERROR1: error: Illegal operation: division by zero
 def v18 : Int<!div(4, 0)>;
 #endif
 
+#ifdef ERROR2
+// ERROR2: error: Illegal operation: INT64_MIN / -1
+def v19 : Int<!div(-9223372036854775808, -1)>;
+#endif
+
 // CHECK: def v1a
 // CHECK: Value = 1
 
 // CHECK: def v2048
 // CHECK: Value = 2048
 def v2048   : Int<!add(int1024.Value, int1024.Value)>;
 
 // CHECK: def v3072

 
 // CHECK: def v925
 // CHECK: Value = 925
 def v925 : Int<!sub(v924.Value, -1)>;
 
 // CHECK: def vneg
 // CHECK: Value = -2
 def vneg : Int<!sub(v925.Value, 927)>;
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