AMDGPU: Optimize VOP2 operand legalization

[arsenm]

Summary

Don't use commuteInstruction, and don't commute if
doing so will not improve legality.

With this patch and others leading up to it, this
reduces the compile time of SIFixSGPRCopies on
some of the LuxMark 2 kernels from ~8ms to ~5ms
on my system.

[arsenm]

Better handling of VOP2b implicit VCC uses

[• tstellarAMD]

lib/Target/AMDGPU/SIInstrInfo.cpp

1702

Which patch adds this function?

[arsenm]

Rebase and squash other "Simplify VOP2 operand legalization" patch

[• tstellarAMD]

LGTM.

[arsenm]

r254452

lib/Target/AMDGPU/SIInstrInfo.cpp

1702

http://reviews.llvm.org/D13483

lib/Target/AMDGPU/SIInstrInfo.h

bool isLegalVSrcOperand(const MachineRegisterInfo &MRI,
                           const MachineOperand &MO) const;
 
   /// \brief Check if \p MO (a register operand) is a legal register for the
   /// given operand description.
   bool isLegalRegOperand(const MachineRegisterInfo &MRI,
                          const MCOperandInfo &OpInfo,
                          const MachineOperand &MO) const;
 
+  /// \brief Legalize operands in \p MI by either commuting it or inserting a
+  /// copy of src1.
+  void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr *MI) const;
+
   /// \brief Fix operands in \p MI to satisfy constant bus requirements.
   void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr *MI) const;
 
   /// \brief Legalize all operands in this instruction.  This function may
   /// create new instruction and insert them before \p MI.
   void legalizeOperands(MachineInstr *MI) const;
 
   /// \brief Split an SMRD instruction into two smaller loads of half the

lib/Target/AMDGPU/SIInstrInfo.cpp

bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
   if (!DefinedRC) {
     // This operand expects an immediate.
     return true;
   }
 
   return isImmOperandLegal(MI, OpIdx, *MO);
 }
 
+void SIInstrInfo::legalizeOperandsVOP2(MachineRegisterInfo &MRI,
+                                       MachineInstr *MI) const {
+  unsigned Opc = MI->getOpcode();
+  const MCInstrDesc &InstrDesc = get(Opc);
+
+  int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
+  MachineOperand &Src1 = MI->getOperand(Src1Idx);
+
+  // VOP2 src0 instructions support all operand types, so we don't need to check
+  // their legality. If src1 is already legal, we don't need to do anything.
+  if (isLegalRegOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src1))
+    return;
+
+  // We do not use commuteInstruction here because it is too aggressive and will
+  // commute if it is possible. We only want to commute here if it improves
+  // legality. This can be called a fairly large number of times so don't waste
+  // compile time pointlessly swapping and checking legality again.
+  if (!MI->isCommutable()) {
+    legalizeOpWithMove(MI, Src1Idx);
+    return;
+  }
+
+  int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
+  MachineOperand &Src0 = MI->getOperand(Src0Idx);
+
+  // If src0 can be used as src1, commuting will make the operands legal.
+  // Otherwise we have to give up and insert a move.
+  //
+  // TODO: Other immediate-like operand kinds could be commuted if there was a
+  // MachineOperand::ChangeTo* for them.
+  if ((!Src1.isImm() && !Src1.isReg()) ||
+      !isLegalRegOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src0)) {
+    legalizeOpWithMove(MI, Src1Idx);
+    return;
+  }
+
+  int CommutedOpc = commuteOpcode(*MI);
+  if (CommutedOpc == -1) {
+    legalizeOpWithMove(MI, Src1Idx);
+    return;
+  }
+
+  MI->setDesc(get(CommutedOpc));
+
+  unsigned Src0Reg = Src0.getReg();
+  unsigned Src0SubReg = Src0.getSubReg();
+  bool Src0Kill = Src0.isKill();
+
+  if (Src1.isImm())
+    Src0.ChangeToImmediate(Src1.getImm());
+  else if (Src1.isReg()) {
+    Src0.ChangeToRegister(Src1.getReg(), false, false, Src1.isKill());
+    Src0.setSubReg(Src1.getSubReg());
+  } else
+    llvm_unreachable("Should only have register or immediate operands");
+
+  Src1.ChangeToRegister(Src0Reg, false, false, Src0Kill);
+  Src1.setSubReg(Src0SubReg);
+}
+
 // Legalize VOP3 operands. Because all operand types are supported for any
 // operand, and since literal constants are not allowed and should never be
 // seen, we only need to worry about inserting copies if we use multiple SGPR
 // operands.
 void SIInstrInfo::legalizeOperandsVOP3(
   MachineRegisterInfo &MRI,
   MachineInstr *MI) const {
   unsigned Opc = MI->getOpcode();
void SIInstrInfo::legalizeOperandsVOP3(
   }
 }
 
 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
   MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
   unsigned Opc = MI->getOpcode();
 
   // Legalize VOP2
-
-  const MCInstrDesc &InstrDesc = get(Opc);
-
   if (isVOP2(Opc)) {
-    if (MI->isCommutable()) {
-      if (commuteInstruction(MI)) {
-        // If we are successful in commuting, then we know MI is legal, so
-        // we are done.
-        return;
-      }
-    }
-
-    // VOP2 src0 instructions support all operand types, so we don't need to
-    // check their legality.
-    int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
-    MachineOperand &Src1 = MI->getOperand(Src1Idx);
-
-    if (!isLegalVSrcOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src1))
-      legalizeOpWithMove(MI, Src1Idx);
-
+    legalizeOperandsVOP2(MRI, MI);
     return;
   }
 
   // Legalize VOP3
   if (isVOP3(Opc)) {
     legalizeOperandsVOP3(MRI, MI);
     return;
   }