[X86][AVX512] add support in VFPCLASS

[AsafBadouh]

Summary

Tests Types Of a Packed FP Values

[delena]

LGTM

../commit/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td

237

This define is unique for FPCLASS. Please put it inside the X86Vfpclass

../commit/llvm/include/llvm/IR/IntrinsicsX86.td

def int_x86_avx_ptestnzc_256 : GCCBuiltin<"__builtin_ia32_ptestnzc256">,
         Intrinsic<[llvm_i32_ty], [llvm_v4i64_ty,
                   llvm_v4i64_ty], [IntrNoMem]>;
   def int_x86_avx512_mask_ptestm_d_512 : GCCBuiltin<"__builtin_ia32_ptestmd512">,
         Intrinsic<[llvm_i16_ty], [llvm_v16i32_ty, llvm_v16i32_ty,
                   llvm_i16_ty], [IntrNoMem]>;
   def int_x86_avx512_mask_ptestm_q_512 : GCCBuiltin<"__builtin_ia32_ptestmq512">,
         Intrinsic<[llvm_i8_ty], [llvm_v8i64_ty, llvm_v8i64_ty,
                   llvm_i8_ty], [IntrNoMem]>;
+  def int_x86_avx512_mask_fpclass_pd_128 : 
+         GCCBuiltin<"__builtin_ia32_fpclasspd128_mask">,
+          Intrinsic<[llvm_i8_ty], [llvm_v2f64_ty, llvm_i32_ty, llvm_i8_ty],
+          [IntrNoMem]>;
+  def int_x86_avx512_mask_fpclass_pd_256 : 
+         GCCBuiltin<"__builtin_ia32_fpclasspd256_mask">,
+          Intrinsic<[llvm_i8_ty], [llvm_v4f64_ty, llvm_i32_ty, llvm_i8_ty],
+          [IntrNoMem]>;
+  def int_x86_avx512_mask_fpclass_pd_512 : 
+         GCCBuiltin<"__builtin_ia32_fpclasspd512_mask">,
+          Intrinsic<[llvm_i8_ty], [llvm_v8f64_ty, llvm_i32_ty, llvm_i8_ty],
+          [IntrNoMem]>;
+  def int_x86_avx512_mask_fpclass_ps_128 : 
+         GCCBuiltin<"__builtin_ia32_fpclassps128_mask">,
+          Intrinsic<[llvm_i8_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i8_ty],
+          [IntrNoMem]>;
+  def int_x86_avx512_mask_fpclass_ps_256 : 
+         GCCBuiltin<"__builtin_ia32_fpclassps256_mask">,
+          Intrinsic<[llvm_i8_ty], [llvm_v8f32_ty, llvm_i32_ty, llvm_i8_ty],
+          [IntrNoMem]>;
+  def int_x86_avx512_mask_fpclass_ps_512 : 
+         GCCBuiltin<"__builtin_ia32_fpclassps512_mask">,
+          Intrinsic<[llvm_i16_ty], [llvm_v16f32_ty, llvm_i32_ty, llvm_i16_ty],
+          [IntrNoMem]>;
 }
 
 // Vector extract sign mask
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_avx_movmsk_pd_256 : GCCBuiltin<"__builtin_ia32_movmskpd256">,
         Intrinsic<[llvm_i32_ty], [llvm_v4f64_ty], [IntrNoMem]>;
   def int_x86_avx_movmsk_ps_256 : GCCBuiltin<"__builtin_ia32_movmskps256">,
         Intrinsic<[llvm_i32_ty], [llvm_v8f32_ty], [IntrNoMem]>;

../commit/llvm/lib/Target/X86/X86ISelLowering.h

enum NodeType : unsigned {
       //Fix Up Special Packed Float32/64 values
       VFIXUPIMM,
       //Range Restriction Calculation For Packed Pairs of Float32/64 values
       VRANGE,
       // Reduce - Perform Reduction Transformation on scalar\packed FP
       VREDUCE,
       // RndScale - Round FP Values To Include A Given Number Of Fraction Bits
       VRNDSCALE,
+      // VFPCLASS - Tests Types Of a FP Values
+      VFPCLASS, 
       // Broadcast scalar to vector
       VBROADCAST,
       // Broadcast subvector to vector
       SUBV_BROADCAST,
       // Insert/Extract vector element
       VINSERT,
       VEXTRACT,
 

../commit/llvm/lib/Target/X86/X86ISelLowering.cpp

static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
 
     switch (Op.getOpcode()) {
       default: break;
       case X86ISD::PCMPEQM:
       case X86ISD::PCMPGTM:
       case X86ISD::CMPM:
       case X86ISD::CMPMU:
         return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
+      case X86ISD::VFPCLASS:
+        return DAG.getNode(ISD::OR, dl, VT, Op, VMask);
       case X86ISD::VTRUNC:
       case X86ISD::VTRUNCS:
       case X86ISD::VTRUNCUS:
         // We can't use ISD::VSELECT here because it is not always "Legal"
         // for the destination type. For example vpmovqb require only AVX512
         // and vselect that can operate on byte element type require BWI
         OpcodeSelect = X86ISD::SELECT;
         break;
case FMA_OP_MASK: {
                                                   Src1, Src2, Src3, Rnd),
                                       Mask, PassThru, Subtarget, DAG);
       }
       return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
                                               dl, Op.getValueType(),
                                               Src1, Src2, Src3),
                                   Mask, PassThru, Subtarget, DAG);
     }
+    case FPCLASS: {
+      // FPclass intrinsics with mask
+      //
+       SDValue Src1 = Op.getOperand(1);
+       EVT VT = Src1.getValueType();
+       EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
+                                      VT.getVectorNumElements());
+       SDValue Imm = Op.getOperand(2);
+       SDValue Mask = Op.getOperand(3);
+       EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
+                                        Mask.getValueType().getSizeInBits());
+       SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MaskVT, Src1, Imm);
+       SDValue FPclassMask = getVectorMaskingNode(FPclass, Mask,
+                                                 DAG.getTargetConstant(0, dl, MaskVT),
+                                                 Subtarget, DAG);
+       SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
+                                 DAG.getUNDEF(BitcastVT), FPclassMask,
+                                 DAG.getIntPtrConstant(0, dl));
+       return DAG.getBitcast(Op.getValueType(), Res);
+    }
     case CMP_MASK:
     case CMP_MASK_CC: {
       // Comparison intrinsics with masks.
       // Example of transformation:
       // (i8 (int_x86_avx512_mask_pcmpeq_q_128
       //             (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
       // (i8 (bitcast
       //   (v8i1 (insert_subvector undef,
const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
   case X86ISD::ADDS:               return "X86ISD::ADDS";
   case X86ISD::SUBS:               return "X86ISD::SUBS";
   case X86ISD::AVG:                return "X86ISD::AVG";
   case X86ISD::MULHRS:             return "X86ISD::MULHRS";
   case X86ISD::SINT_TO_FP_RND:     return "X86ISD::SINT_TO_FP_RND";
   case X86ISD::UINT_TO_FP_RND:     return "X86ISD::UINT_TO_FP_RND";
   case X86ISD::FP_TO_SINT_RND:     return "X86ISD::FP_TO_SINT_RND";
   case X86ISD::FP_TO_UINT_RND:     return "X86ISD::FP_TO_UINT_RND";
+  case X86ISD::VFPCLASS:           return "X86ISD::VFPCLASS";
   }
   return nullptr;
 }
 
 // isLegalAddressingMode - Return true if the addressing mode represented
 // by AM is legal for this target, for a load/store of the specified type.
 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
                                               const AddrMode &AM, Type *Ty,

../commit/llvm/lib/Target/X86/X86InstrAVX512.td

def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
             (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
             imm:$cc), VK8)>;
 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
           (COPY_TO_REGCLASS (VPCMPUDZrri
             (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
             (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
             imm:$cc), VK8)>;
 
+// ----------------------------------------------------------------
+// FPClass
+//handle fpclass instruction mask = fpclass(reg_vec, reg_vec, imm)
+//                                  fpclass(reg_vec, mem_vec, imm)
+//                                  fpclass(reg_vec, broadcast(eltVt), imm)
+multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
+                                 X86VectorVTInfo _, string mem, string broadcast>{
+  def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
+                      (ins _.RC:$src1, i32u8imm:$src2),
+                      OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst | $dst, $src1, $src2}",
+                      [(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
+                                       (i32 imm:$src2)))], NoItinerary>;
+  def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
+                      (ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
+                      OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst {${mask}}| $dst {${mask}}, $src1, $src2}",
+                      [(set _.KRC:$dst,(or _.KRCWM:$mask, 
+                                       (OpNode (_.VT _.RC:$src1),
+                                       (i32 imm:$src2))))], NoItinerary>, EVEX_K;
+  let mayLoad = 1 in {
+    def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
+                      (ins _.MemOp:$src1, i32u8imm:$src2),
+                      OpcodeStr##_.Suffix##mem#"\t{$src2, $src1, $dst | $dst, $src1, $src2}",
+                      [(set _.KRC:$dst,(OpNode 
+                                       (_.VT (bitconvert (_.LdFrag addr:$src1))),
+                                       (i32 imm:$src2)))], NoItinerary>;
+    def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
+                      (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
+                      OpcodeStr##_.Suffix##mem#"\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
+                      [(set _.KRC:$dst, (or _.KRCWM:$mask, (OpNode 
+                                    (_.VT (bitconvert (_.LdFrag addr:$src1))),
+                                    (i32 imm:$src2))))], NoItinerary>, EVEX_K;
+    def rmb : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
+                      (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
+                      OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##_.BroadcastStr##", $dst | $dst, ${src1}"##_.BroadcastStr##", $src2}",
+                      [(set _.KRC:$dst,(OpNode 
+                                       (_.VT (X86VBroadcast 
+                                             (_.ScalarLdFrag addr:$src1))),
+                                       (i32 imm:$src2)))], NoItinerary>,EVEX_B;
+    def rmbk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
+                      (ins _.KRCWM:$mask, _.ScalarMemOp:$src1, i32u8imm:$src2),
+                      OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##_.BroadcastStr##", $dst {${mask}} | $dst {${mask}}, ${src1}"##_.BroadcastStr##", $src2}",
+                      [(set _.KRC:$dst,(or _.KRCWM:$mask, (OpNode 
+                                       (_.VT (X86VBroadcast 
+                                             (_.ScalarLdFrag addr:$src1))),
+                                       (i32 imm:$src2))))], NoItinerary>,
+                                                            EVEX_B, EVEX_K;
+  }
+}
+
+
+multiclass avx512_vector_fpclass_all<string OpcodeStr,
+            AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd, string broadcast>{
+  let Predicates = [prd] in {
+    defm Z    : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info512, "{z}", broadcast>,
+                                  EVEX_V512;
+  }
+  let Predicates = [prd, HasVLX] in {
+    defm Z128 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info128, "{x}", broadcast>,
+                                  EVEX_V128;
+    defm Z256 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info256, "{y}", broadcast>,
+                                  EVEX_V256;
+  }
+}
+
+multiclass avx512_fp_fpclass_all<string OpcodeStr, bits<8> opcVec,
+                                 SDNode OpNode, Predicate prd>{
+  defm PS : avx512_vector_fpclass_all<OpcodeStr,  avx512vl_f32_info, opcVec, 
+                                            OpNode, prd, "{l}">, EVEX_CD8<32, CD8VF>;
+  defm PD : avx512_vector_fpclass_all<OpcodeStr,  avx512vl_f64_info, opcVec, 
+                                            OpNode, prd, "{q}">,EVEX_CD8<64, CD8VF> , VEX_W;
+}
+
+defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, X86Vfpclass, HasDQI>,AVX512AIi8Base,EVEX;
+
 //-----------------------------------------------------------------
 // Mask register copy, including
 // - copy between mask registers
 // - load/store mask registers
 // - copy from GPR to mask register and vice versa
 //
 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
                          string OpcodeStr, RegisterClass KRC,

../commit/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td

 def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
                                         SDTCisVec<2>]>;
 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
                                  SDTCisSameAs<0,1>, SDTCisInt<2>]>;
 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
                                  SDTCisSameAs<0,2>, SDTCisInt<3>]>;
 def SDTFPBinOpImmRound: SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
                              SDTCisSameAs<0,2>, SDTCisInt<3>, SDTCisInt<4>]>;
+def SDTFPUnaryOpImm: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
+                              SDTCisVec<1>, SDTCisInt<2>]>;
 def SDTFPUnaryOpImmRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
                               SDTCisInt<2>, SDTCisInt<3>]>;
 
 def SDTVBroadcast  : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
 def SDTVBroadcastm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>]>;
 
 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
                              SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;

 
 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
 
 def X86VFixupimm   : SDNode<"X86ISD::VFIXUPIMM", SDTFPBinOpImmRound>;
 def X86VRange      : SDNode<"X86ISD::VRANGE",    SDTFPBinOpImmRound>;
 def X86VReduce     : SDNode<"X86ISD::VREDUCE",   SDTFPUnaryOpImmRound>;
 def X86VRndScale   : SDNode<"X86ISD::VRNDSCALE", SDTFPUnaryOpImmRound>;
 def X86VGetMant    : SDNode<"X86ISD::VGETMANT",  SDTFPUnaryOpImmRound>;
+def X86Vfpclass    : SDNode<"X86ISD::VFPCLASS", SDTFPUnaryOpImm>;
 
 def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",
                     SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
                                          SDTCisSubVecOfVec<1, 0>]>, []>;
 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
 def X86Vinsert   : SDNode<"X86ISD::VINSERT",  SDTypeProfile<1, 3,
                               [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
 def X86Vextract   : SDNode<"X86ISD::VEXTRACT",  SDTypeProfile<1, 2,

../commit/llvm/lib/Target/X86/X86IntrinsicsInfo.h

 
 #ifndef LLVM_LIB_TARGET_X86_X86INTRINSICSINFO_H
 #define LLVM_LIB_TARGET_X86_X86INTRINSICSINFO_H
 
 namespace llvm {
 
 enum IntrinsicType {
   INTR_NO_TYPE,
-  GATHER, SCATTER, PREFETCH, RDSEED, RDRAND, RDPMC, RDTSC, XTEST, ADX,
+  GATHER, SCATTER, PREFETCH, RDSEED, RDRAND, RDPMC, RDTSC, XTEST, ADX, FPCLASS,
   INTR_TYPE_1OP, INTR_TYPE_2OP, INTR_TYPE_2OP_IMM8, INTR_TYPE_3OP, INTR_TYPE_4OP,
   CMP_MASK, CMP_MASK_CC, VSHIFT, VSHIFT_MASK, COMI,
   INTR_TYPE_1OP_MASK, INTR_TYPE_1OP_MASK_RM,
   INTR_TYPE_2OP_MASK, INTR_TYPE_2OP_MASK_RM,
   INTR_TYPE_3OP_MASK, INTR_TYPE_3OP_MASK_RM, INTR_TYPE_3OP_IMM8_MASK,
   FMA_OP_MASK, FMA_OP_MASKZ, FMA_OP_MASK3, VPERM_3OP_MASK,
   VPERM_3OP_MASKZ,
   INTR_TYPE_SCALAR_MASK_RM, INTR_TYPE_3OP_SCALAR_MASK_RM,
static const IntrinsicData  IntrinsicsWithoutChain[] = {
   X86_INTRINSIC_DATA(avx512_mask_expand_ps_512, COMPRESS_EXPAND_IN_REG,
                      X86ISD::EXPAND, 0),
   X86_INTRINSIC_DATA(avx512_mask_expand_q_128,  COMPRESS_EXPAND_IN_REG,
                      X86ISD::EXPAND, 0),
   X86_INTRINSIC_DATA(avx512_mask_expand_q_256,  COMPRESS_EXPAND_IN_REG,
                      X86ISD::EXPAND, 0),
   X86_INTRINSIC_DATA(avx512_mask_expand_q_512,  COMPRESS_EXPAND_IN_REG,
                      X86ISD::EXPAND, 0),
+  X86_INTRINSIC_DATA(avx512_mask_fpclass_pd_128, FPCLASS, X86ISD::VFPCLASS, 0), 
+  X86_INTRINSIC_DATA(avx512_mask_fpclass_pd_256, FPCLASS, X86ISD::VFPCLASS, 0), 
+  X86_INTRINSIC_DATA(avx512_mask_fpclass_pd_512, FPCLASS, X86ISD::VFPCLASS, 0), 
+  X86_INTRINSIC_DATA(avx512_mask_fpclass_ps_128, FPCLASS, X86ISD::VFPCLASS, 0), 
+  X86_INTRINSIC_DATA(avx512_mask_fpclass_ps_256, FPCLASS, X86ISD::VFPCLASS, 0),
+  X86_INTRINSIC_DATA(avx512_mask_fpclass_ps_512, FPCLASS, X86ISD::VFPCLASS, 0), 
   X86_INTRINSIC_DATA(avx512_mask_getexp_pd_128, INTR_TYPE_1OP_MASK_RM,
                      X86ISD::FGETEXP_RND, 0),
   X86_INTRINSIC_DATA(avx512_mask_getexp_pd_256, INTR_TYPE_1OP_MASK_RM,
                      X86ISD::FGETEXP_RND, 0),
   X86_INTRINSIC_DATA(avx512_mask_getexp_pd_512, INTR_TYPE_1OP_MASK_RM,
                      X86ISD::FGETEXP_RND, 0),
   X86_INTRINSIC_DATA(avx512_mask_getexp_ps_128, INTR_TYPE_1OP_MASK_RM,
                      X86ISD::FGETEXP_RND, 0),

../commit/llvm/test/CodeGen/X86/avx512dq-intrinsics.ll

 ; CHECK-NEXT:    retq
   %res  = call <8 x float> @llvm.x86.avx512.mask.vextractf32x8.512(<16 x float> %x0,i32 1, <8 x float> %x2, i8 %x3)
   %res2 = call <8 x float> @llvm.x86.avx512.mask.vextractf32x8.512(<16 x float> %x0,i32 1, <8 x float> zeroinitializer, i8 %x3)
   %res1 = call <8 x float> @llvm.x86.avx512.mask.vextractf32x8.512(<16 x float> %x0,i32 1, <8 x float> zeroinitializer, i8 -1)
   %res3 = fadd <8 x float> %res, %res1
   %res4 = fadd <8 x float> %res2, %res3
   ret <8 x float> %res4
 }
+
+declare i8 @llvm.x86.avx512.mask.fpclass.pd.512(<8 x double>, i32, i8)
+
+; CHECK-LABEL: @test_int_x86_avx512_mask_fpclass_pd_512
+; CHECK-NOT: call 
+; CHECK: kmov 
+; CHECK: vfpclasspd
+; CHECK: {%k1} 
+; CHECK: vfpclasspd
+; CHECK: kmovb   %k0
+define i8 @test_int_x86_avx512_mask_fpclass_pd_512(<8 x double> %x0, i8 %x1) {
+  %res = call i8 @llvm.x86.avx512.mask.fpclass.pd.512(<8 x double> %x0, i32 2, i8 %x1)
+  %res1 = call i8 @llvm.x86.avx512.mask.fpclass.pd.512(<8 x double> %x0, i32 4, i8 -1)
+  %res2 = add i8 %res, %res1
+  ret i8 %res2
+}
+declare i16 @llvm.x86.avx512.mask.fpclass.ps.512(<16 x float>, i32, i16)
+
+; CHECK-LABEL: @test_int_x86_avx512_mask_fpclass_ps_512
+; CHECK-NOT: call 
+; CHECK: kmov 
+; CHECK: vfpclassps
+; CHECK: vfpclassps
+; CHECK: {%k1} 
+; CHECK: kmov
+define i16@test_int_x86_avx512_mask_fpclass_ps_512(<16 x float> %x0, i16 %x1) {
+  %res = call i16 @llvm.x86.avx512.mask.fpclass.ps.512(<16 x float> %x0, i32 4, i16 %x1)
+  %res1 = call i16 @llvm.x86.avx512.mask.fpclass.ps.512(<16 x float> %x0, i32 4, i16 -1)
+  %res2 = add i16 %res, %res1
+  ret i16 %res2
+}

../commit/llvm/test/CodeGen/X86/avx512dqvl-intrinsics.ll

 ; CHECK-NEXT:    retq
   %res = call <2 x double> @llvm.x86.avx512.mask.vextractf64x2.256(<4 x double> %x0,i32 1, <2 x double> %x2, i8 %x3)
   %res2 = call <2 x double> @llvm.x86.avx512.mask.vextractf64x2.256(<4 x double> %x0,i32 1, <2 x double> zeroinitializer, i8 %x3)
   %res1 = call <2 x double> @llvm.x86.avx512.mask.vextractf64x2.256(<4 x double> %x0,i32 1, <2 x double> zeroinitializer, i8 -1)
   %res3 = fadd <2 x double> %res, %res1
   %res4 = fadd <2 x double> %res3, %res2
   ret <2 x double> %res4
 }
+
+declare i8 @llvm.x86.avx512.mask.fpclass.ps.128(<4 x float>, i32, i8)
+
+; CHECK-LABEL: @test_int_x86_avx512_mask_fpclass_ps_128
+; CHECK-NOT: call 
+; CHECK: kmov 
+; CHECK: vfpclassps
+; CHECK: {%k1} 
+; CHECK: vfpclassps
+; CHECK: kmovb   %k0
+define i8 @test_int_x86_avx512_mask_fpclass_ps_128(<4 x float> %x0, i8 %x1) {
+  %res = call i8 @llvm.x86.avx512.mask.fpclass.ps.128(<4 x float> %x0, i32 2, i8 %x1)
+  %res1 = call i8 @llvm.x86.avx512.mask.fpclass.ps.128(<4 x float> %x0, i32 4, i8 -1)
+  %res2 = add i8 %res, %res1
+  ret i8 %res2
+}
+
+declare i8 @llvm.x86.avx512.mask.fpclass.ps.256(<8 x float>, i32, i8)
+
+; CHECK-LABEL: @test_int_x86_avx512_mask_fpclass_ps_256
+; CHECK-NOT: call 
+; CHECK: kmov 
+; CHECK: vfpclassps
+; CHECK: {%k1} 
+; CHECK: vfpclassps
+; CHECK: kmovb   %k0
+define i8 @test_int_x86_avx512_mask_fpclass_ps_256(<8 x float> %x0, i8 %x1) {
+  %res = call i8 @llvm.x86.avx512.mask.fpclass.ps.256(<8 x float> %x0, i32 2, i8 %x1)
+  %res1 = call i8 @llvm.x86.avx512.mask.fpclass.ps.256(<8 x float> %x0, i32 4, i8 -1)
+  %res2 = add i8 %res, %res1
+  ret i8 %res2
+}
+
+declare i8 @llvm.x86.avx512.mask.fpclass.pd.128(<2 x double>, i32, i8)
+
+; CHECK-LABEL: @test_int_x86_avx512_mask_fpclass_pd_128
+; CHECK-NOT: call 
+; CHECK: kmov 
+; CHECK: vfpclasspd
+; CHECK: {%k1} 
+; CHECK: vfpclasspd
+; CHECK: kmovb   %k0
+define i8 @test_int_x86_avx512_mask_fpclass_pd_128(<2 x double> %x0, i8 %x1) {
+  %res =  call i8 @llvm.x86.avx512.mask.fpclass.pd.128(<2 x double> %x0, i32 4, i8 %x1)
+  %res1 = call i8 @llvm.x86.avx512.mask.fpclass.pd.128(<2 x double> %x0, i32 2, i8 -1)
+  %res2 = add i8 %res, %res1
+  ret i8 %res2
+}
+
+declare i8 @llvm.x86.avx512.mask.fpclass.pd.256(<4 x double>, i32, i8)
+
+; CHECK-LABEL: @test_int_x86_avx512_mask_fpclass_pd_256
+; CHECK-NOT: call 
+; CHECK: kmov 
+; CHECK: vfpclasspd
+; CHECK: {%k1} 
+; CHECK: vfpclasspd
+; CHECK: kmovb   %k0
+define i8 @test_int_x86_avx512_mask_fpclass_pd_256(<4 x double> %x0, i8 %x1) {
+  %res = call i8 @llvm.x86.avx512.mask.fpclass.pd.256(<4 x double> %x0, i32 2, i8 %x1)
+  %res1 = call i8 @llvm.x86.avx512.mask.fpclass.pd.256(<4 x double> %x0, i32 4, i8 -1)
+  %res2 = add i8 %res, %res1
+  ret i8 %res2
+}
 No newline at end of file

../commit/llvm/test/MC/X86/x86-64-avx512dq.s

 // CHECK: kaddw  %k4, %k3, %k2
 // CHECK:  encoding: [0xc5,0xe4,0x4a,0xd4]
           kaddw  %k4, %k3, %k2
 
 // CHECK: kaddw  %k6, %k6, %k2
 // CHECK:  encoding: [0xc5,0xcc,0x4a,0xd6]
           kaddw  %k6, %k6, %k2
 
+// CHECK: vfpclasspd $171, %zmm17, %k2
+// CHECK:  encoding: [0x62,0xb3,0xfd,0x48,0x66,0xd1,0xab]
+          vfpclasspd $0xab, %zmm17, %k2
+
+// CHECK: vfpclasspd $171, %zmm17, %k2 {%k1}
+// CHECK:  encoding: [0x62,0xb3,0xfd,0x49,0x66,0xd1,0xab]
+          vfpclasspd $0xab, %zmm17, %k2 {%k1}
+
+// CHECK: vfpclasspd $123,  %zmm17, %k2
+// CHECK:  encoding: [0x62,0xb3,0xfd,0x48,0x66,0xd1,0x7b]
+          vfpclasspd $0x7b, %zmm17, %k2
+
+// CHECK: vfpclasspdz $123, (%rcx), %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x48,0x66,0x11,0x7b]
+          vfpclasspdz $0x7b,(%rcx), %k2
+
+// CHECK: vfpclasspdz $123, 291(%rax,%r14,8), %k2
+// CHECK:  encoding: [0x62,0xb3,0xfd,0x48,0x66,0x94,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vfpclasspdz $0x7b,291(%rax,%r14,8), %k2
+
+// CHECK: vfpclasspdq $123, (%rcx){1to8}, %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x58,0x66,0x11,0x7b]
+          vfpclasspdq $0x7b,(%rcx){1to8}, %k2
+
+// CHECK: vfpclasspdz $123, 8128(%rdx), %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x48,0x66,0x52,0x7f,0x7b]
+          vfpclasspdz $0x7b,8128(%rdx), %k2
+
+// CHECK: vfpclasspdz $123, 8192(%rdx), %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x48,0x66,0x92,0x00,0x20,0x00,0x00,0x7b]
+          vfpclasspdz $0x7b,8192(%rdx), %k2
+
+// CHECK: vfpclasspdz $123, -8192(%rdx), %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x48,0x66,0x52,0x80,0x7b]
+          vfpclasspdz $0x7b,-8192(%rdx), %k2
+
+// CHECK: vfpclasspdz $123, -8256(%rdx), %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x48,0x66,0x92,0xc0,0xdf,0xff,0xff,0x7b]
+          vfpclasspdz $0x7b,-8256(%rdx), %k2
+
+// CHECK: vfpclasspdq $123, 1016(%rdx){1to8}, %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x58,0x66,0x52,0x7f,0x7b]
+          vfpclasspdq $0x7b,1016(%rdx){1to8}, %k2
+
+// CHECK: vfpclasspdq $123, 1024(%rdx){1to8}, %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x58,0x66,0x92,0x00,0x04,0x00,0x00,0x7b]
+          vfpclasspdq $0x7b,1024(%rdx){1to8}, %k2
+
+// CHECK: vfpclasspdq $123, -1024(%rdx){1to8}, %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x58,0x66,0x52,0x80,0x7b]
+          vfpclasspdq $0x7b,-1024(%rdx){1to8}, %k2
+
+// CHECK: vfpclasspdq $123, -1032(%rdx){1to8}, %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x58,0x66,0x92,0xf8,0xfb,0xff,0xff,0x7b]
+          vfpclasspdq $0x7b,-1032(%rdx){1to8}, %k2
+
+// CHECK: vfpclassps $171, %zmm21, %k2
+// CHECK:  encoding: [0x62,0xb3,0x7d,0x48,0x66,0xd5,0xab]
+          vfpclassps $0xab, %zmm21, %k2
+
+// CHECK: vfpclassps $171, %zmm21, %k2 {%k2}
+// CHECK:  encoding: [0x62,0xb3,0x7d,0x4a,0x66,0xd5,0xab]
+          vfpclassps $0xab, %zmm21, %k2 {%k2}
+
+// CHECK: vfpclassps $123,  %zmm21, %k2
+// CHECK:  encoding: [0x62,0xb3,0x7d,0x48,0x66,0xd5,0x7b]
+          vfpclassps $0x7b, %zmm21, %k2
+
+// CHECK: vfpclasspsz $123, (%rcx), %k2
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x48,0x66,0x11,0x7b]
+          vfpclasspsz $0x7b,(%rcx), %k2
+
+// CHECK: vfpclasspsz $123, 291(%rax,%r14,8), %k2
+// CHECK:  encoding: [0x62,0xb3,0x7d,0x48,0x66,0x94,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vfpclasspsz $0x7b,291(%rax,%r14,8), %k2
+
+// CHECK: vfpclasspsl $123, (%rcx){1to16}, %k2
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x58,0x66,0x11,0x7b]
+          vfpclasspsl $0x7b,(%rcx){1to16}, %k2
+
+// CHECK: vfpclasspsz $123, 8128(%rdx), %k2
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x48,0x66,0x52,0x7f,0x7b]
+          vfpclasspsz $0x7b,8128(%rdx), %k2
+
+// CHECK: vfpclasspsz $123, 8192(%rdx), %k2
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x48,0x66,0x92,0x00,0x20,0x00,0x00,0x7b]
+          vfpclasspsz $0x7b,8192(%rdx), %k2
+
+// CHECK: vfpclasspsz $123, -8192(%rdx), %k2
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x48,0x66,0x52,0x80,0x7b]
+          vfpclasspsz $0x7b,-8192(%rdx), %k2
+
+// CHECK: vfpclasspsz $123, -8256(%rdx), %k2
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x48,0x66,0x92,0xc0,0xdf,0xff,0xff,0x7b]
+          vfpclasspsz $0x7b,-8256(%rdx), %k2
+
+// CHECK: vfpclasspsl $123, 508(%rdx){1to16}, %k2
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x58,0x66,0x52,0x7f,0x7b]
+          vfpclasspsl $0x7b,508(%rdx){1to16}, %k2
+
+// CHECK: vfpclasspsl $123, 512(%rdx){1to16}, %k2
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x58,0x66,0x92,0x00,0x02,0x00,0x00,0x7b]
+          vfpclasspsl $0x7b,512(%rdx){1to16}, %k2
+
+// CHECK: vfpclasspsl $123, -512(%rdx){1to16}, %k2
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x58,0x66,0x52,0x80,0x7b]
+          vfpclasspsl $0x7b,-512(%rdx){1to16}, %k2
+
+// CHECK: vfpclasspsl $123, -516(%rdx){1to16}, %k2
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x58,0x66,0x92,0xfc,0xfd,0xff,0xff,0x7b]
+          vfpclasspsl $0x7b,-516(%rdx){1to16}, %k2
+
+// CHECK: vfpclasspd $171, %zmm19, %k2
+// CHECK:  encoding: [0x62,0xb3,0xfd,0x48,0x66,0xd3,0xab]
+          vfpclasspd $0xab, %zmm19, %k2
+
+// CHECK: vfpclasspd $171, %zmm19, %k2 {%k6}
+// CHECK:  encoding: [0x62,0xb3,0xfd,0x4e,0x66,0xd3,0xab]
+          vfpclasspd $0xab, %zmm19, %k2 {%k6}
+
+// CHECK: vfpclasspd $123,  %zmm19, %k2
+// CHECK:  encoding: [0x62,0xb3,0xfd,0x48,0x66,0xd3,0x7b]
+          vfpclasspd $0x7b, %zmm19, %k2
+
+// CHECK: vfpclasspdz $123, (%rcx), %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x48,0x66,0x11,0x7b]
+          vfpclasspdz $0x7b,(%rcx), %k2
+
+// CHECK: vfpclasspdz $123, 4660(%rax,%r14,8), %k2
+// CHECK:  encoding: [0x62,0xb3,0xfd,0x48,0x66,0x94,0xf0,0x34,0x12,0x00,0x00,0x7b]
+          vfpclasspdz $0x7b,4660(%rax,%r14,8), %k2
+
+// CHECK: vfpclasspdq $123, (%rcx){1to8}, %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x58,0x66,0x11,0x7b]
+          vfpclasspdq $0x7b,(%rcx){1to8}, %k2
+
+// CHECK: vfpclasspdz $123, 8128(%rdx), %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x48,0x66,0x52,0x7f,0x7b]
+          vfpclasspdz $0x7b,8128(%rdx), %k2
+
+// CHECK: vfpclasspdz $123, 8192(%rdx), %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x48,0x66,0x92,0x00,0x20,0x00,0x00,0x7b]
+          vfpclasspdz $0x7b,8192(%rdx), %k2
+
+// CHECK: vfpclasspdz $123, -8192(%rdx), %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x48,0x66,0x52,0x80,0x7b]
+          vfpclasspdz $0x7b,-8192(%rdx), %k2
+
+// CHECK: vfpclasspdz $123, -8256(%rdx), %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x48,0x66,0x92,0xc0,0xdf,0xff,0xff,0x7b]
+          vfpclasspdz $0x7b,-8256(%rdx), %k2
+
+// CHECK: vfpclasspdq $123, 1016(%rdx){1to8}, %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x58,0x66,0x52,0x7f,0x7b]
+          vfpclasspdq $0x7b,1016(%rdx){1to8}, %k2
+
+// CHECK: vfpclasspdq $123, 1024(%rdx){1to8}, %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x58,0x66,0x92,0x00,0x04,0x00,0x00,0x7b]
+          vfpclasspdq $0x7b,1024(%rdx){1to8}, %k2
+
+// CHECK: vfpclasspdq $123, -1024(%rdx){1to8}, %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x58,0x66,0x52,0x80,0x7b]
+          vfpclasspdq $0x7b,-1024(%rdx){1to8}, %k2
+
+// CHECK: vfpclasspdq $123, -1032(%rdx){1to8}, %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x58,0x66,0x92,0xf8,0xfb,0xff,0xff,0x7b]
+          vfpclasspdq $0x7b,-1032(%rdx){1to8}, %k2
+
+// CHECK: vfpclassps $171, %zmm17, %k4
+// CHECK:  encoding: [0x62,0xb3,0x7d,0x48,0x66,0xe1,0xab]
+          vfpclassps $0xab, %zmm17, %k4
+
+// CHECK: vfpclassps $171, %zmm17, %k4 {%k2}
+// CHECK:  encoding: [0x62,0xb3,0x7d,0x4a,0x66,0xe1,0xab]
+          vfpclassps $0xab, %zmm17, %k4 {%k2}
+
+// CHECK: vfpclassps $123,  %zmm17, %k4
+// CHECK:  encoding: [0x62,0xb3,0x7d,0x48,0x66,0xe1,0x7b]
+          vfpclassps $0x7b, %zmm17, %k4
+
+// CHECK: vfpclasspsz $123, (%rcx), %k4
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x48,0x66,0x21,0x7b]
+          vfpclasspsz $0x7b,(%rcx), %k4
+
+// CHECK: vfpclasspsz $123, 4660(%rax,%r14,8), %k4
+// CHECK:  encoding: [0x62,0xb3,0x7d,0x48,0x66,0xa4,0xf0,0x34,0x12,0x00,0x00,0x7b]
+          vfpclasspsz $0x7b,4660(%rax,%r14,8), %k4
+
+// CHECK: vfpclasspsl $123, (%rcx){1to16}, %k4
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x58,0x66,0x21,0x7b]
+          vfpclasspsl $0x7b,(%rcx){1to16}, %k4
+
+// CHECK: vfpclasspsz $123, 8128(%rdx), %k4
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x48,0x66,0x62,0x7f,0x7b]
+          vfpclasspsz $0x7b,8128(%rdx), %k4
+
+// CHECK: vfpclasspsz $123, 8192(%rdx), %k4
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x48,0x66,0xa2,0x00,0x20,0x00,0x00,0x7b]
+          vfpclasspsz $0x7b,8192(%rdx), %k4
+
+// CHECK: vfpclasspsz $123, -8192(%rdx), %k4
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x48,0x66,0x62,0x80,0x7b]
+          vfpclasspsz $0x7b,-8192(%rdx), %k4
+
+// CHECK: vfpclasspsz $123, -8256(%rdx), %k4
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x48,0x66,0xa2,0xc0,0xdf,0xff,0xff,0x7b]
+          vfpclasspsz $0x7b,-8256(%rdx), %k4
+
+// CHECK: vfpclasspsl $123, 508(%rdx){1to16}, %k4
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x58,0x66,0x62,0x7f,0x7b]
+          vfpclasspsl $0x7b,508(%rdx){1to16}, %k4
+
+// CHECK: vfpclasspsl $123, 512(%rdx){1to16}, %k4
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x58,0x66,0xa2,0x00,0x02,0x00,0x00,0x7b]
+          vfpclasspsl $0x7b,512(%rdx){1to16}, %k4
+
+// CHECK: vfpclasspsl $123, -512(%rdx){1to16}, %k4
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x58,0x66,0x62,0x80,0x7b]
+          vfpclasspsl $0x7b,-512(%rdx){1to16}, %k4
+
+// CHECK: vfpclasspsl $123, -516(%rdx){1to16}, %k4
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x58,0x66,0xa2,0xfc,0xfd,0xff,0xff,0x7b]
+          vfpclasspsl $0x7b,-516(%rdx){1to16}, %k4
+
+

../commit/llvm/test/MC/X86/x86-64-avx512dq_vl.s

 // CHECK: vextracti64x2 $123, %ymm20, -2048(%rdx)
 // CHECK:  encoding: [0x62,0xe3,0xfd,0x28,0x39,0x62,0x80,0x7b]
           vextracti64x2 $0x7b, %ymm20,-2048(%rdx)
 
 // CHECK: vextracti64x2 $123, %ymm20, -2064(%rdx)
 // CHECK:  encoding: [0x62,0xe3,0xfd,0x28,0x39,0xa2,0xf0,0xf7,0xff,0xff,0x7b]
           vextracti64x2 $0x7b, %ymm20,-2064(%rdx)
 
+// CHECK: vfpclasspd $171, %xmm18, %k2
+// CHECK:  encoding: [0x62,0xb3,0xfd,0x08,0x66,0xd2,0xab]
+          vfpclasspd $0xab, %xmm18, %k2
+
+// CHECK: vfpclasspd $171, %xmm18, %k2 {%k7}
+// CHECK:  encoding: [0x62,0xb3,0xfd,0x0f,0x66,0xd2,0xab]
+          vfpclasspd $0xab, %xmm18, %k2 {%k7}
+
+// CHECK: vfpclasspd $123,  %xmm18, %k2
+// CHECK:  encoding: [0x62,0xb3,0xfd,0x08,0x66,0xd2,0x7b]
+          vfpclasspd $0x7b, %xmm18, %k2
+
+// CHECK: vfpclasspdx $123, (%rcx), %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x08,0x66,0x11,0x7b]
+          vfpclasspdx $0x7b,(%rcx), %k2
+
+// CHECK: vfpclasspdx $123, 291(%rax,%r14,8), %k2
+// CHECK:  encoding: [0x62,0xb3,0xfd,0x08,0x66,0x94,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vfpclasspdx $0x7b,291(%rax,%r14,8), %k2
+
+// CHECK: vfpclasspdq $123, (%rcx){1to2}, %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x18,0x66,0x11,0x7b]
+          vfpclasspdq $0x7b,(%rcx){1to2}, %k2
+
+// CHECK: vfpclasspdx $123, 2032(%rdx), %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x08,0x66,0x52,0x7f,0x7b]
+          vfpclasspdx $0x7b,2032(%rdx), %k2
+
+// CHECK: vfpclasspdx $123, 2048(%rdx), %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x08,0x66,0x92,0x00,0x08,0x00,0x00,0x7b]
+          vfpclasspdx $0x7b,2048(%rdx), %k2
+
+// CHECK: vfpclasspdx $123, -2048(%rdx), %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x08,0x66,0x52,0x80,0x7b]
+          vfpclasspdx $0x7b,-2048(%rdx), %k2
+
+// CHECK: vfpclasspdx $123, -2064(%rdx), %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x08,0x66,0x92,0xf0,0xf7,0xff,0xff,0x7b]
+          vfpclasspdx $0x7b,-2064(%rdx), %k2
+
+// CHECK: vfpclasspdq $123, 1016(%rdx){1to2}, %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x18,0x66,0x52,0x7f,0x7b]
+          vfpclasspdq $0x7b,1016(%rdx){1to2}, %k2
+
+// CHECK: vfpclasspdq $123, 1024(%rdx){1to2}, %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x18,0x66,0x92,0x00,0x04,0x00,0x00,0x7b]
+          vfpclasspdq $0x7b,1024(%rdx){1to2}, %k2
+
+// CHECK: vfpclasspdq $123, -1024(%rdx){1to2}, %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x18,0x66,0x52,0x80,0x7b]
+          vfpclasspdq $0x7b,-1024(%rdx){1to2}, %k2
+
+// CHECK: vfpclasspdq $123, -1032(%rdx){1to2}, %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x18,0x66,0x92,0xf8,0xfb,0xff,0xff,0x7b]
+          vfpclasspdq $0x7b,-1032(%rdx){1to2}, %k2
+
+// CHECK: vfpclasspd $171, %ymm25, %k4
+// CHECK:  encoding: [0x62,0x93,0xfd,0x28,0x66,0xe1,0xab]
+          vfpclasspd $0xab, %ymm25, %k4
+
+// CHECK: vfpclasspd $171, %ymm25, %k4 {%k6}
+// CHECK:  encoding: [0x62,0x93,0xfd,0x2e,0x66,0xe1,0xab]
+          vfpclasspd $0xab, %ymm25, %k4 {%k6}
+
+// CHECK: vfpclasspd $123,  %ymm25, %k4
+// CHECK:  encoding: [0x62,0x93,0xfd,0x28,0x66,0xe1,0x7b]
+          vfpclasspd $0x7b, %ymm25, %k4
+
+// CHECK: vfpclasspdy $123, (%rcx), %k4
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x28,0x66,0x21,0x7b]
+          vfpclasspdy $0x7b,(%rcx), %k4
+
+// CHECK: vfpclasspdy $123, 291(%rax,%r14,8), %k4
+// CHECK:  encoding: [0x62,0xb3,0xfd,0x28,0x66,0xa4,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vfpclasspdy $0x7b,291(%rax,%r14,8), %k4
+
+// CHECK: vfpclasspdq $123, (%rcx){1to4}, %k4
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x38,0x66,0x21,0x7b]
+          vfpclasspdq $0x7b,(%rcx){1to4}, %k4
+
+// CHECK: vfpclasspdy $123, 4064(%rdx), %k4
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x28,0x66,0x62,0x7f,0x7b]
+          vfpclasspdy $0x7b,4064(%rdx), %k4
+
+// CHECK: vfpclasspdy $123, 4096(%rdx), %k4
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x28,0x66,0xa2,0x00,0x10,0x00,0x00,0x7b]
+          vfpclasspdy $0x7b,4096(%rdx), %k4
+
+// CHECK: vfpclasspdy $123, -4096(%rdx), %k4
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x28,0x66,0x62,0x80,0x7b]
+          vfpclasspdy $0x7b,-4096(%rdx), %k4
+
+// CHECK: vfpclasspdy $123, -4128(%rdx), %k4
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x28,0x66,0xa2,0xe0,0xef,0xff,0xff,0x7b]
+          vfpclasspdy $0x7b,-4128(%rdx), %k4
+
+// CHECK: vfpclasspdq $123, 1016(%rdx){1to4}, %k4
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x38,0x66,0x62,0x7f,0x7b]
+          vfpclasspdq $0x7b,1016(%rdx){1to4}, %k4
+
+// CHECK: vfpclasspdq $123, 1024(%rdx){1to4}, %k4
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x38,0x66,0xa2,0x00,0x04,0x00,0x00,0x7b]
+          vfpclasspdq $0x7b,1024(%rdx){1to4}, %k4
+
+// CHECK: vfpclasspdq $123, -1024(%rdx){1to4}, %k4
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x38,0x66,0x62,0x80,0x7b]
+          vfpclasspdq $0x7b,-1024(%rdx){1to4}, %k4
+
+// CHECK: vfpclasspdq $123, -1032(%rdx){1to4}, %k4
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x38,0x66,0xa2,0xf8,0xfb,0xff,0xff,0x7b]
+          vfpclasspdq $0x7b,-1032(%rdx){1to4}, %k4
+
+// CHECK: vfpclassps $171, %xmm20, %k4
+// CHECK:  encoding: [0x62,0xb3,0x7d,0x08,0x66,0xe4,0xab]
+          vfpclassps $0xab, %xmm20, %k4
+
+// CHECK: vfpclassps $171, %xmm20, %k4 {%k5}
+// CHECK:  encoding: [0x62,0xb3,0x7d,0x0d,0x66,0xe4,0xab]
+          vfpclassps $0xab, %xmm20, %k4 {%k5}
+
+// CHECK: vfpclassps $123,  %xmm20, %k4
+// CHECK:  encoding: [0x62,0xb3,0x7d,0x08,0x66,0xe4,0x7b]
+          vfpclassps $0x7b, %xmm20, %k4
+
+// CHECK: vfpclasspsx $123, (%rcx), %k4
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x08,0x66,0x21,0x7b]
+          vfpclasspsx $0x7b,(%rcx), %k4
+
+// CHECK: vfpclasspsx $123, 291(%rax,%r14,8), %k4
+// CHECK:  encoding: [0x62,0xb3,0x7d,0x08,0x66,0xa4,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vfpclasspsx $0x7b,291(%rax,%r14,8), %k4
+
+// CHECK: vfpclasspsl $123, (%rcx){1to4}, %k4
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x18,0x66,0x21,0x7b]
+          vfpclasspsl $0x7b,(%rcx){1to4}, %k4
+
+// CHECK: vfpclasspsx $123, 2032(%rdx), %k4
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x08,0x66,0x62,0x7f,0x7b]
+          vfpclasspsx $0x7b,2032(%rdx), %k4
+
+// CHECK: vfpclasspsx $123, 2048(%rdx), %k4
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x08,0x66,0xa2,0x00,0x08,0x00,0x00,0x7b]
+          vfpclasspsx $0x7b,2048(%rdx), %k4
+
+// CHECK: vfpclasspsx $123, -2048(%rdx), %k4
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x08,0x66,0x62,0x80,0x7b]
+          vfpclasspsx $0x7b,-2048(%rdx), %k4
+
+// CHECK: vfpclasspsx $123, -2064(%rdx), %k4
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x08,0x66,0xa2,0xf0,0xf7,0xff,0xff,0x7b]
+          vfpclasspsx $0x7b,-2064(%rdx), %k4
+
+// CHECK: vfpclasspsl $123, 508(%rdx){1to4}, %k4
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x18,0x66,0x62,0x7f,0x7b]
+          vfpclasspsl $0x7b,508(%rdx){1to4}, %k4
+
+// CHECK: vfpclasspsl $123, 512(%rdx){1to4}, %k4
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x18,0x66,0xa2,0x00,0x02,0x00,0x00,0x7b]
+          vfpclasspsl $0x7b,512(%rdx){1to4}, %k4
+
+// CHECK: vfpclasspsl $123, -512(%rdx){1to4}, %k4
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x18,0x66,0x62,0x80,0x7b]
+          vfpclasspsl $0x7b,-512(%rdx){1to4}, %k4
+
+// CHECK: vfpclasspsl $123, -516(%rdx){1to4}, %k4
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x18,0x66,0xa2,0xfc,0xfd,0xff,0xff,0x7b]
+          vfpclasspsl $0x7b,-516(%rdx){1to4}, %k4
+
+// CHECK: vfpclassps $171, %ymm17, %k4
+// CHECK:  encoding: [0x62,0xb3,0x7d,0x28,0x66,0xe1,0xab]
+          vfpclassps $0xab, %ymm17, %k4
+
+// CHECK: vfpclassps $171, %ymm17, %k4 {%k5}
+// CHECK:  encoding: [0x62,0xb3,0x7d,0x2d,0x66,0xe1,0xab]
+          vfpclassps $0xab, %ymm17, %k4 {%k5}
+
+// CHECK: vfpclassps $123,  %ymm17, %k4
+// CHECK:  encoding: [0x62,0xb3,0x7d,0x28,0x66,0xe1,0x7b]
+          vfpclassps $0x7b, %ymm17, %k4
+
+// CHECK: vfpclasspsy $123, (%rcx), %k4
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x28,0x66,0x21,0x7b]
+          vfpclasspsy $0x7b,(%rcx), %k4
+
+// CHECK: vfpclasspsy $123, 291(%rax,%r14,8), %k4
+// CHECK:  encoding: [0x62,0xb3,0x7d,0x28,0x66,0xa4,0xf0,0x23,0x01,0x00,0x00,0x7b]
+          vfpclasspsy $0x7b,291(%rax,%r14,8), %k4
+
+// CHECK: vfpclasspsl $123, (%rcx){1to8}, %k4
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x38,0x66,0x21,0x7b]
+          vfpclasspsl $0x7b,(%rcx){1to8}, %k4
+
+// CHECK: vfpclasspsy $123, 4064(%rdx), %k4
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x28,0x66,0x62,0x7f,0x7b]
+          vfpclasspsy $0x7b,4064(%rdx), %k4
+
+// CHECK: vfpclasspsy $123, 4096(%rdx), %k4
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x28,0x66,0xa2,0x00,0x10,0x00,0x00,0x7b]
+          vfpclasspsy $0x7b,4096(%rdx), %k4
+
+// CHECK: vfpclasspsy $123, -4096(%rdx), %k4
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x28,0x66,0x62,0x80,0x7b]
+          vfpclasspsy $0x7b,-4096(%rdx), %k4
+
+// CHECK: vfpclasspsy $123, -4128(%rdx), %k4
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x28,0x66,0xa2,0xe0,0xef,0xff,0xff,0x7b]
+          vfpclasspsy $0x7b,-4128(%rdx), %k4
+
+// CHECK: vfpclasspsl $123, 508(%rdx){1to8}, %k4
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x38,0x66,0x62,0x7f,0x7b]
+          vfpclasspsl $0x7b,508(%rdx){1to8}, %k4
+
+// CHECK: vfpclasspsl $123, 512(%rdx){1to8}, %k4
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x38,0x66,0xa2,0x00,0x02,0x00,0x00,0x7b]
+          vfpclasspsl $0x7b,512(%rdx){1to8}, %k4
+
+// CHECK: vfpclasspsl $123, -512(%rdx){1to8}, %k4
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x38,0x66,0x62,0x80,0x7b]
+          vfpclasspsl $0x7b,-512(%rdx){1to8}, %k4
+
+// CHECK: vfpclasspsl $123, -516(%rdx){1to8}, %k4
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x38,0x66,0xa2,0xfc,0xfd,0xff,0xff,0x7b]
+          vfpclasspsl $0x7b,-516(%rdx){1to8}, %k4
+
+// CHECK: vfpclasspd $171, %xmm26, %k3
+// CHECK:  encoding: [0x62,0x93,0xfd,0x08,0x66,0xda,0xab]
+          vfpclasspd $0xab, %xmm26, %k3
+
+// CHECK: vfpclasspd $171, %xmm26, %k3 {%k5}
+// CHECK:  encoding: [0x62,0x93,0xfd,0x0d,0x66,0xda,0xab]
+          vfpclasspd $0xab, %xmm26, %k3 {%k5}
+
+// CHECK: vfpclasspd $123,  %xmm26, %k3
+// CHECK:  encoding: [0x62,0x93,0xfd,0x08,0x66,0xda,0x7b]
+          vfpclasspd $0x7b, %xmm26, %k3
+
+// CHECK: vfpclasspdx $123, (%rcx), %k3
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x08,0x66,0x19,0x7b]
+          vfpclasspdx $0x7b,(%rcx), %k3
+
+// CHECK: vfpclasspdx $123, 4660(%rax,%r14,8), %k3
+// CHECK:  encoding: [0x62,0xb3,0xfd,0x08,0x66,0x9c,0xf0,0x34,0x12,0x00,0x00,0x7b]
+          vfpclasspdx $0x7b,4660(%rax,%r14,8), %k3
+
+// CHECK: vfpclasspdq $123, (%rcx){1to2}, %k3
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x18,0x66,0x19,0x7b]
+          vfpclasspdq $0x7b,(%rcx){1to2}, %k3
+
+// CHECK: vfpclasspdx $123, 2032(%rdx), %k3
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x08,0x66,0x5a,0x7f,0x7b]
+          vfpclasspdx $0x7b,2032(%rdx), %k3
+
+// CHECK: vfpclasspdx $123, 2048(%rdx), %k3
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x08,0x66,0x9a,0x00,0x08,0x00,0x00,0x7b]
+          vfpclasspdx $0x7b,2048(%rdx), %k3
+
+// CHECK: vfpclasspdx $123, -2048(%rdx), %k3
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x08,0x66,0x5a,0x80,0x7b]
+          vfpclasspdx $0x7b,-2048(%rdx), %k3
+
+// CHECK: vfpclasspdx $123, -2064(%rdx), %k3
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x08,0x66,0x9a,0xf0,0xf7,0xff,0xff,0x7b]
+          vfpclasspdx $0x7b,-2064(%rdx), %k3
+
+// CHECK: vfpclasspdq $123, 1016(%rdx){1to2}, %k3
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x18,0x66,0x5a,0x7f,0x7b]
+          vfpclasspdq $0x7b,1016(%rdx){1to2}, %k3
+
+// CHECK: vfpclasspdq $123, 1024(%rdx){1to2}, %k3
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x18,0x66,0x9a,0x00,0x04,0x00,0x00,0x7b]
+          vfpclasspdq $0x7b,1024(%rdx){1to2}, %k3
+
+// CHECK: vfpclasspdq $123, -1024(%rdx){1to2}, %k3
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x18,0x66,0x5a,0x80,0x7b]
+          vfpclasspdq $0x7b,-1024(%rdx){1to2}, %k3
+
+// CHECK: vfpclasspdq $123, -1032(%rdx){1to2}, %k3
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x18,0x66,0x9a,0xf8,0xfb,0xff,0xff,0x7b]
+          vfpclasspdq $0x7b,-1032(%rdx){1to2}, %k3
+
+// CHECK: vfpclasspd $171, %ymm26, %k2
+// CHECK:  encoding: [0x62,0x93,0xfd,0x28,0x66,0xd2,0xab]
+          vfpclasspd $0xab, %ymm26, %k2
+
+// CHECK: vfpclasspd $171, %ymm26, %k2 {%k6}
+// CHECK:  encoding: [0x62,0x93,0xfd,0x2e,0x66,0xd2,0xab]
+          vfpclasspd $0xab, %ymm26, %k2 {%k6}
+
+// CHECK: vfpclasspd $123,  %ymm26, %k2
+// CHECK:  encoding: [0x62,0x93,0xfd,0x28,0x66,0xd2,0x7b]
+          vfpclasspd $0x7b, %ymm26, %k2
+
+// CHECK: vfpclasspdy $123, (%rcx), %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x28,0x66,0x11,0x7b]
+          vfpclasspdy $0x7b,(%rcx), %k2
+
+// CHECK: vfpclasspdy $123, 4660(%rax,%r14,8), %k2
+// CHECK:  encoding: [0x62,0xb3,0xfd,0x28,0x66,0x94,0xf0,0x34,0x12,0x00,0x00,0x7b]
+          vfpclasspdy $0x7b,4660(%rax,%r14,8), %k2
+
+// CHECK: vfpclasspdq $123, (%rcx){1to4}, %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x38,0x66,0x11,0x7b]
+          vfpclasspdq $0x7b,(%rcx){1to4}, %k2
+
+// CHECK: vfpclasspdy $123, 4064(%rdx), %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x28,0x66,0x52,0x7f,0x7b]
+          vfpclasspdy $0x7b,4064(%rdx), %k2
+
+// CHECK: vfpclasspdy $123, 4096(%rdx), %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x28,0x66,0x92,0x00,0x10,0x00,0x00,0x7b]
+          vfpclasspdy $0x7b,4096(%rdx), %k2
+
+// CHECK: vfpclasspdy $123, -4096(%rdx), %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x28,0x66,0x52,0x80,0x7b]
+          vfpclasspdy $0x7b,-4096(%rdx), %k2
+
+// CHECK: vfpclasspdy $123, -4128(%rdx), %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x28,0x66,0x92,0xe0,0xef,0xff,0xff,0x7b]
+          vfpclasspdy $0x7b,-4128(%rdx), %k2
+
+// CHECK: vfpclasspdq $123, 1016(%rdx){1to4}, %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x38,0x66,0x52,0x7f,0x7b]
+          vfpclasspdq $0x7b,1016(%rdx){1to4}, %k2
+
+// CHECK: vfpclasspdq $123, 1024(%rdx){1to4}, %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x38,0x66,0x92,0x00,0x04,0x00,0x00,0x7b]
+          vfpclasspdq $0x7b,1024(%rdx){1to4}, %k2
+
+// CHECK: vfpclasspdq $123, -1024(%rdx){1to4}, %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x38,0x66,0x52,0x80,0x7b]
+          vfpclasspdq $0x7b,-1024(%rdx){1to4}, %k2
+
+// CHECK: vfpclasspdq $123, -1032(%rdx){1to4}, %k2
+// CHECK:  encoding: [0x62,0xf3,0xfd,0x38,0x66,0x92,0xf8,0xfb,0xff,0xff,0x7b]
+          vfpclasspdq $0x7b,-1032(%rdx){1to4}, %k2
+
+// CHECK: vfpclassps $171, %xmm29, %k3
+// CHECK:  encoding: [0x62,0x93,0x7d,0x08,0x66,0xdd,0xab]
+          vfpclassps $0xab, %xmm29, %k3
+
+// CHECK: vfpclassps $171, %xmm29, %k3 {%k6}
+// CHECK:  encoding: [0x62,0x93,0x7d,0x0e,0x66,0xdd,0xab]
+          vfpclassps $0xab, %xmm29, %k3 {%k6}
+
+// CHECK: vfpclassps $123,  %xmm29, %k3
+// CHECK:  encoding: [0x62,0x93,0x7d,0x08,0x66,0xdd,0x7b]
+          vfpclassps $0x7b, %xmm29, %k3
+
+// CHECK: vfpclasspsx $123, (%rcx), %k3
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x08,0x66,0x19,0x7b]
+          vfpclasspsx $0x7b,(%rcx), %k3
+
+// CHECK: vfpclasspsx $123, 4660(%rax,%r14,8), %k3
+// CHECK:  encoding: [0x62,0xb3,0x7d,0x08,0x66,0x9c,0xf0,0x34,0x12,0x00,0x00,0x7b]
+          vfpclasspsx $0x7b,4660(%rax,%r14,8), %k3
+
+// CHECK: vfpclasspsl $123, (%rcx){1to4}, %k3
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x18,0x66,0x19,0x7b]
+          vfpclasspsl $0x7b,(%rcx){1to4}, %k3
+
+// CHECK: vfpclasspsx $123, 2032(%rdx), %k3
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x08,0x66,0x5a,0x7f,0x7b]
+          vfpclasspsx $0x7b,2032(%rdx), %k3
+
+// CHECK: vfpclasspsx $123, 2048(%rdx), %k3
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x08,0x66,0x9a,0x00,0x08,0x00,0x00,0x7b]
+          vfpclasspsx $0x7b,2048(%rdx), %k3
+
+// CHECK: vfpclasspsx $123, -2048(%rdx), %k3
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x08,0x66,0x5a,0x80,0x7b]
+          vfpclasspsx $0x7b,-2048(%rdx), %k3
+
+// CHECK: vfpclasspsx $123, -2064(%rdx), %k3
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x08,0x66,0x9a,0xf0,0xf7,0xff,0xff,0x7b]
+          vfpclasspsx $0x7b,-2064(%rdx), %k3
+
+// CHECK: vfpclasspsl $123, 508(%rdx){1to4}, %k3
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x18,0x66,0x5a,0x7f,0x7b]
+          vfpclasspsl $0x7b,508(%rdx){1to4}, %k3
+
+// CHECK: vfpclasspsl $123, 512(%rdx){1to4}, %k3
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x18,0x66,0x9a,0x00,0x02,0x00,0x00,0x7b]
+          vfpclasspsl $0x7b,512(%rdx){1to4}, %k3
+
+// CHECK: vfpclasspsl $123, -512(%rdx){1to4}, %k3
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x18,0x66,0x5a,0x80,0x7b]
+          vfpclasspsl $0x7b,-512(%rdx){1to4}, %k3
+
+// CHECK: vfpclasspsl $123, -516(%rdx){1to4}, %k3
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x18,0x66,0x9a,0xfc,0xfd,0xff,0xff,0x7b]
+          vfpclasspsl $0x7b,-516(%rdx){1to4}, %k3
+
+// CHECK: vfpclassps $171, %ymm19, %k3
+// CHECK:  encoding: [0x62,0xb3,0x7d,0x28,0x66,0xdb,0xab]
+          vfpclassps $0xab, %ymm19, %k3
+
+// CHECK: vfpclassps $171, %ymm19, %k3 {%k3}
+// CHECK:  encoding: [0x62,0xb3,0x7d,0x2b,0x66,0xdb,0xab]
+          vfpclassps $0xab, %ymm19, %k3 {%k3}
+
+// CHECK: vfpclassps $123,  %ymm19, %k3
+// CHECK:  encoding: [0x62,0xb3,0x7d,0x28,0x66,0xdb,0x7b]
+          vfpclassps $0x7b, %ymm19, %k3
+
+// CHECK: vfpclasspsy $123, (%rcx), %k3
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x28,0x66,0x19,0x7b]
+          vfpclasspsy $0x7b,(%rcx), %k3
+
+// CHECK: vfpclasspsy $123, 4660(%rax,%r14,8), %k3
+// CHECK:  encoding: [0x62,0xb3,0x7d,0x28,0x66,0x9c,0xf0,0x34,0x12,0x00,0x00,0x7b]
+          vfpclasspsy $0x7b,4660(%rax,%r14,8), %k3
+
+// CHECK: vfpclasspsl $123, (%rcx){1to8}, %k3
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x38,0x66,0x19,0x7b]
+          vfpclasspsl $0x7b,(%rcx){1to8}, %k3
+
+// CHECK: vfpclasspsy $123, 4064(%rdx), %k3
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x28,0x66,0x5a,0x7f,0x7b]
+          vfpclasspsy $0x7b,4064(%rdx), %k3
+
+// CHECK: vfpclasspsy $123, 4096(%rdx), %k3
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x28,0x66,0x9a,0x00,0x10,0x00,0x00,0x7b]
+          vfpclasspsy $0x7b,4096(%rdx), %k3
+
+// CHECK: vfpclasspsy $123, -4096(%rdx), %k3
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x28,0x66,0x5a,0x80,0x7b]
+          vfpclasspsy $0x7b,-4096(%rdx), %k3
+
+// CHECK: vfpclasspsy $123, -4128(%rdx), %k3
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x28,0x66,0x9a,0xe0,0xef,0xff,0xff,0x7b]
+          vfpclasspsy $0x7b,-4128(%rdx), %k3
+
+// CHECK: vfpclasspsl $123, 508(%rdx){1to8}, %k3
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x38,0x66,0x5a,0x7f,0x7b]
+          vfpclasspsl $0x7b,508(%rdx){1to8}, %k3
+
+// CHECK: vfpclasspsl $123, 512(%rdx){1to8}, %k3
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x38,0x66,0x9a,0x00,0x02,0x00,0x00,0x7b]
+          vfpclasspsl $0x7b,512(%rdx){1to8}, %k3
+
+// CHECK: vfpclasspsl $123, -512(%rdx){1to8}, %k3
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x38,0x66,0x5a,0x80,0x7b]
+          vfpclasspsl $0x7b,-512(%rdx){1to8}, %k3
+
+// CHECK: vfpclasspsl $123, -516(%rdx){1to8}, %k3
+// CHECK:  encoding: [0x62,0xf3,0x7d,0x38,0x66,0x9a,0xfc,0xfd,0xff,0xff,0x7b]
+          vfpclasspsl $0x7b,-516(%rdx){1to8}, %k3