AArch64 Watchpoints: Make sure we are only setting supported no of debug registers.

[omjavaid]

Summary

This patch makes sure that we are setting the correct number of hardware breakpoint or watchpoint registers while setting/clearing hardware watchpoints/breakpoints.

In current implementation of AArch64 Watchpoints we try to set all debug registers present in user_hwdebug_state structure.

There are more debug registers declared by user_hwdebug_state than the one exported to ptrace for hardware watchpoints and hardware breakpoints.

We only should be setting the N number of registers supported by the target in response to read debug registers calls.

Failure to do so results in unexpected watchpoint behavior.

[tberghammer]

source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp

820–821 ↗

(On Diff #33671)

You are using offsetof with a value determined in runtime (m_max_hwp_supported) what won't be work in all case (it isn't standard compliance AFAIK). I suggest to sue the following version instead:

ioVec.iov_len = (offsetof (struct user_hwdebug_state, dbg_regs) + sizeof (dreg_state.dbg_regs [0]) * m_max_hwp_supported);

[omjavaid]

This patch fixes unexpected behaviour of watchpoint code on Nexus 9 (AArch64).

[tberghammer]

LGTM

lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp

 NativeRegisterContextLinux_arm64::WriteHardwareDebugRegs(int hwbType)
 {
     struct iovec ioVec;
     struct user_hwdebug_state dreg_state;
     Error error;
 
     memset (&dreg_state, 0, sizeof (dreg_state));
     ioVec.iov_base = &dreg_state;
-    ioVec.iov_len = sizeof (dreg_state);
 
     if (hwbType == eDREGTypeWATCH)
     {
         hwbType = NT_ARM_HW_WATCH;
+        ioVec.iov_len = sizeof (dreg_state.dbg_info) + sizeof (dreg_state.pad)
+                + (sizeof (dreg_state.dbg_regs [0]) * m_max_hwp_supported);
 
         for (uint32_t i = 0; i < m_max_hwp_supported; i++)
         {
             dreg_state.dbg_regs[i].addr = m_hwp_regs[i].address;
             dreg_state.dbg_regs[i].ctrl = m_hwp_regs[i].control;
         }
     }
     else
     {
         hwbType = NT_ARM_HW_BREAK;
+        ioVec.iov_len = sizeof (dreg_state.dbg_info) + sizeof (dreg_state.pad)
+                + (sizeof (dreg_state.dbg_regs [0]) * m_max_hbp_supported);
 
         for (uint32_t i = 0; i < m_max_hbp_supported; i++)
         {
             dreg_state.dbg_regs[i].addr = m_hbr_regs[i].address;
             dreg_state.dbg_regs[i].ctrl = m_hbr_regs[i].control;
         }
     }