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Differential D122970

[LoongArch] Fix instruction definition
ClosedPublic

Authored by wangleiat on Apr 2 2022, 1:53 AM.

Details

Reviewers
SixWeining
Commits
rGcd85ea943157: [LoongArch] Fix instruction definition
Summary

This patch fixes issue with the LU32I_D instruction, which did not have
an input register operand.

Diff Detail

Event Timeline

wangleiat created this revision.Apr 2 2022, 1:53 AM
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wangleiat requested review of this revision.Apr 2 2022, 1:53 AM
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SixWeining accepted this revision.Apr 2 2022, 3:15 AM
This revision is now accepted and ready to land.Apr 2 2022, 3:15 AM
This revision was landed with ongoing or failed builds.Apr 2 2022, 3:16 AM
Closed by commit rGcd85ea943157: [LoongArch] Fix instruction definition (authored by wangleiat, committed by SixWeining). · Explain Why
This revision was automatically updated to reflect the committed changes.
SixWeining added a commit: rGcd85ea943157: [LoongArch] Fix instruction definition.
Harbormaster completed remote builds in B157579: Diff 419960.Apr 2 2022, 4:16 AM

Revision Contents

PathSize
llvm/
lib/
Target/
LoongArch/
6 lines
test/
CodeGen/
LoongArch/
2 lines

Diff 419962

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

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// Arithmetic Operation Instructions for 64-bits // Arithmetic Operation Instructions for 64-bits
def ADD_D : ALU_3R<0b00000000000100001, "add.d">; def ADD_D : ALU_3R<0b00000000000100001, "add.d">;
def SUB_D : ALU_3R<0b00000000000100011, "sub.d">; def SUB_D : ALU_3R<0b00000000000100011, "sub.d">;
def ADDI_D : ALU_2RI12<0b0000001011, "addi.d", simm12>; def ADDI_D : ALU_2RI12<0b0000001011, "addi.d", simm12>;
def ADDU16I_D : ALU_2RI16<0b000100, "addu16i.d", simm16>; def ADDU16I_D : ALU_2RI16<0b000100, "addu16i.d", simm16>;
def ALSL_WU : ALU_3RI2<0b000000000000011, "alsl.wu", uimm2_plus1>; def ALSL_WU : ALU_3RI2<0b000000000000011, "alsl.wu", uimm2_plus1>;
def ALSL_D : ALU_3RI2<0b000000000010110, "alsl.d", uimm2_plus1>; def ALSL_D : ALU_3RI2<0b000000000010110, "alsl.d", uimm2_plus1>;
def LU32I_D : ALU_1RI20<0b0001011, "lu32i.d", simm20>; let Constraints = "$rd = $dst" in {
def LU32I_D : Fmt1RI20<0b0001011, (outs GPR:$dst),
(ins GPR:$rd, simm20:$imm20),
"lu32i.d\t$rd, $imm20">;
}
def LU52I_D : ALU_2RI12<0b0000001100, "lu52i.d", simm12>; def LU52I_D : ALU_2RI12<0b0000001100, "lu52i.d", simm12>;
def PCADDU18I : ALU_1RI20<0b0001111, "pcaddu18i", simm20>; def PCADDU18I : ALU_1RI20<0b0001111, "pcaddu18i", simm20>;
def MUL_D : ALU_3R<0b00000000000111011, "mul.d">; def MUL_D : ALU_3R<0b00000000000111011, "mul.d">;
def MULH_D : ALU_3R<0b00000000000111100, "mulh.d">; def MULH_D : ALU_3R<0b00000000000111100, "mulh.d">;
def MULH_DU : ALU_3R<0b00000000000111101, "mulh.du">; def MULH_DU : ALU_3R<0b00000000000111101, "mulh.du">;
def MULW_D_W : ALU_3R<0b00000000000111110, "mulw.d.w">; def MULW_D_W : ALU_3R<0b00000000000111110, "mulw.d.w">;
def MULW_D_WU : ALU_3R<0b00000000000111111, "mulw.d.wu">; def MULW_D_WU : ALU_3R<0b00000000000111111, "mulw.d.wu">;
def DIV_D : ALU_3R<0b00000000001000100, "div.d">; def DIV_D : ALU_3R<0b00000000001000100, "div.d">;
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llvm/test/CodeGen/LoongArch/1ri.mir

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... ...
--- ---
# CHECK-LABEL: test_LU32I_D: # CHECK-LABEL: test_LU32I_D:
# CHECK-ENC: 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 # CHECK-ENC: 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0
# CHECK-ASM: lu32i.d $a0, 196 # CHECK-ASM: lu32i.d $a0, 196
name: test_LU32I_D name: test_LU32I_D
body: | body: |
bb.0: bb.0:
$r4 = LU32I_D 196 $r4 = LU32I_D $r4, 196
... ...
--- ---
# CHECK-LABEL: test_PCADDI: # CHECK-LABEL: test_PCADDI:
# CHECK-ENC: 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 1 0 0 1 0 0
# CHECK-ASM: pcaddi $a0, 187 # CHECK-ASM: pcaddi $a0, 187
name: test_PCADDI name: test_PCADDI
body: | body: |
bb.0: bb.0:
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