AMDGPU/SI: Fix some invaild assumptions when folding 64-bit immediates

[• tstellarAMD]

Summary

We were assuming tha if the use operand had a sub-register that
the immediate was 64-bits, but this was breaking the case of
folding a 64-bit immediate into another 64-bit instruction.

[arsenm]

Typo in commit message: tha

This needs a test

[• tstellarAMD]

In D12255#230544, @arsenm wrote:

Typo in commit message: tha

This needs a test

I don't think there is any way to hit this bug now, but it is uncovered by the REG_SEQUENCE folding patch and covered by existing tests.

[arsenm]

LGTM

lib/Target/AMDGPU/SIFoldOperands.cpp

if (FoldingImm) {
     unsigned UseReg = UseOp.getReg();
     const TargetRegisterClass *UseRC
       = TargetRegisterInfo::isVirtualRegister(UseReg) ?
       MRI.getRegClass(UseReg) :
       TRI.getPhysRegClass(UseReg);
 
     Imm = APInt(64, OpToFold.getImm());
 
+    const MCInstrDesc &FoldDesc = TII->get(OpToFold.getParent()->getOpcode());
+    const TargetRegisterClass *FoldRC =
+        TRI.getRegClass(FoldDesc.OpInfo[0].RegClass);
+
     // Split 64-bit constants into 32-bits for folding.
-    if (UseOp.getSubReg()) {
+    if (FoldRC->getSize() == 8 && UseOp.getSubReg()) {
       if (UseRC->getSize() != 8)
         return;
 
       if (UseOp.getSubReg() == AMDGPU::sub0) {
         Imm = Imm.getLoBits(32);
       } else {
         assert(UseOp.getSubReg() == AMDGPU::sub1);
         Imm = Imm.getHiBits(32);