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Differential D12151

Adding support for MMWORD type for MS inline asm
ClosedPublic

Authored by m_zuckerman on Aug 19 2015, 6:58 AM.

Details

Reviewers
rnk
mcrosier
Commits
rG9beca2e7e29e: [X86] Add support for mmword memory operand size for Intel-syntax x86 assembly
rL245835: [X86] Add support for mmword memory operand size for Intel-syntax x86 assembly
Summary

[X86] Add support for mmword memory operand size for Intel-syntax x86 assembly

Diff Detail

Repository
rL LLVM

Event Timeline

m_zuckerman updated this revision to Diff 32547.Aug 19 2015, 6:58 AM
m_zuckerman retitled this revision from to Adding support for MMWORD type for MS inline asm.
m_zuckerman updated this object.
m_zuckerman added reviewers: rnk, mcrosier.
mcrosier accepted this revision.Aug 19 2015, 8:09 AM
mcrosier edited edge metadata.

Please include a newline at the end of the test case. Otherwise, LGTM.

This revision is now accepted and ready to land.Aug 19 2015, 8:09 AM
Closed by commit rL245835: [X86] Add support for mmword memory operand size for Intel-syntax x86 assembly (authored by mzuckerm). · Explain WhyAug 24 2015, 3:27 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
X86/
AsmParser/
2 lines
test/
MC/
X86/
3 lines

Diff 32942

llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp

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/// getIntelMemOperandSize - Return intel memory operand size. /// getIntelMemOperandSize - Return intel memory operand size.
static unsigned getIntelMemOperandSize(StringRef OpStr) { static unsigned getIntelMemOperandSize(StringRef OpStr) {
unsigned Size = StringSwitch<unsigned>(OpStr) unsigned Size = StringSwitch<unsigned>(OpStr)
.Cases("BYTE", "byte", 8) .Cases("BYTE", "byte", 8)
.Cases("WORD", "word", 16) .Cases("WORD", "word", 16)
.Cases("DWORD", "dword", 32) .Cases("DWORD", "dword", 32)
.Cases("QWORD", "qword", 64) .Cases("QWORD", "qword", 64)
.Cases("MMWORD","mmword", 64)
.Cases("XWORD", "xword", 80) .Cases("XWORD", "xword", 80)
//
.Cases("TBYTE", "tbyte", 80) .Cases("TBYTE", "tbyte", 80)
.Cases("XMMWORD", "xmmword", 128) .Cases("XMMWORD", "xmmword", 128)
.Cases("YMMWORD", "ymmword", 256) .Cases("YMMWORD", "ymmword", 256)
.Cases("ZMMWORD", "zmmword", 512) .Cases("ZMMWORD", "zmmword", 512)
.Cases("OPAQUE", "opaque", -1U) // needs to be non-zero, but doesn't matter .Cases("OPAQUE", "opaque", -1U) // needs to be non-zero, but doesn't matter
.Default(0); .Default(0);
return Size; return Size;
} }
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llvm/trunk/test/MC/X86/intel-syntax.s

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// CHECK: repne // CHECK: repne
// CHECK: cmpsb %es:(%rdi), (%rsi) // CHECK: cmpsb %es:(%rdi), (%rsi)
// CHECK: repne // CHECK: repne
// CHECK: cmpsb %es:(%rdi), (%rsi) // CHECK: cmpsb %es:(%rdi), (%rsi)
sal eax, 123 sal eax, 123
// CHECK: shll $123, %eax // CHECK: shll $123, %eax
psignw mm0, MMWORD PTR t2
// CHECK: psignw t2, %mm0
comisd xmm0, QWORD PTR [eax] comisd xmm0, QWORD PTR [eax]
comiss xmm0, DWORD PTR [eax] comiss xmm0, DWORD PTR [eax]
vcomisd xmm0, QWORD PTR [eax] vcomisd xmm0, QWORD PTR [eax]
vcomiss xmm0, DWORD PTR [eax] vcomiss xmm0, DWORD PTR [eax]
// CHECK: comisd (%eax), %xmm0 // CHECK: comisd (%eax), %xmm0
// CHECK: comiss (%eax), %xmm0 // CHECK: comiss (%eax), %xmm0
// CHECK: vcomisd (%eax), %xmm0 // CHECK: vcomisd (%eax), %xmm0
// CHECK: vcomiss (%eax), %xmm0 // CHECK: vcomiss (%eax), %xmm0
fbld tbyte ptr [eax] fbld tbyte ptr [eax]
fbstp tbyte ptr [eax] fbstp tbyte ptr [eax]
// CHECK: fbld (%eax) // CHECK: fbld (%eax)
// CHECK: fbstp (%eax) // CHECK: fbstp (%eax)