WebAssembly: print immediates

[jfb]

Summary

For now output using C99's hexadecimal floating-point representation.

This patch also cleans up how machine operands are printed: instead of special-casing per type of machine instruction, the code now handles operands generically.

[sunfish]

lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp

122

It looks like APFloat's NaN printing doesn't include the significand (the "(n-char-sequence)"). I don't want to bikeshed on the format here, but we'll need to do *something* to preserve all the information in any case. Can you add asserts, or perhaps just highly-visible comments, indicating that we're missing functionality here?

[jfb]

• Canonicalize NaNs.

[jfb]

lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp

122

I changed it to canonicalize by default. The code looks a bit weird, so that all the bits are in place to do something else if we want to.

[sunfish]

llvm/trunk/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp

123 ↗

(On Diff #31739)

WebAssembly does have NaNs that have sign bits and payloads, so the comment here is incorrect.

Canonicalization here isn't useful since APFloat currently ignores NaN payloads. Could you change this canonicalization code to assert if a NaN is non-canonical? That won't happen in any code we write for a while, and when it does, the assert will fail and remind us that we need to fix this.

[jfb]

llvm/trunk/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp

123 ↗

(On Diff #31739)

Done in D11925.

lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp

assert(NumDefs <= 1 &&
          "Instructions with multiple result values not implemented");
 
   if (NumDefs != 0) {
     const MachineOperand &MO = MI->getOperand(0);
     unsigned Reg = MO.getReg();
     OS << "(setlocal @" << TargetRegisterInfo::virtReg2Index(Reg) << ' ';
   }
 
-  OS << '(';
-
-  bool PrintOperands = true;
-  switch (MI->getOpcode()) {
-  case WebAssembly::ARGUMENT_Int32:
-  case WebAssembly::ARGUMENT_Int64:
-  case WebAssembly::ARGUMENT_Float32:
-  case WebAssembly::ARGUMENT_Float64:
-    OS << Name(TII, MI) << ' ' << MI->getOperand(1).getImm();
-    PrintOperands = false;
-    break;
+  OS << '(' << Name(TII, MI);
+  for (const MachineOperand &MO : MI->uses())
+    switch (MO.getType()) {
     default:
-    OS << Name(TII, MI);
-    break;
-  }
-
-  if (PrintOperands)
-    for (const MachineOperand &MO : MI->uses()) {
-      if (MO.isReg() && MO.isImplicit())
+      llvm_unreachable("unexpected machine operand type");
+    case MachineOperand::MO_Register: {
+      if (MO.isImplicit())
         continue;
       unsigned Reg = MO.getReg();
       OS << " @" << TargetRegisterInfo::virtReg2Index(Reg);
+    } break;
+    case MachineOperand::MO_Immediate: {
+      OS << ' ' << MO.getImm();
+    } break;
+    case MachineOperand::MO_FPImmediate: {
+      static const size_t BufBytes = 128;
+      char buf[BufBytes];
+      // Use C99's hexadecimal floating-point representation.
+      auto Written = MO.getFPImm()->getValueAPF().convertToHexString(
+          buf, /*hexDigits=*/0, /*upperCase=*/false,
+          APFloat::rmNearestTiesToEven);
+      assert(Written != 0);
+      assert(Written < BufBytes);
+      OS << ' ' << buf;
+    } break;
     }
   OS << ')';
 
   if (NumDefs != 0)
     OS << ')';
 
   OS << '\n';
 
   OutStreamer->EmitRawText(OS.str());
 }
 
 // Force static initialization.
 extern "C" void LLVMInitializeWebAssemblyAsmPrinter() {
   RegisterAsmPrinter<WebAssemblyAsmPrinter> X(TheWebAssemblyTarget32);
   RegisterAsmPrinter<WebAssemblyAsmPrinter> Y(TheWebAssemblyTarget64);
 }

lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

WebAssemblyTargetLowering::WebAssemblyTargetLowering(
   // Set up the register classes.
   addRegisterClass(MVT::i32, &WebAssembly::Int32RegClass);
   addRegisterClass(MVT::i64, &WebAssembly::Int64RegClass);
   addRegisterClass(MVT::f32, &WebAssembly::Float32RegClass);
   addRegisterClass(MVT::f64, &WebAssembly::Float64RegClass);
   // Compute derived properties from the register classes.
   computeRegisterProperties(Subtarget->getRegisterInfo());
 
-  // FIXME: setOperationAction...
+  // FIXME: many setOperationAction are missing...
+
+  // Don't expand the following types to constant pools.
+  setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
+  setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
 }
 
 MVT WebAssemblyTargetLowering::getScalarShiftAmountTy(const DataLayout &DL,
                                                       EVT VT) const {
   return VT.getSimpleVT();
 }
 
 //===----------------------------------------------------------------------===//

lib/Target/WebAssembly/WebAssemblyInstrInfo.td

multiclass ARGUMENT<WebAssemblyRegClass vt> {
   def ARGUMENT_#vt : I<(outs vt:$res), (ins i32imm:$argno),
                        [(set vt:$res, (WebAssemblyargument timm:$argno))]>;
 }
 defm : ARGUMENT<Int32>;
 defm : ARGUMENT<Int64>;
 defm : ARGUMENT<Float32>;
 defm : ARGUMENT<Float64>;
 
+
+def Immediate_I32 : I<(outs Int32:$res), (ins i32imm:$imm),
+                      [(set Int32:$res, imm:$imm)]>;
+def Immediate_I64 : I<(outs Int64:$res), (ins i64imm:$imm),
+                      [(set Int64:$res, imm:$imm)]>;
+def Immediate_F32 : I<(outs Float32:$res), (ins f32imm:$imm),
+                      [(set Float32:$res, fpimm:$imm)]>;
+def Immediate_F64 : I<(outs Float64:$res), (ins f64imm:$imm),
+                      [(set Float64:$res, fpimm:$imm)]>;
+
 //===----------------------------------------------------------------------===//
 // Additional sets of instructions.
 //===----------------------------------------------------------------------===//
 
 include "WebAssemblyInstrMemory.td"
 include "WebAssemblyInstrCall.td"
 include "WebAssemblyInstrControl.td"
 include "WebAssemblyInstrInteger.td"
 include "WebAssemblyInstrFloat.td"
 include "WebAssemblyInstrConv.td"
 include "WebAssemblyInstrAtomics.td"
 include "WebAssemblyInstrSIMD.td"

test/CodeGen/WebAssembly/immediates.ll

+; RUN: llc < %s -asm-verbose=false | FileCheck %s
+
+; Test that basic immediates assemble as expected.
+
+target datalayout = "e-p:32:32-i64:64-v128:8:128-n32:64-S128"
+target triple = "wasm32-unknown-unknown"
+
+; CHECK-LABEL: zero_i32:
+; CHECK-NEXT: (setlocal @0 (immediate 0))
+; CHECK-NEXT: (return @0)
+define i32 @zero_i32() {
+  ret i32 0
+}
+
+; CHECK-LABEL: one_i32:
+; CHECK-NEXT: (setlocal @0 (immediate 1))
+; CHECK-NEXT: (return @0)
+define i32 @one_i32() {
+  ret i32 1
+}
+
+; CHECK-LABEL: max_i32:
+; CHECK-NEXT: (setlocal @0 (immediate 2147483647))
+; CHECK-NEXT: (return @0)
+define i32 @max_i32() {
+  ret i32 2147483647
+}
+
+; CHECK-LABEL: min_i32:
+; CHECK-NEXT: (setlocal @0 (immediate -2147483648))
+; CHECK-NEXT: (return @0)
+define i32 @min_i32() {
+  ret i32 -2147483648
+}
+
+; CHECK-LABEL: zero_i64:
+; CHECK-NEXT: (setlocal @0 (immediate 0))
+; CHECK-NEXT: (return @0)
+define i64 @zero_i64() {
+  ret i64 0
+}
+
+; CHECK-LABEL: one_i64:
+; CHECK-NEXT: (setlocal @0 (immediate 1))
+; CHECK-NEXT: (return @0)
+define i64 @one_i64() {
+  ret i64 1
+}
+
+; CHECK-LABEL: max_i64:
+; CHECK-NEXT: (setlocal @0 (immediate 9223372036854775807))
+; CHECK-NEXT: (return @0)
+define i64 @max_i64() {
+  ret i64 9223372036854775807
+}
+
+; CHECK-LABEL: min_i64:
+; CHECK-NEXT: (setlocal @0 (immediate -9223372036854775808))
+; CHECK-NEXT: (return @0)
+define i64 @min_i64() {
+  ret i64 -9223372036854775808
+}
+
+; CHECK-LABEL: negzero_f32:
+; CHECK-NEXT: (setlocal @0 (immediate -0x0p0))
+; CHECK-NEXT: (return @0)
+define float @negzero_f32() {
+  ret float -0.0
+}
+
+; CHECK-LABEL: zero_f32:
+; CHECK-NEXT: (setlocal @0 (immediate 0x0p0))
+; CHECK-NEXT: (return @0)
+define float @zero_f32() {
+  ret float 0.0
+}
+
+; CHECK-LABEL: one_f32:
+; CHECK-NEXT: (setlocal @0 (immediate 0x1p0))
+; CHECK-NEXT: (return @0)
+define float @one_f32() {
+  ret float 1.0
+}
+
+; CHECK-LABEL: two_f32:
+; CHECK-NEXT: (setlocal @0 (immediate 0x1p1))
+; CHECK-NEXT: (return @0)
+define float @two_f32() {
+  ret float 2.0
+}
+
+; CHECK-LABEL: nan_f32:
+; CHECK-NEXT: (setlocal @0 (immediate nan))
+; CHECK-NEXT: (return @0)
+define float @nan_f32() {
+  ret float 0x7FF8000000000000
+}
+
+; CHECK-LABEL: negnan_f32:
+; CHECK-NEXT: (setlocal @0 (immediate -nan))
+; CHECK-NEXT: (return @0)
+define float @negnan_f32() {
+  ret float 0xFFF8000000000000
+}
+
+; CHECK-LABEL: inf_f32:
+; CHECK-NEXT: (setlocal @0 (immediate infinity))
+; CHECK-NEXT: (return @0)
+define float @inf_f32() {
+  ret float 0x7FF0000000000000
+}
+
+; CHECK-LABEL: neginf_f32:
+; CHECK-NEXT: (setlocal @0 (immediate -infinity))
+; CHECK-NEXT: (return @0)
+define float @neginf_f32() {
+  ret float 0xFFF0000000000000
+}
+
+; CHECK-LABEL: negzero_f64:
+; CHECK-NEXT: (setlocal @0 (immediate -0x0p0))
+; CHECK-NEXT: (return @0)
+define double @negzero_f64() {
+  ret double -0.0
+}
+
+; CHECK-LABEL: zero_f64:
+; CHECK-NEXT: (setlocal @0 (immediate 0x0p0))
+; CHECK-NEXT: (return @0)
+define double @zero_f64() {
+  ret double 0.0
+}
+
+; CHECK-LABEL: one_f64:
+; CHECK-NEXT: (setlocal @0 (immediate 0x1p0))
+; CHECK-NEXT: (return @0)
+define double @one_f64() {
+  ret double 1.0
+}
+
+; CHECK-LABEL: two_f64:
+; CHECK-NEXT: (setlocal @0 (immediate 0x1p1))
+; CHECK-NEXT: (return @0)
+define double @two_f64() {
+  ret double 2.0
+}
+
+; CHECK-LABEL: nan_f64:
+; CHECK-NEXT: (setlocal @0 (immediate nan))
+; CHECK-NEXT: (return @0)
+define double @nan_f64() {
+  ret double 0x7FF8000000000000
+}
+
+; CHECK-LABEL: negnan_f64:
+; CHECK-NEXT: (setlocal @0 (immediate -nan))
+; CHECK-NEXT: (return @0)
+define double @negnan_f64() {
+  ret double 0xFFF8000000000000
+}
+
+; CHECK-LABEL: inf_f64:
+; CHECK-NEXT: (setlocal @0 (immediate infinity))
+; CHECK-NEXT: (return @0)
+define double @inf_f64() {
+  ret double 0x7FF0000000000000
+}
+
+; CHECK-LABEL: neginf_f64:
+; CHECK-NEXT: (setlocal @0 (immediate -infinity))
+; CHECK-NEXT: (return @0)
+define double @neginf_f64() {
+  ret double 0xFFF0000000000000
+}