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Differential D11812

AMDGPU/SI: Use correct encoding of vopc for VI in the assembler
ClosedPublic

Authored by • tstellarAMD on Aug 6 2015, 11:30 AM.

Details

Reviewers
arsenm
Commits
rG9d67d223ffc4: Merging r244332: --------------------------------------------------------------…
rGc8733e805e2f: AMDGPU/SI: Use correct encoding of vopc for VI in the assembler
rL244332: AMDGPU/SI: Use correct encoding of vopc for VI in the assembler
Summary

We were using the SI encoding for VI.

Diff Detail

Event Timeline

• tstellarAMD updated this revision to Diff 31462.Aug 6 2015, 11:30 AM
• tstellarAMD retitled this revision from to AMDGPU/SI: Use correct encoding of vopc for VI in the assembler.
• tstellarAMD updated this object.
• tstellarAMD added a reviewer: arsenm.
• tstellarAMD added a subscriber: llvm-commits.
arsenm accepted this revision.Aug 6 2015, 11:55 AM
arsenm edited edge metadata.

LGTM

This revision is now accepted and ready to land.Aug 6 2015, 11:55 AM
Closed by commit rL244332: AMDGPU/SI: Use correct encoding of vopc for VI in the assembler (authored by tstellar). · Explain WhyAug 7 2015, 9:46 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
AMDGPU/
2 lines
test/
MC/
AMDGPU/
26 lines

Diff 31462

lib/Target/AMDGPU/SIInstrInfo.td

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multiclass VOPC_m <vopc op, dag ins, string asm, list<dag> pattern, multiclass VOPC_m <vopc op, dag ins, string asm, list<dag> pattern,
string opName, bit DefExec, string revOpName = ""> { string opName, bit DefExec, string revOpName = ""> {
def "" : VOPC_Pseudo <ins, pattern, opName>; def "" : VOPC_Pseudo <ins, pattern, opName>;
def _si : VOPC<op.SI, ins, asm, []>, def _si : VOPC<op.SI, ins, asm, []>,
SIMCInstr <opName#"_e32", SISubtarget.SI> { SIMCInstr <opName#"_e32", SISubtarget.SI> {
let Defs = !if(DefExec, [EXEC], []); let Defs = !if(DefExec, [EXEC], []);
let hasSideEffects = DefExec; let hasSideEffects = DefExec;
let AssemblerPredicates = [isSICI];
} }
def _vi : VOPC<op.VI, ins, asm, []>, def _vi : VOPC<op.VI, ins, asm, []>,
SIMCInstr <opName#"_e32", SISubtarget.VI> { SIMCInstr <opName#"_e32", SISubtarget.VI> {
let Defs = !if(DefExec, [EXEC], []); let Defs = !if(DefExec, [EXEC], []);
let hasSideEffects = DefExec; let hasSideEffects = DefExec;
let AssemblerPredicates = [isVI];
} }
} }
multiclass VOPC_Helper <vopc op, string opName, multiclass VOPC_Helper <vopc op, string opName,
dag ins32, string asm32, list<dag> pat32, dag ins32, string asm32, list<dag> pat32,
dag out64, dag ins64, string asm64, list<dag> pat64, dag out64, dag ins64, string asm64, list<dag> pat64,
bit HasMods, bit DefExec, string revOp> { bit HasMods, bit DefExec, string revOp> {
defm _e32 : VOPC_m <op, ins32, opName#asm32, pat32, opName, DefExec>; defm _e32 : VOPC_m <op, ins32, opName#asm32, pat32, opName, DefExec>;
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test/MC/AMDGPU/vopc.s

// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s // RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=SICI
// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s // RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s --check-prefix=SICI
// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=VI
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Generic Checks // Generic Checks
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// src0 sgpr // src0 sgpr
v_cmp_lt_f32 vcc, s2, v4 v_cmp_lt_f32 vcc, s2, v4
// CHECK: v_cmp_lt_f32_e32 vcc, s2, v4 ; encoding: [0x02,0x08,0x02,0x7c] // SICI: v_cmp_lt_f32_e32 vcc, s2, v4 ; encoding: [0x02,0x08,0x02,0x7c]
// VI: v_cmp_lt_f32_e32 vcc, s2, v4 ; encoding: [0x02,0x08,0x82,0x7c]
// src0 inline immediate // src0 inline immediate
v_cmp_lt_f32 vcc, 0, v4 v_cmp_lt_f32 vcc, 0, v4
// CHECK: v_cmp_lt_f32_e32 vcc, 0, v4 ; encoding: [0x80,0x08,0x02,0x7c] // SICI: v_cmp_lt_f32_e32 vcc, 0, v4 ; encoding: [0x80,0x08,0x02,0x7c]
// VI: v_cmp_lt_f32_e32 vcc, 0, v4 ; encoding: [0x80,0x08,0x82,0x7c]
// src0 literal // src0 literal
v_cmp_lt_f32 vcc, 10.0, v4 v_cmp_lt_f32 vcc, 10.0, v4
// CHECK: v_cmp_lt_f32_e32 vcc, 0x41200000, v4 ; encoding: [0xff,0x08,0x02,0x7c,0x00,0x00,0x20,0x41] // SICI: v_cmp_lt_f32_e32 vcc, 0x41200000, v4 ; encoding: [0xff,0x08,0x02,0x7c,0x00,0x00,0x20,0x41]
// VI: v_cmp_lt_f32_e32 vcc, 0x41200000, v4 ; encoding: [0xff,0x08,0x82,0x7c,0x00,0x00,0x20,0x41]
// src0, src1 max vgpr // src0, src1 max vgpr
v_cmp_lt_f32 vcc, v255, v255 v_cmp_lt_f32 vcc, v255, v255
// CHECK: v_cmp_lt_f32_e32 vcc, v255, v255 ; encoding: [0xff,0xff,0x03,0x7c] // SICI: v_cmp_lt_f32_e32 vcc, v255, v255 ; encoding: [0xff,0xff,0x03,0x7c]
// VI: v_cmp_lt_f32_e32 vcc, v255, v255 ; encoding: [0xff,0xff,0x83,0x7c]
// force 32-bit encoding // force 32-bit encoding
v_cmp_lt_f32_e32 vcc, v2, v4 v_cmp_lt_f32_e32 vcc, v2, v4
// CHECK: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x02,0x7c] // SICI: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x02,0x7c]
// VI: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x82,0x7c]
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Instructions // Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
v_cmp_f_f32 vcc, v2, v4 v_cmp_f_f32 vcc, v2, v4
// CHECK: v_cmp_f_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x00,0x7c] // SICI: v_cmp_f_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x00,0x7c]
// VI: v_cmp_f_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x80,0x7c]
v_cmp_lt_f32 vcc, v2, v4 v_cmp_lt_f32 vcc, v2, v4
// CHECK: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x02,0x7c] // SICI: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x02,0x7c]
// VI: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x82,0x7c]
// TODO: Add tests for the rest of the instructions. // TODO: Add tests for the rest of the instructions.