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Differential D11796

[PATCH, Mips] Remap move as or.
ClosedPublic

Authored by sdardis on Aug 6 2015, 2:46 AM.

Details

Reviewers
vkalintiris
Commits
rG1c78ca6a09ce: [mips] Remap move as or.
rL244579: [mips] Remap move as or.
Summary

This patch remaps the assembly idiom 'move' to 'or' instead of 'daddu' or
'addu'. The use of addu/daddu instead of or as move was highlighted as a
performance issue during the analysis of a recent 64bit design. Originally
move was encoded as 'or' by binutils but was changed for the r10k cpu family
due to their pipeline which had 2 arithmetic units and a single logical unit,
and so could issue multiple (d)addu based moves at the same time but only 1
logical move.




This patch preserves the disassembly behaviour so that disassembling a old style

(d)addu move still appears as move, but assembling move always gives an or
Diff Detail
Event Timeline
sdardis updated this revision to Diff 31434.Aug 6 2015, 2:46 AM
sdardis retitled this revision from  to [PATCH, Mips] Remap move as or..
sdardis updated this object.
sdardis added a reviewer: vkalintiris.
sdardis added a subscriber: llvm-commits.
vkalintiris accepted this revision.Aug 7 2015, 1:47 AM
vkalintiris edited edge metadata.
LGTM.
This revision is now accepted and ready to land.Aug 7 2015, 1:47 AM
vkalintiris added a comment.Aug 7 2015, 1:52 AM
I'm sorry, I hit the submit button accidentally.



You mention in your commit message the following:



This patch preserves the disassembly behaviour so that disassembling a old style

(d)addu move still appears as move, but assembling move always gives an or



Could you confirm that this is the behaviour that binutils project follows (or will follow) too?
sdardis added a comment.Aug 10 2015, 3:36 AM
Yes, this is same behaviour as binutils will do.
Closed by commit rL244579: [mips] Remap move as or. (authored by vkalintiris).  ·  Explain WhyAug 11 2015, 1:57 AM
This revision was automatically updated to reflect the committed changes.
Revision Contents
PathSize
lib/
Target/
Mips/
MCTargetDesc/
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test/
MC/
Disassembler/
Mips/
mips1/
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mips2/
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mips3/
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mips32/
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mips32r2/
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mips4/
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mips64/
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mips64r2/
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mips64r3/
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mips64r5/
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mips64r6/
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Mips/
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mips1/
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mips2/
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mips3/
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mips32/
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mips32r2/
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mips32r3/
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mips32r5/
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mips32r6/
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mips4/
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mips5/
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mips64/
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mips64r2/
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mips64r3/
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mips64r5/
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mips64r6/
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Diff 31434
lib/Target/Mips/MCTargetDesc/MipsABIInfo.h
Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Linespublic:

  }
  }




  unsigned GetStackPtr() const;
  unsigned GetStackPtr() const;

  unsigned GetFramePtr() const;
  unsigned GetFramePtr() const;

  unsigned GetBasePtr() const;
  unsigned GetBasePtr() const;

  unsigned GetNullPtr() const;
  unsigned GetNullPtr() const;

  unsigned GetPtrAdduOp() const;
  unsigned GetPtrAdduOp() const;

  unsigned GetPtrAddiuOp() const;
  unsigned GetPtrAddiuOp() const;

  unsigned GetGPRMoveOp() const;

  inline bool ArePtrs64bit() const { return IsN64(); }
  inline bool ArePtrs64bit() const { return IsN64(); }




  unsigned GetEhDataReg(unsigned I) const;
  unsigned GetEhDataReg(unsigned I) const;

};
};

}
}




#endif
#endif

lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
Show First 20 Lines • Show All 109 Lines • ▼ Show 20 Lines
unsigned MipsABIInfo::GetPtrAdduOp() const {
unsigned MipsABIInfo::GetPtrAdduOp() const {

  return ArePtrs64bit() ? Mips::DADDu : Mips::ADDu;
  return ArePtrs64bit() ? Mips::DADDu : Mips::ADDu;

}
}




unsigned MipsABIInfo::GetPtrAddiuOp() const {
unsigned MipsABIInfo::GetPtrAddiuOp() const {

  return ArePtrs64bit() ? Mips::DADDiu : Mips::ADDiu;
  return ArePtrs64bit() ? Mips::DADDiu : Mips::ADDiu;

}
}




unsigned MipsABIInfo::GetGPRMoveOp() const {

  return ArePtrs64bit() ? Mips::OR64 : Mips::OR;

}



unsigned MipsABIInfo::GetEhDataReg(unsigned I) const {
unsigned MipsABIInfo::GetEhDataReg(unsigned I) const {

  static const unsigned EhDataReg[] = {
  static const unsigned EhDataReg[] = {

    Mips::A0, Mips::A1, Mips::A2, Mips::A3
    Mips::A0, Mips::A1, Mips::A2, Mips::A3

  };
  };

  static const unsigned EhDataReg64[] = {
  static const unsigned EhDataReg64[] = {

    Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64
    Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64

  };
  };




  return IsN64() ? EhDataReg64[I] : EhDataReg[I];
  return IsN64() ? EhDataReg64[I] : EhDataReg[I];

}
}




lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
Show First 20 Lines • Show All 760 Lines • ▼ Show 20 Lines  if (!Pic || !(getABI().IsN32() || getABI().IsN64()))

    return;
    return;




  MCAssembler &MCA = getStreamer().getAssembler();
  MCAssembler &MCA = getStreamer().getAssembler();

  MCInst Inst;
  MCInst Inst;




  // Either store the old $gp in a register or on the stack
  // Either store the old $gp in a register or on the stack

  if (IsReg) {
  if (IsReg) {

    // move $save, $gpreg
    // move $save, $gpreg

    Inst.setOpcode(Mips::DADDu);
    Inst.setOpcode(Mips::OR64);

    Inst.addOperand(MCOperand::createReg(RegOrOffset));
    Inst.addOperand(MCOperand::createReg(RegOrOffset));

    Inst.addOperand(MCOperand::createReg(Mips::GP));
    Inst.addOperand(MCOperand::createReg(Mips::GP));

    Inst.addOperand(MCOperand::createReg(Mips::ZERO));
    Inst.addOperand(MCOperand::createReg(Mips::ZERO));

  } else {
  } else {

    // sd $gpreg, offset($sp)
    // sd $gpreg, offset($sp)

    Inst.setOpcode(Mips::SD);
    Inst.setOpcode(Mips::SD);

    Inst.addOperand(MCOperand::createReg(Mips::GP));
    Inst.addOperand(MCOperand::createReg(Mips::GP));

    Inst.addOperand(MCOperand::createReg(Mips::SP));
    Inst.addOperand(MCOperand::createReg(Mips::SP));

▲ Show 20 Lines • Show All 47 Lines • Show Last 20 Lines
lib/Target/Mips/Mips64InstrInfo.td
Show First 20 Lines • Show All 542 Lines • ▼ Show 20 Lines
def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst),
def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst),

              (BBIT132 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>;
              (BBIT132 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>;

}
}




//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//

// Instruction aliases
// Instruction aliases

//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//

def : MipsInstAlias<"move $dst, $src",
def : MipsInstAlias<"move $dst, $src",

                    (OR64 GPR64Opnd:$dst,  GPR64Opnd:$src, ZERO_64), 1>,

      GPR_64;

def : MipsInstAlias<"move $dst, $src",

                    (DADDu GPR64Opnd:$dst,  GPR64Opnd:$src, ZERO_64), 1>,
                    (DADDu GPR64Opnd:$dst,  GPR64Opnd:$src, ZERO_64), 1>,

      GPR_64;
      GPR_64;

def : MipsInstAlias<"daddu $rs, $rt, $imm",
def : MipsInstAlias<"daddu $rs, $rt, $imm",

                    (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
                    (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),

                    0>, ISA_MIPS3;
                    0>, ISA_MIPS3;

def : MipsInstAlias<"dadd $rs, $rt, $imm",
def : MipsInstAlias<"dadd $rs, $rt, $imm",

                    (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
                    (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),

                    0>, ISA_MIPS3_NOT_32R6_64R6;
                    0>, ISA_MIPS3_NOT_32R6_64R6;

▲ Show 20 Lines • Show All 69 Lines • Show Last 20 Lines
lib/Target/Mips/MipsAsmPrinter.cpp
Show First 20 Lines • Show All 1,002 Lines • ▼ Show 20 Linesvoid MipsAsmPrinter::EmitFPCallStub(

  //
  //

  // mov the return address to S2.
  // mov the return address to S2.

  // we have no stack space to store it and we are about to make another call.
  // we have no stack space to store it and we are about to make another call.

  // We need to make sure that the enclosing function knows to save S2
  // We need to make sure that the enclosing function knows to save S2

  // This should have already been handled.
  // This should have already been handled.

  //
  //

  // Mov $18, $31
  // Mov $18, $31




  EmitInstrRegRegReg(*STI, Mips::ADDu, Mips::S2, Mips::RA, Mips::ZERO);
  EmitInstrRegRegReg(*STI, Mips::OR, Mips::S2, Mips::RA, Mips::ZERO);




  EmitSwapFPIntParams(*STI, Signature->ParamSig, LE, true);
  EmitSwapFPIntParams(*STI, Signature->ParamSig, LE, true);




  // Jal xxxx
  // Jal xxxx

  //
  //

  EmitJal(*STI, MSymbol);
  EmitJal(*STI, MSymbol);




  // fix return values
  // fix return values

▲ Show 20 Lines • Show All 74 Lines • Show Last 20 Lines
lib/Target/Mips/MipsInstrInfo.td
Show First 20 Lines • Show All 1,564 Lines • ▼ Show 20 Linesdef CACHE : MMRel, CacheOp<"cache", mem>, CACHEOP_FM<0b101111>,

            INSN_MIPS3_32_NOT_32R6_64R6;
            INSN_MIPS3_32_NOT_32R6_64R6;

def PREF :  MMRel, CacheOp<"pref", mem>, CACHEOP_FM<0b110011>,
def PREF :  MMRel, CacheOp<"pref", mem>, CACHEOP_FM<0b110011>,

            INSN_MIPS3_32_NOT_32R6_64R6;
            INSN_MIPS3_32_NOT_32R6_64R6;




//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//

// Instruction aliases
// Instruction aliases

//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//

def : MipsInstAlias<"move $dst, $src",
def : MipsInstAlias<"move $dst, $src",

                    (OR GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>,

      GPR_32 {

  let AdditionalPredicates = [NotInMicroMips];

}

def : MipsInstAlias<"move $dst, $src",

                    (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
                    (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>,

      GPR_32 {
      GPR_32 {

  let AdditionalPredicates = [NotInMicroMips];
  let AdditionalPredicates = [NotInMicroMips];

}
}

def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>,
def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>,

      ISA_MIPS1_NOT_32R6_64R6;
      ISA_MIPS1_NOT_32R6_64R6;

def : MipsInstAlias<"addu $rs, $rt, $imm",
def : MipsInstAlias<"addu $rs, $rt, $imm",

                    (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
                    (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;

def : MipsInstAlias<"addu $rs, $imm",
def : MipsInstAlias<"addu $rs, $imm",

▲ Show 20 Lines • Show All 397 Lines • Show Last 20 Lines
lib/Target/Mips/MipsSEFrameLowering.cpp
Show First 20 Lines • Show All 375 Lines • ▼ Show 20 Lines  const MipsRegisterInfo &RegInfo =

      *static_cast<const MipsRegisterInfo *>(STI.getRegisterInfo());
      *static_cast<const MipsRegisterInfo *>(STI.getRegisterInfo());




  MachineBasicBlock::iterator MBBI = MBB.begin();
  MachineBasicBlock::iterator MBBI = MBB.begin();

  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();

  MipsABIInfo ABI = STI.getABI();
  MipsABIInfo ABI = STI.getABI();

  unsigned SP = ABI.GetStackPtr();
  unsigned SP = ABI.GetStackPtr();

  unsigned FP = ABI.GetFramePtr();
  unsigned FP = ABI.GetFramePtr();

  unsigned ZERO = ABI.GetNullPtr();
  unsigned ZERO = ABI.GetNullPtr();

  unsigned ADDu = ABI.GetPtrAdduOp();
  unsigned MOVE = ABI.GetGPRMoveOp();

  unsigned ADDiu = ABI.GetPtrAddiuOp();
  unsigned ADDiu = ABI.GetPtrAddiuOp();

  unsigned AND = ABI.IsN64() ? Mips::AND64 : Mips::AND;
  unsigned AND = ABI.IsN64() ? Mips::AND64 : Mips::AND;




  const TargetRegisterClass *RC = ABI.ArePtrs64bit() ?
  const TargetRegisterClass *RC = ABI.ArePtrs64bit() ?

        &Mips::GPR64RegClass : &Mips::GPR32RegClass;
        &Mips::GPR64RegClass : &Mips::GPR32RegClass;




  // First, compute final stack size.
  // First, compute final stack size.

  uint64_t StackSize = MFI->getStackSize();
  uint64_t StackSize = MFI->getStackSize();

▲ Show 20 Lines • Show All 93 Lines • ▼ Show 20 Lines    for (int I = 0; I < 4; ++I) {

      BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
      BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))

          .addCFIIndex(CFIIndex);
          .addCFIIndex(CFIIndex);

    }
    }

  }
  }




  // if framepointer enabled, set it to point to the stack pointer.
  // if framepointer enabled, set it to point to the stack pointer.

  if (hasFP(MF)) {
  if (hasFP(MF)) {

    // Insert instruction "move $fp, $sp" at this location.
    // Insert instruction "move $fp, $sp" at this location.

    BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO)
    BuildMI(MBB, MBBI, dl, TII.get(MOVE), FP).addReg(SP).addReg(ZERO)

      .setMIFlag(MachineInstr::FrameSetup);
      .setMIFlag(MachineInstr::FrameSetup);




    // emit ".cfi_def_cfa_register $fp"
    // emit ".cfi_def_cfa_register $fp"

    unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(
    unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(

        nullptr, MRI->getDwarfRegNum(FP, true)));
        nullptr, MRI->getDwarfRegNum(FP, true)));

    BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
    BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))

        .addCFIIndex(CFIIndex);
        .addCFIIndex(CFIIndex);




    if (RegInfo.needsStackRealignment(MF)) {
    if (RegInfo.needsStackRealignment(MF)) {

      // addiu $Reg, $zero, -MaxAlignment
      // addiu $Reg, $zero, -MaxAlignment

      // andi $sp, $sp, $Reg
      // andi $sp, $sp, $Reg

      unsigned VR = MF.getRegInfo().createVirtualRegister(RC);
      unsigned VR = MF.getRegInfo().createVirtualRegister(RC);

      assert(isInt<16>(MFI->getMaxAlignment()) &&
      assert(isInt<16>(MFI->getMaxAlignment()) &&

             "Function's alignment size requirement is not supported.");
             "Function's alignment size requirement is not supported.");

      int MaxAlign = - (signed) MFI->getMaxAlignment();
      int MaxAlign = - (signed) MFI->getMaxAlignment();




      BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO) .addImm(MaxAlign);
      BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO) .addImm(MaxAlign);

      BuildMI(MBB, MBBI, dl, TII.get(AND), SP).addReg(SP).addReg(VR);
      BuildMI(MBB, MBBI, dl, TII.get(AND), SP).addReg(SP).addReg(VR);




      if (hasBP(MF)) {
      if (hasBP(MF)) {

        // move $s7, $sp
        // move $s7, $sp

        unsigned BP = STI.isABI_N64() ? Mips::S7_64 : Mips::S7;
        unsigned BP = STI.isABI_N64() ? Mips::S7_64 : Mips::S7;

        BuildMI(MBB, MBBI, dl, TII.get(ADDu), BP)
        BuildMI(MBB, MBBI, dl, TII.get(MOVE), BP)

          .addReg(SP)
          .addReg(SP)

          .addReg(ZERO);
          .addReg(ZERO);

      }
      }

    }
    }

  }
  }

}
}




void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF,
void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF,

                                       MachineBasicBlock &MBB) const {
                                       MachineBasicBlock &MBB) const {

  MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
  MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();

  MachineFrameInfo *MFI            = MF.getFrameInfo();
  MachineFrameInfo *MFI            = MF.getFrameInfo();

  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();




  const MipsSEInstrInfo &TII =
  const MipsSEInstrInfo &TII =

      *static_cast<const MipsSEInstrInfo *>(STI.getInstrInfo());
      *static_cast<const MipsSEInstrInfo *>(STI.getInstrInfo());

  const MipsRegisterInfo &RegInfo =
  const MipsRegisterInfo &RegInfo =

      *static_cast<const MipsRegisterInfo *>(STI.getRegisterInfo());
      *static_cast<const MipsRegisterInfo *>(STI.getRegisterInfo());




  DebugLoc dl = MBBI->getDebugLoc();
  DebugLoc dl = MBBI->getDebugLoc();

  MipsABIInfo ABI = STI.getABI();
  MipsABIInfo ABI = STI.getABI();

  unsigned SP = ABI.GetStackPtr();
  unsigned SP = ABI.GetStackPtr();

  unsigned FP = ABI.GetFramePtr();
  unsigned FP = ABI.GetFramePtr();

  unsigned ZERO = ABI.GetNullPtr();
  unsigned ZERO = ABI.GetNullPtr();

  unsigned ADDu = ABI.GetPtrAdduOp();
  unsigned MOVE = ABI.GetGPRMoveOp();




  // if framepointer enabled, restore the stack pointer.
  // if framepointer enabled, restore the stack pointer.

  if (hasFP(MF)) {
  if (hasFP(MF)) {

    // Find the first instruction that restores a callee-saved register.
    // Find the first instruction that restores a callee-saved register.

    MachineBasicBlock::iterator I = MBBI;
    MachineBasicBlock::iterator I = MBBI;




    for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i)
    for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i)

      --I;
      --I;




    // Insert instruction "move $sp, $fp" at this location.
    // Insert instruction "move $sp, $fp" at this location.

    BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO);
    BuildMI(MBB, I, dl, TII.get(MOVE), SP).addReg(FP).addReg(ZERO);

  }
  }




  if (MipsFI->callsEhReturn()) {
  if (MipsFI->callsEhReturn()) {

    const TargetRegisterClass *RC =
    const TargetRegisterClass *RC =

        ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
        ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;




    // Find first instruction that restores a callee-saved register.
    // Find first instruction that restores a callee-saved register.

    MachineBasicBlock::iterator I = MBBI;
    MachineBasicBlock::iterator I = MBBI;

▲ Show 20 Lines • Show All 121 Lines • Show Last 20 Lines
lib/Target/Mips/MipsSEInstrInfo.cpp
Show First 20 Lines • Show All 82 Lines • ▼ Show 20 Linesvoid MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,

  unsigned Opc = 0, ZeroReg = 0;
  unsigned Opc = 0, ZeroReg = 0;

  bool isMicroMips = Subtarget.inMicroMipsMode();
  bool isMicroMips = Subtarget.inMicroMipsMode();




  if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
  if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.

    if (Mips::GPR32RegClass.contains(SrcReg)) {
    if (Mips::GPR32RegClass.contains(SrcReg)) {

      if (isMicroMips)
      if (isMicroMips)

        Opc = Mips::MOVE16_MM;
        Opc = Mips::MOVE16_MM;

      else
      else

        Opc = Mips::ADDu, ZeroReg = Mips::ZERO;
        Opc = Mips::OR, ZeroReg = Mips::ZERO;

    } else if (Mips::CCRRegClass.contains(SrcReg))
    } else if (Mips::CCRRegClass.contains(SrcReg))

      Opc = Mips::CFC1;
      Opc = Mips::CFC1;

    else if (Mips::FGR32RegClass.contains(SrcReg))
    else if (Mips::FGR32RegClass.contains(SrcReg))

      Opc = Mips::MFC1;
      Opc = Mips::MFC1;

    else if (Mips::HI32RegClass.contains(SrcReg)) {
    else if (Mips::HI32RegClass.contains(SrcReg)) {

      Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
      Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;

      SrcReg = 0;
      SrcReg = 0;

    } else if (Mips::LO32RegClass.contains(SrcReg)) {
    } else if (Mips::LO32RegClass.contains(SrcReg)) {

Show All 36 Linesvoid MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,

  else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
  else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))

    Opc = Mips::FMOV_S;
    Opc = Mips::FMOV_S;

  else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
  else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))

    Opc = Mips::FMOV_D32;
    Opc = Mips::FMOV_D32;

  else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
  else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))

    Opc = Mips::FMOV_D64;
    Opc = Mips::FMOV_D64;

  else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
  else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.

    if (Mips::GPR64RegClass.contains(SrcReg))
    if (Mips::GPR64RegClass.contains(SrcReg))

      Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64;
      Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;

    else if (Mips::HI64RegClass.contains(SrcReg))
    else if (Mips::HI64RegClass.contains(SrcReg))

      Opc = Mips::MFHI64, SrcReg = 0;
      Opc = Mips::MFHI64, SrcReg = 0;

    else if (Mips::LO64RegClass.contains(SrcReg))
    else if (Mips::LO64RegClass.contains(SrcReg))

      Opc = Mips::MFLO64, SrcReg = 0;
      Opc = Mips::MFLO64, SrcReg = 0;

    else if (Mips::FGR64RegClass.contains(SrcReg))
    else if (Mips::FGR64RegClass.contains(SrcReg))

      Opc = Mips::DMFC1;
      Opc = Mips::DMFC1;

  }
  }

  else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
  else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.

▲ Show 20 Lines • Show All 487 Lines • Show Last 20 Lines
test/MC/Disassembler/Mips/mips1/valid-mips1-el.txt
Show First 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
0x79 0xef 0xf4 0x89 # CHECK: lwl $20, -4231($15)
0x79 0xef 0xf4 0x89 # CHECK: lwl $20, -4231($15)

0x35 0xb5 0x80 0x9b # CHECK: lwr $zero, -19147($gp)
0x35 0xb5 0x80 0x9b # CHECK: lwr $zero, -19147($gp)

0x00 0xd8 0x07 0x44 # CHECK: mfc1 $7, $f27
0x00 0xd8 0x07 0x44 # CHECK: mfc1 $7, $f27

0x10 0x98 0x00 0x00 # CHECK: mfhi $19
0x10 0x98 0x00 0x00 # CHECK: mfhi $19

0x10 0xe8 0x00 0x00 # CHECK: mfhi $sp
0x10 0xe8 0x00 0x00 # CHECK: mfhi $sp

0x12 0x88 0x00 0x00 # CHECK: mflo $17
0x12 0x88 0x00 0x00 # CHECK: mflo $17

0x06 0x75 0x20 0x46 # CHECK: mov.d $f20, $f14
0x06 0x75 0x20 0x46 # CHECK: mov.d $f20, $f14

0x86 0xd8 0x00 0x46 # CHECK: mov.s $f2, $f27
0x86 0xd8 0x00 0x46 # CHECK: mov.s $f2, $f27

0x25 0xf0 0x80 0x00 # CHECK: move $fp, $4

0x25 0xc8 0xc0 0x00 # CHECK: move $25, $6

0x21 0xf0 0x80 0x00 # CHECK: move $fp, $4
0x21 0xf0 0x80 0x00 # CHECK: move $fp, $4

0x21 0xc8 0xc0 0x00 # CHECK: move $25, $6
0x21 0xc8 0xc0 0x00 # CHECK: move $25, $6

0x00 0x48 0x9e 0x44 # CHECK: mtc1 $fp, $f9
0x00 0x48 0x9e 0x44 # CHECK: mtc1 $fp, $f9

0x11 0x00 0x20 0x02 # CHECK: mthi $17
0x11 0x00 0x20 0x02 # CHECK: mthi $17

0x13 0x00 0xa0 0x03 # CHECK: mtlo $sp
0x13 0x00 0xa0 0x03 # CHECK: mtlo $sp

0x13 0x00 0x20 0x03 # CHECK: mtlo $25
0x13 0x00 0x20 0x03 # CHECK: mtlo $25

0x02 0xa5 0x30 0x46 # CHECK: mul.d $f20, $f20, $f16
0x02 0xa5 0x30 0x46 # CHECK: mul.d $f20, $f20, $f16

0x82 0x57 0x02 0x46 # CHECK: mul.s $f30, $f10, $f2
0x82 0x57 0x02 0x46 # CHECK: mul.s $f30, $f10, $f2

▲ Show 20 Lines • Show All 48 Lines • Show Last 20 Lines
test/MC/Disassembler/Mips/mips1/valid-mips1.txt
Show All 10 Lines
0x00 0x02 0x11 0xc2 # CHECK: srl $2, $2, 7
0x00 0x02 0x11 0xc2 # CHECK: srl $2, $2, 7

0x00 0x03 0x10 0x23 # CHECK: negu $2, $3
0x00 0x03 0x10 0x23 # CHECK: negu $2, $3

0x00 0x07 0x38 0x27 # CHECK: nor $7, $zero, $7
0x00 0x07 0x38 0x27 # CHECK: nor $7, $zero, $7

0x00 0x07 0x3c 0x80 # CHECK: sll $7, $7, 18
0x00 0x07 0x3c 0x80 # CHECK: sll $7, $7, 18

0x00 0x11 0x8b 0xc3 # CHECK: sra $17, $17, 15
0x00 0x11 0x8b 0xc3 # CHECK: sra $17, $17, 15

0x00 0x17 0x8b 0xc3 # CHECK: sra $17, $23, 15
0x00 0x17 0x8b 0xc3 # CHECK: sra $17, $23, 15

0x00 0x4c 0xb8 0x24 # CHECK: and $23, $2, $12
0x00 0x4c 0xb8 0x24 # CHECK: and $23, $2, $12

0x00 0x80 0xf0 0x21 # CHECK: move $fp, $4
0x00 0x80 0xf0 0x21 # CHECK: move $fp, $4

0x00 0x80 0xf0 0x25 # CHECK: move $fp, $4

0x00 0x86 0x48 0x21 # CHECK: addu $9, $4, $6
0x00 0x86 0x48 0x21 # CHECK: addu $9, $4, $6

0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4
0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4

0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4
0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4

0x00 0x9e 0x90 0x26 # CHECK: xor $18, $4, $fp
0x00 0x9e 0x90 0x26 # CHECK: xor $18, $4, $fp

0x00 0xc0 0xc8 0x21 # CHECK: move $25, $6
0x00 0xc0 0xc8 0x21 # CHECK: move $25, $6

0x00 0xc0 0xc8 0x25 # CHECK: move $25, $6

0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9
0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9

0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9
0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9

0x01 0x32 0x00 0x19 # CHECK: multu $9, $18
0x01 0x32 0x00 0x19 # CHECK: multu $9, $18

0x01 0x7b 0xb8 0x2a # CHECK: slt $23, $11, $27
0x01 0x7b 0xb8 0x2a # CHECK: slt $23, $11, $27

0x02 0x1d 0x60 0x25 # CHECK: or $12, $16, $sp
0x02 0x1d 0x60 0x25 # CHECK: or $12, $16, $sp

0x02 0x20 0x00 0x11 # CHECK: mthi $17
0x02 0x20 0x00 0x11 # CHECK: mthi $17

0x02 0x45 0xb8 0x20 # CHECK: add $23, $18, $5
0x02 0x45 0xb8 0x20 # CHECK: add $23, $18, $5

0x02 0x6c 0xb0 0x22 # CHECK: sub $22, $19, $12
0x02 0x6c 0xb0 0x22 # CHECK: sub $22, $19, $12

▲ Show 20 Lines • Show All 79 Lines • Show Last 20 Lines
test/MC/Disassembler/Mips/mips2/valid-mips2-el.txt
Show First 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
0x00 0xd8 0x07 0x44 # CHECK: mfc1 $7, $f27
0x00 0xd8 0x07 0x44 # CHECK: mfc1 $7, $f27

0x10 0x98 0x00 0x00 # CHECK: mfhi $19
0x10 0x98 0x00 0x00 # CHECK: mfhi $19

0x10 0xe8 0x00 0x00 # CHECK: mfhi $sp
0x10 0xe8 0x00 0x00 # CHECK: mfhi $sp

0x12 0x88 0x00 0x00 # CHECK: mflo $17
0x12 0x88 0x00 0x00 # CHECK: mflo $17

0x06 0x75 0x20 0x46 # CHECK: mov.d $f20, $f14
0x06 0x75 0x20 0x46 # CHECK: mov.d $f20, $f14

0x86 0xd8 0x00 0x46 # CHECK: mov.s $f2, $f27
0x86 0xd8 0x00 0x46 # CHECK: mov.s $f2, $f27

0x21 0xf0 0x80 0x00 # CHECK: move $fp, $4
0x21 0xf0 0x80 0x00 # CHECK: move $fp, $4

0x21 0xc8 0xc0 0x00 # CHECK: move $25, $6
0x21 0xc8 0xc0 0x00 # CHECK: move $25, $6

0x25 0xf0 0x80 0x00 # CHECK: move $fp, $4

0x25 0xc8 0xc0 0x00 # CHECK: move $25, $6

0x00 0x48 0x9e 0x44 # CHECK: mtc1 $fp, $f9
0x00 0x48 0x9e 0x44 # CHECK: mtc1 $fp, $f9

0x11 0x00 0x20 0x02 # CHECK: mthi $17
0x11 0x00 0x20 0x02 # CHECK: mthi $17

0x13 0x00 0xa0 0x03 # CHECK: mtlo $sp
0x13 0x00 0xa0 0x03 # CHECK: mtlo $sp

0x13 0x00 0x20 0x03 # CHECK: mtlo $25
0x13 0x00 0x20 0x03 # CHECK: mtlo $25

0x02 0xa5 0x30 0x46 # CHECK: mul.d $f20, $f20, $f16
0x02 0xa5 0x30 0x46 # CHECK: mul.d $f20, $f20, $f16

0x82 0x57 0x02 0x46 # CHECK: mul.s $f30, $f10, $f2
0x82 0x57 0x02 0x46 # CHECK: mul.s $f30, $f10, $f2

0x18 0x00 0xb4 0x03 # CHECK: mult $sp, $20
0x18 0x00 0xb4 0x03 # CHECK: mult $sp, $20

0x18 0x00 0xa2 0x03 # CHECK: mult $sp, $2
0x18 0x00 0xa2 0x03 # CHECK: mult $sp, $2

▲ Show 20 Lines • Show All 75 Lines • Show Last 20 Lines
test/MC/Disassembler/Mips/mips2/valid-mips2.txt
Show All 13 Lines
0x00 0x03 0x10 0x23 # CHECK: negu $2, $3
0x00 0x03 0x10 0x23 # CHECK: negu $2, $3

0x00 0x07 0x38 0x27 # CHECK: nor $7, $zero, $7
0x00 0x07 0x38 0x27 # CHECK: nor $7, $zero, $7

0x00 0x07 0x3c 0x80 # CHECK: sll $7, $7, 18
0x00 0x07 0x3c 0x80 # CHECK: sll $7, $7, 18

0x00 0x11 0x8b 0xc3 # CHECK: sra $17, $17, 15
0x00 0x11 0x8b 0xc3 # CHECK: sra $17, $17, 15

0x00 0x17 0x8b 0xc3 # CHECK: sra $17, $23, 15
0x00 0x17 0x8b 0xc3 # CHECK: sra $17, $23, 15

0x00 0x4c 0xb8 0x24 # CHECK: and $23, $2, $12
0x00 0x4c 0xb8 0x24 # CHECK: and $23, $2, $12

0x00 0x53 0x21 0x72 # CHECK: tlt $2, $19, 133
0x00 0x53 0x21 0x72 # CHECK: tlt $2, $19, 133

0x00 0x80 0xf0 0x21 # CHECK: move $fp, $4
0x00 0x80 0xf0 0x21 # CHECK: move $fp, $4

0x00 0x80 0xf0 0x25 # CHECK: move $fp, $4

0x00 0x86 0x48 0x21 # CHECK: addu $9, $4, $6
0x00 0x86 0x48 0x21 # CHECK: addu $9, $4, $6

0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4
0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4

0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4
0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4

0x00 0x9e 0x90 0x26 # CHECK: xor $18, $4, $fp
0x00 0x9e 0x90 0x26 # CHECK: xor $18, $4, $fp

0x00 0xa7 0x9b 0x34 # CHECK: teq $5, $7, 620
0x00 0xa7 0x9b 0x34 # CHECK: teq $5, $7, 620

0x00 0xb3 0x55 0x30 # CHECK: tge $5, $19, 340
0x00 0xb3 0x55 0x30 # CHECK: tge $5, $19, 340

0x00 0xc0 0xc8 0x21 # CHECK: move $25, $6
0x00 0xc0 0xc8 0x21 # CHECK: move $25, $6

0x00 0xc0 0xc8 0x25 # CHECK: move $25, $6

0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17
0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17

0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885
0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885

0x00 0xea 0x00 0x30 # CHECK: tge $7, $10
0x00 0xea 0x00 0x30 # CHECK: tge $7, $10

0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9
0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9

0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9
0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9

0x01 0x32 0x00 0x19 # CHECK: multu $9, $18
0x01 0x32 0x00 0x19 # CHECK: multu $9, $18

0x01 0x70 0x00 0x33 # CHECK: tltu $11, $16
0x01 0x70 0x00 0x33 # CHECK: tltu $11, $16

0x01 0x7b 0xb8 0x2a # CHECK: slt $23, $11, $27
0x01 0x7b 0xb8 0x2a # CHECK: slt $23, $11, $27

▲ Show 20 Lines • Show All 125 Lines • Show Last 20 Lines
test/MC/Disassembler/Mips/mips3/valid-mips3-el.txt
Show First 20 Lines • Show All 112 Lines • ▼ Show 20 Lines
0x00 0xd8 0x07 0x44 # CHECK: mfc1 $7, $f27
0x00 0xd8 0x07 0x44 # CHECK: mfc1 $7, $f27

0x10 0x98 0x00 0x00 # CHECK: mfhi $19
0x10 0x98 0x00 0x00 # CHECK: mfhi $19

0x10 0xe8 0x00 0x00 # CHECK: mfhi $sp
0x10 0xe8 0x00 0x00 # CHECK: mfhi $sp

0x12 0x88 0x00 0x00 # CHECK: mflo $17
0x12 0x88 0x00 0x00 # CHECK: mflo $17

0x06 0x75 0x20 0x46 # CHECK: mov.d $f20, $f14
0x06 0x75 0x20 0x46 # CHECK: mov.d $f20, $f14

0x86 0xd8 0x00 0x46 # CHECK: mov.s $f2, $f27
0x86 0xd8 0x00 0x46 # CHECK: mov.s $f2, $f27

0x21 0xf0 0x80 0x00 # CHECK: move $fp, $4
0x21 0xf0 0x80 0x00 # CHECK: move $fp, $4

0x21 0xc8 0xc0 0x00 # CHECK: move $25, $6
0x21 0xc8 0xc0 0x00 # CHECK: move $25, $6

0x25 0xf0 0x80 0x00 # CHECK: move $fp, $4

0x25 0xc8 0xc0 0x00 # CHECK: move $25, $6

0x00 0x48 0x9e 0x44 # CHECK: mtc1 $fp, $f9
0x00 0x48 0x9e 0x44 # CHECK: mtc1 $fp, $f9

0x11 0x00 0x20 0x02 # CHECK: mthi $17
0x11 0x00 0x20 0x02 # CHECK: mthi $17

0x13 0x00 0xa0 0x03 # CHECK: mtlo $sp
0x13 0x00 0xa0 0x03 # CHECK: mtlo $sp

0x13 0x00 0x20 0x03 # CHECK: mtlo $25
0x13 0x00 0x20 0x03 # CHECK: mtlo $25

0x02 0xa5 0x30 0x46 # CHECK: mul.d $f20, $f20, $f16
0x02 0xa5 0x30 0x46 # CHECK: mul.d $f20, $f20, $f16

0x82 0x57 0x02 0x46 # CHECK: mul.s $f30, $f10, $f2
0x82 0x57 0x02 0x46 # CHECK: mul.s $f30, $f10, $f2

0x18 0x00 0xb4 0x03 # CHECK: mult $sp, $20
0x18 0x00 0xb4 0x03 # CHECK: mult $sp, $20

0x18 0x00 0xa2 0x03 # CHECK: mult $sp, $2
0x18 0x00 0xa2 0x03 # CHECK: mult $sp, $2

▲ Show 20 Lines • Show All 81 Lines • Show Last 20 Lines
test/MC/Disassembler/Mips/mips3/valid-mips3.txt
Show All 29 Lines
0x00 0x17 0x8b 0xc3 # CHECK: sra $17, $23, 15
0x00 0x17 0x8b 0xc3 # CHECK: sra $17, $23, 15

0x00 0x1c 0xe2 0xbb # CHECK: dsra $gp, $gp, 10
0x00 0x1c 0xe2 0xbb # CHECK: dsra $gp, $gp, 10

0x00 0x1c 0xe2 0xbf # CHECK: dsra32 $gp, $gp, 10
0x00 0x1c 0xe2 0xbf # CHECK: dsra32 $gp, $gp, 10

0x00 0x3f 0x98 0x2c # CHECK: dadd $19, $1, $ra
0x00 0x3f 0x98 0x2c # CHECK: dadd $19, $1, $ra

0x00 0x3f 0x98 0x2d # CHECK: daddu $19, $1, $ra
0x00 0x3f 0x98 0x2d # CHECK: daddu $19, $1, $ra

0x00 0x4c 0xb8 0x24 # CHECK: and $23, $2, $12
0x00 0x4c 0xb8 0x24 # CHECK: and $23, $2, $12

0x00 0x53 0x21 0x72 # CHECK: tlt $2, $19, 133
0x00 0x53 0x21 0x72 # CHECK: tlt $2, $19, 133

0x00 0x80 0xf0 0x21 # CHECK: move $fp, $4
0x00 0x80 0xf0 0x21 # CHECK: move $fp, $4

0x00 0x80 0xf0 0x25 # CHECK: move $fp, $4

0x00 0x80 0xf0 0x2d # CHECK: move $fp, $4

0x00 0x86 0x48 0x21 # CHECK: addu $9, $4, $6
0x00 0x86 0x48 0x21 # CHECK: addu $9, $4, $6

0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4
0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4

0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4
0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4

0x00 0x9e 0x90 0x26 # CHECK: xor $18, $4, $fp
0x00 0x9e 0x90 0x26 # CHECK: xor $18, $4, $fp

0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6
0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6

0x00 0xa7 0x9b 0x34 # CHECK: teq $5, $7, 620
0x00 0xa7 0x9b 0x34 # CHECK: teq $5, $7, 620

0x00 0xb3 0x55 0x30 # CHECK: tge $5, $19, 340
0x00 0xb3 0x55 0x30 # CHECK: tge $5, $19, 340

0x00 0xba 0x28 0x2f # CHECK: dsubu $5, $5, $26
0x00 0xba 0x28 0x2f # CHECK: dsubu $5, $5, $26

0x00 0xc0 0xc8 0x21 # CHECK: move $25, $6
0x00 0xc0 0xc8 0x21 # CHECK: move $25, $6

0x00 0xc0 0xc8 0x25 # CHECK: move $25, $6

0x00 0xc0 0xc8 0x2d # CHECK: move $25, $6

0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17
0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17

0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885
0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885

0x00 0xea 0x00 0x30 # CHECK: tge $7, $10
0x00 0xea 0x00 0x30 # CHECK: tge $7, $10

0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9
0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9

0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9
0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9

0x01 0x32 0x00 0x19 # CHECK: multu $9, $18
0x01 0x32 0x00 0x19 # CHECK: multu $9, $18

0x01 0x70 0x00 0x33 # CHECK: tltu $11, $16
0x01 0x70 0x00 0x33 # CHECK: tltu $11, $16

0x01 0x7b 0xb8 0x2a # CHECK: slt $23, $11, $27
0x01 0x7b 0xb8 0x2a # CHECK: slt $23, $11, $27

▲ Show 20 Lines • Show All 155 Lines • Show Last 20 Lines
test/MC/Disassembler/Mips/mips32/valid-mips32-el.txt
# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux | FileCheck %s
# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux | FileCheck %s

0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14

0x85 0x39 0x00 0x46 # CHECK: abs.s $f6, $f7
0x85 0x39 0x00 0x46 # CHECK: abs.s $f6, $f7

0x20 0x48 0xc7 0x00 # CHECK: add $9, $6, $7
0x20 0x48 0xc7 0x00 # CHECK: add $9, $6, $7

0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14

0x40 0x32 0x07 0x46 # CHECK: add.s $f9, $f6, $f7
0x40 0x32 0x07 0x46 # CHECK: add.s $f9, $f6, $f7

0x67 0x45 0xc9 0x20 # CHECK: addi $9, $6, 17767
0x67 0x45 0xc9 0x20 # CHECK: addi $9, $6, 17767

0x67 0xc5 0xc9 0x24 # CHECK: addiu $9, $6, -15001
0x67 0xc5 0xc9 0x24 # CHECK: addiu $9, $6, -15001

0x21 0x48 0xc7 0x00 # CHECK: addu $9, $6, $7
0x21 0x48 0xc7 0x00 # CHECK: addu $9, $6, $7

0x21 0xf0 0x80 0x00 # CHECK: move $fp, $4

0x24 0x48 0xc7 0x00 # CHECK: and $9, $6, $7
0x24 0x48 0xc7 0x00 # CHECK: and $9, $6, $7

0x25 0xf0 0x80 0x00 # CHECK: move $fp, $4

0x67 0x45 0xc9 0x30 # CHECK: andi $9, $6, 17767
0x67 0x45 0xc9 0x30 # CHECK: andi $9, $6, 17767

0x4c 0x01 0x00 0x10 # CHECK: b 1332
0x4c 0x01 0x00 0x10 # CHECK: b 1332

0x4c 0x01 0x00 0x45 # CHECK: bc1f 1332
0x4c 0x01 0x00 0x45 # CHECK: bc1f 1332

0x4c 0x01 0x1c 0x45 # CHECK: bc1f $fcc7, 1332
0x4c 0x01 0x1c 0x45 # CHECK: bc1f $fcc7, 1332

0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332

0x4c 0x01 0x1d 0x45 # CHECK: bc1t $fcc7, 1332
0x4c 0x01 0x1d 0x45 # CHECK: bc1t $fcc7, 1332

0x4c 0x01 0x26 0x11 # CHECK: beq $9, $6, 1332
0x4c 0x01 0x26 0x11 # CHECK: beq $9, $6, 1332

0x4c 0x01 0xc1 0x04 # CHECK: bgez $6, 1332
0x4c 0x01 0xc1 0x04 # CHECK: bgez $6, 1332

▲ Show 20 Lines • Show All 133 Lines • Show Last 20 Lines
test/MC/Disassembler/Mips/mips32/valid-mips32.txt
Show All 9 Lines
0x00 0x5d 0x18 0x01 # CHECK: movt $3, $2, $fcc7
0x00 0x5d 0x18 0x01 # CHECK: movt $3, $2, $fcc7

0x00 0x65 0x00 0x18 # CHECK: mult $3, $5
0x00 0x65 0x00 0x18 # CHECK: mult $3, $5

0x00 0x65 0x00 0x19 # CHECK: multu $3, $5
0x00 0x65 0x00 0x19 # CHECK: multu $3, $5

0x00 0x65 0x18 0x25 # CHECK: or $3, $3, $5
0x00 0x65 0x18 0x25 # CHECK: or $3, $3, $5

0x00 0x65 0x18 0x26 # CHECK: xor $3, $3, $5
0x00 0x65 0x18 0x26 # CHECK: xor $3, $3, $5

0x00 0x65 0x18 0x2a # CHECK: slt $3, $3, $5
0x00 0x65 0x18 0x2a # CHECK: slt $3, $3, $5

0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5
0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5

0x00 0x65 0x20 0x23 # CHECK: subu $4, $3, $5
0x00 0x65 0x20 0x23 # CHECK: subu $4, $3, $5

0x00 0x80 0xf0 0x21 # CHECK: move $fp, $4

0x00 0x80 0xf0 0x25 # CHECK: move $fp, $4

0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4
0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4

0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5
0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5

0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5
0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5

0x00 0xa3 0x10 0x06 # CHECK: srlv $2, $3, $5
0x00 0xa3 0x10 0x06 # CHECK: srlv $2, $3, $5

0x00 0xa3 0x10 0x07 # CHECK: srav $2, $3, $5
0x00 0xa3 0x10 0x07 # CHECK: srav $2, $3, $5

0x00 0xc7 0x48 0x20 # CHECK: add $9, $6, $7
0x00 0xc7 0x48 0x20 # CHECK: add $9, $6, $7

0x00 0xc7 0x48 0x21 # CHECK: addu $9, $6, $7
0x00 0xc7 0x48 0x21 # CHECK: addu $9, $6, $7

0x00 0xc7 0x48 0x22 # CHECK: sub $9, $6, $7
0x00 0xc7 0x48 0x22 # CHECK: sub $9, $6, $7

▲ Show 20 Lines • Show All 133 Lines • Show Last 20 Lines
test/MC/Disassembler/Mips/mips32_le.txt
Show First 20 Lines • Show All 267 Lines • ▼ Show 20 Lines



# CHECK: mov.d $f6, $f8
# CHECK: mov.d $f6, $f8

0x86 0x41 0x20 0x46
0x86 0x41 0x20 0x46




# CHECK: mov.s $f6, $f7
# CHECK: mov.s $f6, $f7

0x86 0x39 0x00 0x46
0x86 0x39 0x00 0x46




# CHECK: move $7, $8
# CHECK: move $7, $8

0x21,0x38,0x00,0x01
0x25,0x38,0x00,0x01




# CHECK: move $3, $2
# CHECK: move $3, $2

0x25,0x18,0x40,0x00
0x25,0x18,0x40,0x00




# CHECK: movf $3, $2, $fcc7
# CHECK: movf $3, $2, $fcc7

0x01,0x18,0x5c,0x00
0x01,0x18,0x5c,0x00




# CHECK: movf.d $f4, $f2, $fcc7
# CHECK: movf.d $f4, $f2, $fcc7

▲ Show 20 Lines • Show All 166 Lines • Show Last 20 Lines
test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
Show All 11 Lines
0x00 0x26 0x49 0xc2 # CHECK: rotr $9, $6, 7
0x00 0x26 0x49 0xc2 # CHECK: rotr $9, $6, 7

0x00 0x65 0x00 0x18 # CHECK: mult $3, $5
0x00 0x65 0x00 0x18 # CHECK: mult $3, $5

0x00 0x65 0x00 0x19 # CHECK: multu $3, $5
0x00 0x65 0x00 0x19 # CHECK: multu $3, $5

0x00 0x65 0x18 0x25 # CHECK: or $3, $3, $5
0x00 0x65 0x18 0x25 # CHECK: or $3, $3, $5

0x00 0x65 0x18 0x26 # CHECK: xor $3, $3, $5
0x00 0x65 0x18 0x26 # CHECK: xor $3, $3, $5

0x00 0x65 0x18 0x2a # CHECK: slt $3, $3, $5
0x00 0x65 0x18 0x2a # CHECK: slt $3, $3, $5

0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5
0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5

0x00 0x65 0x20 0x23 # CHECK: subu $4, $3, $5
0x00 0x65 0x20 0x23 # CHECK: subu $4, $3, $5

0x00 0x80 0xf0 0x21 # CHECK: move $fp, $4

0x00 0x80 0xf0 0x25 # CHECK: move $fp, $4

0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4
0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4

0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5
0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5

0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5
0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5

0x00 0xa3 0x10 0x06 # CHECK: srlv $2, $3, $5
0x00 0xa3 0x10 0x06 # CHECK: srlv $2, $3, $5

0x00 0xa3 0x10 0x07 # CHECK: srav $2, $3, $5
0x00 0xa3 0x10 0x07 # CHECK: srav $2, $3, $5

0x00 0xc7 0x48 0x20 # CHECK: add $9, $6, $7
0x00 0xc7 0x48 0x20 # CHECK: add $9, $6, $7

0x00 0xc7 0x48 0x21 # CHECK: addu $9, $6, $7
0x00 0xc7 0x48 0x21 # CHECK: addu $9, $6, $7

0x00 0xc7 0x48 0x22 # CHECK: sub $9, $6, $7
0x00 0xc7 0x48 0x22 # CHECK: sub $9, $6, $7

▲ Show 20 Lines • Show All 149 Lines • Show Last 20 Lines
test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt
Show First 20 Lines • Show All 120 Lines • ▼ Show 20 Lines
0x12 0x88 0x00 0x00 # CHECK: mflo $17
0x12 0x88 0x00 0x00 # CHECK: mflo $17

0x06 0x75 0x20 0x46 # CHECK: mov.d $f20, $f14
0x06 0x75 0x20 0x46 # CHECK: mov.d $f20, $f14

0x86 0xd8 0x00 0x46 # CHECK: mov.s $f2, $f27
0x86 0xd8 0x00 0x46 # CHECK: mov.s $f2, $f27

0x01 0xe0 0x1c 0x01 # CHECK: movf $gp, $8, $fcc7
0x01 0xe0 0x1c 0x01 # CHECK: movf $gp, $8, $fcc7

0x91 0x59 0x34 0x46 # CHECK: movf.d $f6, $f11, $fcc5
0x91 0x59 0x34 0x46 # CHECK: movf.d $f6, $f11, $fcc5

0xd1 0x2d 0x18 0x46 # CHECK: movf.s $f23, $f5, $fcc6
0xd1 0x2d 0x18 0x46 # CHECK: movf.s $f23, $f5, $fcc6

0x21 0xf0 0x80 0x00 # CHECK: move $fp, $4
0x21 0xf0 0x80 0x00 # CHECK: move $fp, $4

0x21 0xc8 0xc0 0x00 # CHECK: move $25, $6
0x21 0xc8 0xc0 0x00 # CHECK: move $25, $6

0x25 0xf0 0x80 0x00 # CHECK: move $fp, $4

0x25 0xc8 0xc0 0x00 # CHECK: move $25, $6

0x0b 0x18 0x30 0x02 # CHECK: movn $3, $17, $16
0x0b 0x18 0x30 0x02 # CHECK: movn $3, $17, $16

0xd3 0xae 0x3a 0x46 # CHECK: movn.d $f27, $f21, $26
0xd3 0xae 0x3a 0x46 # CHECK: movn.d $f27, $f21, $26

0x13 0x03 0x17 0x46 # CHECK: movn.s $f12, $f0, $23
0x13 0x03 0x17 0x46 # CHECK: movn.s $f12, $f0, $23

0x01 0x00 0x95 0x02 # CHECK: movt $zero, $20, $fcc5
0x01 0x00 0x95 0x02 # CHECK: movt $zero, $20, $fcc5

0x11 0x10 0x21 0x46 # CHECK: movt.d $f0, $f2, $fcc0
0x11 0x10 0x21 0x46 # CHECK: movt.d $f0, $f2, $fcc0

0x91 0x17 0x05 0x46 # CHECK: movt.s $f30, $f2, $fcc1
0x91 0x17 0x05 0x46 # CHECK: movt.s $f30, $f2, $fcc1

0x0a 0x28 0xc9 0x02 # CHECK: movz $5, $22, $9
0x0a 0x28 0xc9 0x02 # CHECK: movz $5, $22, $9

0x12 0xeb 0x29 0x46 # CHECK: movz.d $f12, $f29, $9
0x12 0xeb 0x29 0x46 # CHECK: movz.d $f12, $f29, $9

▲ Show 20 Lines • Show All 93 Lines • Show Last 20 Lines
test/MC/Disassembler/Mips/mips4/valid-mips4.txt
Show All 29 Lines
0x00 0x17 0x8b 0xc3 # CHECK: sra $17, $23, 15
0x00 0x17 0x8b 0xc3 # CHECK: sra $17, $23, 15

0x00 0x1c 0xe2 0xbb # CHECK: dsra $gp, $gp, 10
0x00 0x1c 0xe2 0xbb # CHECK: dsra $gp, $gp, 10

0x00 0x1c 0xe2 0xbf # CHECK: dsra32 $gp, $gp, 10
0x00 0x1c 0xe2 0xbf # CHECK: dsra32 $gp, $gp, 10

0x00 0x3f 0x98 0x2c # CHECK: dadd $19, $1, $ra
0x00 0x3f 0x98 0x2c # CHECK: dadd $19, $1, $ra

0x00 0x3f 0x98 0x2d # CHECK: daddu $19, $1, $ra
0x00 0x3f 0x98 0x2d # CHECK: daddu $19, $1, $ra

0x00 0x4c 0xb8 0x24 # CHECK: and $23, $2, $12
0x00 0x4c 0xb8 0x24 # CHECK: and $23, $2, $12

0x00 0x53 0x21 0x72 # CHECK: tlt $2, $19, 133
0x00 0x53 0x21 0x72 # CHECK: tlt $2, $19, 133

0x00 0x80 0xf0 0x21 # CHECK: move $fp, $4
0x00 0x80 0xf0 0x21 # CHECK: move $fp, $4

0x00 0x80 0xf0 0x25 # CHECK: move $fp, $4

0x00 0x80 0xf0 0x2d # CHECK: move $fp, $4

0x00 0x86 0x48 0x21 # CHECK: addu $9, $4, $6
0x00 0x86 0x48 0x21 # CHECK: addu $9, $4, $6

0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4
0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4

0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4
0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4

0x00 0x9e 0x90 0x26 # CHECK: xor $18, $4, $fp
0x00 0x9e 0x90 0x26 # CHECK: xor $18, $4, $fp

0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6
0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6

0x00 0xa7 0x9b 0x34 # CHECK: teq $5, $7, 620
0x00 0xa7 0x9b 0x34 # CHECK: teq $5, $7, 620

0x00 0xb3 0x55 0x30 # CHECK: tge $5, $19, 340
0x00 0xb3 0x55 0x30 # CHECK: tge $5, $19, 340

0x00 0xba 0x28 0x2f # CHECK: dsubu $5, $5, $26
0x00 0xba 0x28 0x2f # CHECK: dsubu $5, $5, $26

0x00 0xc0 0xc8 0x21 # CHECK: move $25, $6
0x00 0xc0 0xc8 0x21 # CHECK: move $25, $6

0x00 0xc0 0xc8 0x25 # CHECK: move $25, $6

0x00 0xc0 0xc8 0x2d # CHECK: move $25, $6

0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17
0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17

0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885
0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885

0x00 0xea 0x00 0x30 # CHECK: tge $7, $10
0x00 0xea 0x00 0x30 # CHECK: tge $7, $10

0x01 0x1c 0xe0 0x01 # CHECK: movf $gp, $8, $fcc7
0x01 0x1c 0xe0 0x01 # CHECK: movf $gp, $8, $fcc7

0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9
0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9

0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9
0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9

0x01 0x32 0x00 0x19 # CHECK: multu $9, $18
0x01 0x32 0x00 0x19 # CHECK: multu $9, $18

0x01 0x70 0x00 0x33 # CHECK: tltu $11, $16
0x01 0x70 0x00 0x33 # CHECK: tltu $11, $16

▲ Show 20 Lines • Show All 175 Lines • Show Last 20 Lines
test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt
Show First 20 Lines • Show All 142 Lines • ▼ Show 20 Lines
0x03 0x00 0x82 0x88 # CHECK: lwl $2, 3($4)
0x03 0x00 0x82 0x88 # CHECK: lwl $2, 3($4)

0x10 0x00 0xa3 0x98 # CHECK: lwr $3, 16($5)
0x10 0x00 0xa3 0x98 # CHECK: lwr $3, 16($5)

0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7
0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7

0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7
0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7

0x01 0x78 0x08 0x40 # CHECK: mfc0 $8, $15, 1
0x01 0x78 0x08 0x40 # CHECK: mfc0 $8, $15, 1

0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7
0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7

0x10 0x28 0x00 0x00 # CHECK: mfhi $5
0x10 0x28 0x00 0x00 # CHECK: mfhi $5

0x12 0x28 0x00 0x00 # CHECK: mflo $5
0x12 0x28 0x00 0x00 # CHECK: mflo $5

0x25 0x78 0xe0 0x03 # CEHCK: move $15, $ra

0x2d 0x78 0xe0 0x03 # CEHCK: move $15, $ra

0x86 0x41 0x20 0x46 # CHECK: mov.d $f6, $f8
0x86 0x41 0x20 0x46 # CHECK: mov.d $f6, $f8

0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7
0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7

0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7
0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7

0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7
0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7

0x01 0x78 0x89 0x40 # CHECK: mtc0 $9, $15, 1
0x01 0x78 0x89 0x40 # CHECK: mtc0 $9, $15, 1

0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7
0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7

0x11 0x00 0xe0 0x00 # CHECK: mthi $7
0x11 0x00 0xe0 0x00 # CHECK: mthi $7

0x13 0x00 0xe0 0x00 # CHECK: mtlo $7
0x13 0x00 0xe0 0x00 # CHECK: mtlo $7

▲ Show 20 Lines • Show All 62 Lines • Show Last 20 Lines
test/MC/Disassembler/Mips/mips64/valid-mips64.txt
Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9
0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9

0x02 0xea 0xe0 0x16 # CHECK: dsrlv $gp, $10, $23
0x02 0xea 0xe0 0x16 # CHECK: dsrlv $gp, $10, $23

0x02 0xed 0x00 0x1d # CHECK: dmultu $23, $13
0x02 0xed 0x00 0x1d # CHECK: dmultu $23, $13

0x03 0x1b 0xe0 0x14 # CHECK: dsllv $gp, $27, $24
0x03 0x1b 0xe0 0x14 # CHECK: dsllv $gp, $27, $24

0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19
0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19

0x03 0x56 0x00 0x1e # CHECK: ddiv $zero, $26, $22
0x03 0x56 0x00 0x1e # CHECK: ddiv $zero, $26, $22

0x03 0x78 0xe0 0x2f # CHECK: dsubu $gp, $27, $24
0x03 0x78 0xe0 0x2f # CHECK: dsubu $gp, $27, $24

0x03 0xc1 0x08 0x17 # CHECK: dsrav $1, $1, $fp
0x03 0xc1 0x08 0x17 # CHECK: dsrav $1, $1, $fp

0x03 0xe0 0x78 0x25 # CHECK: move $15, $ra

0x03 0xe0 0x78 0x2d # CHECK: move $15, $ra

0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332
0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332

0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332
0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332

0x08 0x00 0x01 0x4c # CHECK: j 1328
0x08 0x00 0x01 0x4c # CHECK: j 1328

0x0c 0x00 0x01 0x4c # CHECK: jal 1328
0x0c 0x00 0x01 0x4c # CHECK: jal 1328

0x10 0x00 0x01 0x4c # CHECK: b 1332
0x10 0x00 0x01 0x4c # CHECK: b 1332

0x11 0x26 0x01 0x4c # CHECK: beq $9, $6, 1332
0x11 0x26 0x01 0x4c # CHECK: beq $9, $6, 1332

0x15 0x26 0x01 0x4c # CHECK: bne $9, $6, 1332
0x15 0x26 0x01 0x4c # CHECK: bne $9, $6, 1332

0x18 0xc0 0x01 0x4c # CHECK: blez $6, 1332
0x18 0xc0 0x01 0x4c # CHECK: blez $6, 1332

▲ Show 20 Lines • Show All 177 Lines • Show Last 20 Lines
test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
Show First 20 Lines • Show All 162 Lines • ▼ Show 20 Lines
0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7
0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7

0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25
0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25

0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7
0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7

0x01 0x78 0x08 0x40 # CHECK: mfc0 $8, $15, 1
0x01 0x78 0x08 0x40 # CHECK: mfc0 $8, $15, 1

0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7
0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7

0x10 0x28 0x00 0x00 # CHECK: mfhi $5
0x10 0x28 0x00 0x00 # CHECK: mfhi $5

0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24
0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24

0x12 0x28 0x00 0x00 # CHECK: mflo $5
0x12 0x28 0x00 0x00 # CHECK: mflo $5

0x25 0x78 0xe0 0x03 # CHECK: move $15, $ra

0x2d 0x78 0xe0 0x03 # CHECK: move $15, $ra

0x86 0x41 0x20 0x46 # CHECK: mov.d $f6, $f8
0x86 0x41 0x20 0x46 # CHECK: mov.d $f6, $f8

0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7
0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7

0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7
0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7

0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16
0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16

0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7
0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7

0x01 0x78 0x89 0x40 # CHECK: mtc0 $9, $15, 1
0x01 0x78 0x89 0x40 # CHECK: mtc0 $9, $15, 1

0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7
0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7

0x11 0x00 0xe0 0x00 # CHECK: mthi $7
0x11 0x00 0xe0 0x00 # CHECK: mthi $7

▲ Show 20 Lines • Show All 63 Lines • Show Last 20 Lines
test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt
Show First 20 Lines • Show All 74 Lines • ▼ Show 20 Lines
0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9
0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9

0x02 0xea 0xe0 0x16 # CHECK: dsrlv $gp, $10, $23
0x02 0xea 0xe0 0x16 # CHECK: dsrlv $gp, $10, $23

0x02 0xed 0x00 0x1d # CHECK: dmultu $23, $13
0x02 0xed 0x00 0x1d # CHECK: dmultu $23, $13

0x03 0x1b 0xe0 0x14 # CHECK: dsllv $gp, $27, $24
0x03 0x1b 0xe0 0x14 # CHECK: dsllv $gp, $27, $24

0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19
0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19

0x03 0x56 0x00 0x1e # CHECK: ddiv $zero, $26, $22
0x03 0x56 0x00 0x1e # CHECK: ddiv $zero, $26, $22

0x03 0x78 0xe0 0x2f # CHECK: dsubu $gp, $27, $24
0x03 0x78 0xe0 0x2f # CHECK: dsubu $gp, $27, $24

0x03 0xc1 0x08 0x17 # CHECK: dsrav $1, $1, $fp
0x03 0xc1 0x08 0x17 # CHECK: dsrav $1, $1, $fp

0x03 0xe0 0x78 0x25 # CHECK: move $15, $ra

0x03 0xe0 0x78 0x2d # CHECK: move $15, $ra

0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332
0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332

0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332
0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332

0x08 0x00 0x01 0x4c # CHECK: j 1328
0x08 0x00 0x01 0x4c # CHECK: j 1328

0x0c 0x00 0x01 0x4c # CHECK: jal 1328
0x0c 0x00 0x01 0x4c # CHECK: jal 1328

0x10 0x00 0x01 0x4c # CHECK: b 1332
0x10 0x00 0x01 0x4c # CHECK: b 1332

0x11 0x26 0x01 0x4c # CHECK: beq $9, $6, 1332
0x11 0x26 0x01 0x4c # CHECK: beq $9, $6, 1332

0x15 0x26 0x01 0x4c # CHECK: bne $9, $6, 1332
0x15 0x26 0x01 0x4c # CHECK: bne $9, $6, 1332

0x18 0xc0 0x01 0x4c # CHECK: blez $6, 1332
0x18 0xc0 0x01 0x4c # CHECK: blez $6, 1332

▲ Show 20 Lines • Show All 183 Lines • Show Last 20 Lines
test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
Show First 20 Lines • Show All 159 Lines • ▼ Show 20 Lines
0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7
0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7

0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25
0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25

0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7
0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7

0x01 0x78 0x08 0x40 # CHECK: mfc0 $8, $15, 1
0x01 0x78 0x08 0x40 # CHECK: mfc0 $8, $15, 1

0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7
0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7

0x10 0x28 0x00 0x00 # CHECK: mfhi $5
0x10 0x28 0x00 0x00 # CHECK: mfhi $5

0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24
0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24

0x12 0x28 0x00 0x00 # CHECK: mflo $5
0x12 0x28 0x00 0x00 # CHECK: mflo $5

0x25 0x78 0xe0 0x03 # CEHCK: move $15, $ra

0x2d 0x78 0xe0 0x03 # CEHCK: move $15, $ra

0x86 0x41 0x20 0x46 # CHECK: mov.d $f6, $f8
0x86 0x41 0x20 0x46 # CHECK: mov.d $f6, $f8

0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7
0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7

0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7
0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7

0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16
0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16

0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7
0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7

0x01 0x78 0x89 0x40 # CHECK: mtc0 $9, $15, 1
0x01 0x78 0x89 0x40 # CHECK: mtc0 $9, $15, 1

0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7
0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7

0x11 0x00 0xe0 0x00 # CHECK: mthi $7
0x11 0x00 0xe0 0x00 # CHECK: mthi $7

▲ Show 20 Lines • Show All 63 Lines • Show Last 20 Lines
test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt
Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
0x02 0x11 0x00 0x1f # CHECK: ddivu $zero, $16, $17
0x02 0x11 0x00 0x1f # CHECK: ddivu $zero, $16, $17

0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19
0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19

0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19
0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19

0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20
0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20

0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20
0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20

0x02 0xc8 0x38 0x2e # CHECK: dsub $7, $22, $8
0x02 0xc8 0x38 0x2e # CHECK: dsub $7, $22, $8

0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9
0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9

0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19
0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19

0x03 0xe0 0x78 0x25 # CHECK: move $15, $ra

0x03 0xe0 0x78 0x2d # CHECK: move $15, $ra

0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332
0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332

0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332
0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332

0x08 0x00 0x01 0x4c # CHECK: j 1328
0x08 0x00 0x01 0x4c # CHECK: j 1328

0x0c 0x00 0x01 0x4c # CHECK: jal 1328
0x0c 0x00 0x01 0x4c # CHECK: jal 1328

0x10 0x00 0x01 0x4c # CHECK: b 1332
0x10 0x00 0x01 0x4c # CHECK: b 1332

0x11 0x26 0x01 0x4c # CHECK: beq $9, $6, 1332
0x11 0x26 0x01 0x4c # CHECK: beq $9, $6, 1332

0x15 0x26 0x01 0x4c # CHECK: bne $9, $6, 1332
0x15 0x26 0x01 0x4c # CHECK: bne $9, $6, 1332

0x18 0xc0 0x01 0x4c # CHECK: blez $6, 1332
0x18 0xc0 0x01 0x4c # CHECK: blez $6, 1332

▲ Show 20 Lines • Show All 167 Lines • Show Last 20 Lines
test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
Show First 20 Lines • Show All 159 Lines • ▼ Show 20 Lines
0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7
0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7

0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25
0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25

0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7
0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7

0x01 0x78 0x08 0x40 # CHECK: mfc0 $8, $15, 1
0x01 0x78 0x08 0x40 # CHECK: mfc0 $8, $15, 1

0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7
0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7

0x10 0x28 0x00 0x00 # CHECK: mfhi $5
0x10 0x28 0x00 0x00 # CHECK: mfhi $5

0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24
0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24

0x12 0x28 0x00 0x00 # CHECK: mflo $5
0x12 0x28 0x00 0x00 # CHECK: mflo $5

0x25 0x78 0xe0 0x03 # CEHCK: move $15, $ra

0x2d 0x78 0xe0 0x03 # CEHCK: move $15, $ra

0x86 0x41 0x20 0x46 # CHECK: mov.d $f6, $f8
0x86 0x41 0x20 0x46 # CHECK: mov.d $f6, $f8

0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7
0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7

0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7
0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7

0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16
0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16

0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7
0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7

0x01 0x78 0x89 0x40 # CHECK: mtc0 $9, $15, 1
0x01 0x78 0x89 0x40 # CHECK: mtc0 $9, $15, 1

0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7
0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7

0x11 0x00 0xe0 0x00 # CHECK: mthi $7
0x11 0x00 0xe0 0x00 # CHECK: mthi $7

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test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
0x02 0x11 0x00 0x1f # CHECK: ddivu $zero, $16, $17
0x02 0x11 0x00 0x1f # CHECK: ddivu $zero, $16, $17

0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19
0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19

0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19
0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19

0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20
0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20

0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20
0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20

0x02 0xc8 0x38 0x2e # CHECK: dsub $7, $22, $8
0x02 0xc8 0x38 0x2e # CHECK: dsub $7, $22, $8

0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9
0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9

0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19
0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19

0x03 0xe0 0x78 0x25 # CHECK: move $15, $ra

0x03 0xe0 0x78 0x2d # CHECK: move $15, $ra

0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332
0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332

0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332
0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332

0x08 0x00 0x01 0x4c # CHECK: j 1328
0x08 0x00 0x01 0x4c # CHECK: j 1328

0x0c 0x00 0x01 0x4c # CHECK: jal 1328
0x0c 0x00 0x01 0x4c # CHECK: jal 1328

0x10 0x00 0x01 0x4c # CHECK: b 1332
0x10 0x00 0x01 0x4c # CHECK: b 1332

0x11 0x26 0x01 0x4c # CHECK: beq $9, $6, 1332
0x11 0x26 0x01 0x4c # CHECK: beq $9, $6, 1332

0x15 0x26 0x01 0x4c # CHECK: bne $9, $6, 1332
0x15 0x26 0x01 0x4c # CHECK: bne $9, $6, 1332

0x18 0xc0 0x01 0x4c # CHECK: blez $6, 1332
0x18 0xc0 0x01 0x4c # CHECK: blez $6, 1332

▲ Show 20 Lines • Show All 168 Lines • Show Last 20 Lines
test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
Show First 20 Lines • Show All 122 Lines • ▼ Show 20 Lines
0x1f 0x10 0x04 0x46 # CHECK: maxa.s $f0, $f2, $f4
0x1f 0x10 0x04 0x46 # CHECK: maxa.s $f0, $f2, $f4

0x01 0x78 0x08 0x40 # CHECK: mfc0 $8, $15, 1
0x01 0x78 0x08 0x40 # CHECK: mfc0 $8, $15, 1

0x1c 0x10 0x24 0x46 # CHECK: min.d $f0, $f2, $f4
0x1c 0x10 0x24 0x46 # CHECK: min.d $f0, $f2, $f4

0x1c 0x10 0x04 0x46 # CHECK: min.s $f0, $f2, $f4
0x1c 0x10 0x04 0x46 # CHECK: min.s $f0, $f2, $f4

0x1e 0x10 0x24 0x46 # CHECK: mina.d $f0, $f2, $f4
0x1e 0x10 0x24 0x46 # CHECK: mina.d $f0, $f2, $f4

0x1e 0x10 0x04 0x46 # CHECK: mina.s $f0, $f2, $f4
0x1e 0x10 0x04 0x46 # CHECK: mina.s $f0, $f2, $f4

0xda 0x10 0x64 0x00 # CHECK: mod $2, $3, $4
0xda 0x10 0x64 0x00 # CHECK: mod $2, $3, $4

0xdb 0x10 0x64 0x00 # CHECK: modu $2, $3, $4
0xdb 0x10 0x64 0x00 # CHECK: modu $2, $3, $4

0x25 0x78 0xe0 0x03 # CHECK: move $15, $ra

0x2d 0x78 0xe0 0x03 # CHECK: move $15, $ra

0x01 0x78 0x89 0x40 # CHECK: mtc0 $9, $15, 1
0x01 0x78 0x89 0x40 # CHECK: mtc0 $9, $15, 1

0x99 0x18 0x24 0x46 # CHECK: msubf.d $f2, $f3, $f4
0x99 0x18 0x24 0x46 # CHECK: msubf.d $f2, $f3, $f4

0x99 0x18 0x04 0x46 # CHECK: msubf.s $f2, $f3, $f4
0x99 0x18 0x04 0x46 # CHECK: msubf.s $f2, $f3, $f4

0xd8 0x10 0x64 0x00 # CHECK: muh $2, $3, $4
0xd8 0x10 0x64 0x00 # CHECK: muh $2, $3, $4

0xd9 0x10 0x64 0x00 # CHECK: muhu $2, $3, $4
0xd9 0x10 0x64 0x00 # CHECK: muhu $2, $3, $4

0x98 0x10 0x64 0x00 # CHECK: mul $2, $3, $4
0x98 0x10 0x64 0x00 # CHECK: mul $2, $3, $4

0x99 0x10 0x64 0x00 # CHECK: mulu $2, $3, $4
0x99 0x10 0x64 0x00 # CHECK: mulu $2, $3, $4

0x04 0x00 0x42 0x34 # CHECK: ori $2, $2, 4
0x04 0x00 0x42 0x34 # CHECK: ori $2, $2, 4

Show All 32 Lines
test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
Show All 39 Lines
0x00 0xea 0x00 0x30 # CHECK: tge $7, $10
0x00 0xea 0x00 0x30 # CHECK: tge $7, $10

0x01 0x70 0x00 0x33 # CHECK: tltu $11, $16
0x01 0x70 0x00 0x33 # CHECK: tltu $11, $16

0x01 0xed 0x00 0x32 # CHECK: tlt $15, $13
0x01 0xed 0x00 0x32 # CHECK: tlt $15, $13

0x02 0x1d 0xfe 0x33 # CHECK: tltu $16, $sp, 1016
0x02 0x1d 0xfe 0x33 # CHECK: tltu $16, $sp, 1016

0x02 0x8e 0x5e 0xf1 # CHECK: tgeu $20, $14, 379
0x02 0x8e 0x5e 0xf1 # CHECK: tgeu $20, $14, 379

0x02 0xdc 0x00 0x31 # CHECK: tgeu $22, $gp
0x02 0xdc 0x00 0x31 # CHECK: tgeu $22, $gp

0x03 0x20 0x80 0x52 # CHECK: dclz $16, $25
0x03 0x20 0x80 0x52 # CHECK: dclz $16, $25

0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp
0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp

0x03 0xe0 0x78 0x25 # CHECK: move $15, $ra

0x03 0xe0 0x78 0x2d # CHECK: move $15, $ra

0x04 0x11 0x14 0x9b # CHECK: bal 21104
0x04 0x11 0x14 0x9b # CHECK: bal 21104

0x04 0x66 0x56 0x78 # CHECK: dahi $3, 22136
0x04 0x66 0x56 0x78 # CHECK: dahi $3, 22136

0x04 0x7e 0xab 0xcd # CHECK: dati $3, -21555
0x04 0x7e 0xab 0xcd # CHECK: dati $3, -21555

# FIXME: The encode/decode functions are not inverses of each other.
# FIXME: The encode/decode functions are not inverses of each other.

0x18 0x02 0x01 0x4d # CHECK: blezalc $2, 1332
0x18 0x02 0x01 0x4d # CHECK: blezalc $2, 1332

# FIXME: The encode/decode functions are not inverses of each other.
# FIXME: The encode/decode functions are not inverses of each other.

0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, 1332
0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, 1332

0x18 0x43 0x00 0x40 # CHECK: bgeuc $2, $3, 256
0x18 0x43 0x00 0x40 # CHECK: bgeuc $2, $3, 256

▲ Show 20 Lines • Show All 142 Lines • Show Last 20 Lines
test/MC/Mips/mips-alu-instructions.s
Show First 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
# CHECK:  mult   $3, $5          # encoding: [0x18,0x00,0x65,0x00]
# CHECK:  mult   $3, $5          # encoding: [0x18,0x00,0x65,0x00]

# CHECK:  multu  $3, $5          # encoding: [0x19,0x00,0x65,0x00]
# CHECK:  multu  $3, $5          # encoding: [0x19,0x00,0x65,0x00]

# CHECK:  sub    $9, $6, $7      # encoding: [0x22,0x48,0xc7,0x00]
# CHECK:  sub    $9, $6, $7      # encoding: [0x22,0x48,0xc7,0x00]

# CHECK:  addi   $sp, $sp, -56   # encoding: [0xc8,0xff,0xbd,0x23]
# CHECK:  addi   $sp, $sp, -56   # encoding: [0xc8,0xff,0xbd,0x23]

# CHECK:  subu   $4, $3, $5      # encoding: [0x23,0x20,0x65,0x00]
# CHECK:  subu   $4, $3, $5      # encoding: [0x23,0x20,0x65,0x00]

# CHECK:  addiu   $sp, $sp, -40  # encoding: [0xd8,0xff,0xbd,0x27]
# CHECK:  addiu   $sp, $sp, -40  # encoding: [0xd8,0xff,0xbd,0x27]

# CHECK:  neg     $6, $7         # encoding: [0x22,0x30,0x07,0x00]
# CHECK:  neg     $6, $7         # encoding: [0x22,0x30,0x07,0x00]

# CHECK:  negu    $6, $7         # encoding: [0x23,0x30,0x07,0x00]
# CHECK:  negu    $6, $7         # encoding: [0x23,0x30,0x07,0x00]

# CHECK:  move    $7, $8         # encoding: [0x21,0x38,0x00,0x01]
# CHECK:  move    $7, $8         # encoding: [0x25,0x38,0x00,0x01]

# CHECK:  .set    push
# CHECK:  .set    push

# CHECK:  .set    mips32r2
# CHECK:  .set    mips32r2

# CHECK:  rdhwr   $5, $29
# CHECK:  rdhwr   $5, $29

# CHECK:  .set    pop            # encoding: [0x3b,0xe8,0x05,0x7c]
# CHECK:  .set    pop            # encoding: [0x3b,0xe8,0x05,0x7c]

    add    $9,$6,$7
    add    $9,$6,$7

    add    $9,$6,17767
    add    $9,$6,17767

    addu   $9,$6,-15001
    addu   $9,$6,-15001

    addi   $9,$6,17767
    addi   $9,$6,17767

▲ Show 20 Lines • Show All 47 Lines • Show Last 20 Lines
test/MC/Mips/mips1/valid.s
Show First 20 Lines • Show All 58 Lines • ▼ Show 20 Linesa:

        lwl       $s4,-4231($15)
        lwl       $s4,-4231($15)

        lwr       $zero,-19147($gp)
        lwr       $zero,-19147($gp)

        mfc1      $a3,$f27
        mfc1      $a3,$f27

        mfhi      $s3
        mfhi      $s3

        mfhi      $sp
        mfhi      $sp

        mflo      $s1
        mflo      $s1

        mov.d     $f20,$f14
        mov.d     $f20,$f14

        mov.s     $f2,$f27
        mov.s     $f2,$f27

        move      $s8,$a0
        move      $s8,$a0              # CHECK: move $fp, $4           # encoding: [0x00,0x80,0xf0,0x25]

        move      $25,$a2
        move      $25,$a2              # CHECK: move $25, $6           # encoding: [0x00,0xc0,0xc8,0x25]

        mtc1      $s8,$f9
        mtc1      $s8,$f9

        mthi      $s1
        mthi      $s1

        mtlo      $sp
        mtlo      $sp

        mtlo      $25
        mtlo      $25

        mul.d     $f20,$f20,$f16
        mul.d     $f20,$f20,$f16

        mul.s     $f30,$f10,$f2
        mul.s     $f30,$f10,$f2

        mult      $sp,$s4
        mult      $sp,$s4

        mult      $sp,$v0
        mult      $sp,$v0

▲ Show 20 Lines • Show All 50 Lines • Show Last 20 Lines
test/MC/Mips/mips2/valid.s
Show First 20 Lines • Show All 78 Lines • ▼ Show 20 Linesa:

        lwl       $s4,-4231($15)
        lwl       $s4,-4231($15)

        lwr       $zero,-19147($gp)
        lwr       $zero,-19147($gp)

        mfc1      $a3,$f27
        mfc1      $a3,$f27

        mfhi      $s3
        mfhi      $s3

        mfhi      $sp
        mfhi      $sp

        mflo      $s1
        mflo      $s1

        mov.d     $f20,$f14
        mov.d     $f20,$f14

        mov.s     $f2,$f27
        mov.s     $f2,$f27

        move      $s8,$a0
        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]

        move      $25,$a2
        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]

        mtc1      $s8,$f9
        mtc1      $s8,$f9

        mthi      $s1
        mthi      $s1

        mtlo      $sp
        mtlo      $sp

        mtlo      $25
        mtlo      $25

        mul.d     $f20,$f20,$f16
        mul.d     $f20,$f20,$f16

        mul.s     $f30,$f10,$f2
        mul.s     $f30,$f10,$f2

        mult      $sp,$s4
        mult      $sp,$s4

        mult      $sp,$v0
        mult      $sp,$v0

▲ Show 20 Lines • Show All 79 Lines • Show Last 20 Lines
test/MC/Mips/mips3/valid.s
Show First 20 Lines • Show All 136 Lines • ▼ Show 20 Linesa:

        lwr       $zero,-19147($gp)
        lwr       $zero,-19147($gp)

        lwu       $s3,-24086($v1)
        lwu       $s3,-24086($v1)

        mfc1      $a3,$f27
        mfc1      $a3,$f27

        mfhi      $s3
        mfhi      $s3

        mfhi      $sp
        mfhi      $sp

        mflo      $s1
        mflo      $s1

        mov.d     $f20,$f14
        mov.d     $f20,$f14

        mov.s     $f2,$f27
        mov.s     $f2,$f27

        move      $a0,$a3
        move      $a0,$a3              # CHECK: move $4, $7              # encoding: [0x00,0xe0,0x20,0x25]

        move      $s5,$a0
        move      $s5,$a0              # CHECK: move $21, $4             # encoding: [0x00,0x80,0xa8,0x25]

        move      $s8,$a0
        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]

        move      $25,$a2
        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]

        mtc1      $s8,$f9
        mtc1      $s8,$f9

        mthi      $s1
        mthi      $s1

        mtlo      $sp
        mtlo      $sp

        mtlo      $25
        mtlo      $25

        mul.d     $f20,$f20,$f16
        mul.d     $f20,$f20,$f16

        mul.s     $f30,$f10,$f2
        mul.s     $f30,$f10,$f2

        mult      $sp,$s4
        mult      $sp,$s4

        mult      $sp,$v0
        mult      $sp,$v0

▲ Show 20 Lines • Show All 85 Lines • Show Last 20 Lines
test/MC/Mips/mips32/valid.s
Show First 20 Lines • Show All 90 Lines • ▼ Show 20 Linesa:

        maddu     $24,$s2
        maddu     $24,$s2

        mfc0      $8,$15,1             # CHECK: mfc0 $8, $15, 1        # encoding: [0x40,0x08,0x78,0x01]
        mfc0      $8,$15,1             # CHECK: mfc0 $8, $15, 1        # encoding: [0x40,0x08,0x78,0x01]

        mfc1      $a3,$f27
        mfc1      $a3,$f27

        mfhi      $s3
        mfhi      $s3

        mfhi      $sp
        mfhi      $sp

        mflo      $s1
        mflo      $s1

        mov.d     $f20,$f14
        mov.d     $f20,$f14

        mov.s     $f2,$f27
        mov.s     $f2,$f27

        move      $s8,$a0
        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]

        move      $25,$a2
        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]

        movf      $gp,$8,$fcc7
        movf      $gp,$8,$fcc7

        movf.d    $f6,$f11,$fcc5
        movf.d    $f6,$f11,$fcc5

        movf.s    $f23,$f5,$fcc6
        movf.s    $f23,$f5,$fcc6

        movn      $v1,$s1,$s0
        movn      $v1,$s1,$s0

        movn.d    $f27,$f21,$k0
        movn.d    $f27,$f21,$k0

        movn.s    $f12,$f0,$s7
        movn.s    $f12,$f0,$s7

        movt      $zero,$s4,$fcc5
        movt      $zero,$s4,$fcc5

        movt.d    $f0,$f2,$fcc0
        movt.d    $f0,$f2,$fcc0

▲ Show 20 Lines • Show All 97 Lines • Show Last 20 Lines
test/MC/Mips/mips32r2/valid.s
Show First 20 Lines • Show All 105 Lines • ▼ Show 20 Linesa:

        mfc0      $8,$15,1             # CHECK: mfc0 $8, $15, 1      # encoding: [0x40,0x08,0x78,0x01]
        mfc0      $8,$15,1             # CHECK: mfc0 $8, $15, 1      # encoding: [0x40,0x08,0x78,0x01]

        mfc1      $a3,$f27
        mfc1      $a3,$f27

        mfhc1     $s8,$f24
        mfhc1     $s8,$f24

        mfhi      $s3
        mfhi      $s3

        mfhi      $sp
        mfhi      $sp

        mflo      $s1
        mflo      $s1

        mov.d     $f20,$f14
        mov.d     $f20,$f14

        mov.s     $f2,$f27
        mov.s     $f2,$f27

        move      $s8,$a0
        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]

        move      $25,$a2
        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]

        movf      $gp,$8,$fcc7
        movf      $gp,$8,$fcc7

        movf.d    $f6,$f11,$fcc5
        movf.d    $f6,$f11,$fcc5

        movf.s    $f23,$f5,$fcc6
        movf.s    $f23,$f5,$fcc6

        movn      $v1,$s1,$s0
        movn      $v1,$s1,$s0

        movn.d    $f27,$f21,$k0
        movn.d    $f27,$f21,$k0

        movn.s    $f12,$f0,$s7
        movn.s    $f12,$f0,$s7

        movt      $zero,$s4,$fcc5
        movt      $zero,$s4,$fcc5

        movt.d    $f0,$f2,$fcc0
        movt.d    $f0,$f2,$fcc0

▲ Show 20 Lines • Show All 121 Lines • Show Last 20 Lines
test/MC/Mips/mips32r3/valid.s
Show First 20 Lines • Show All 105 Lines • ▼ Show 20 Linesa:

        mfc0      $8,$15,1             # CHECK: mfc0 $8, $15, 1        # encoding: [0x40,0x08,0x78,0x01]
        mfc0      $8,$15,1             # CHECK: mfc0 $8, $15, 1        # encoding: [0x40,0x08,0x78,0x01]

        mfc1      $a3,$f27
        mfc1      $a3,$f27

        mfhc1     $s8,$f24
        mfhc1     $s8,$f24

        mfhi      $s3
        mfhi      $s3

        mfhi      $sp
        mfhi      $sp

        mflo      $s1
        mflo      $s1

        mov.d     $f20,$f14
        mov.d     $f20,$f14

        mov.s     $f2,$f27
        mov.s     $f2,$f27

        move      $s8,$a0
        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]

        move      $25,$a2
        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]

        movf      $gp,$8,$fcc7
        movf      $gp,$8,$fcc7

        movf.d    $f6,$f11,$fcc5
        movf.d    $f6,$f11,$fcc5

        movf.s    $f23,$f5,$fcc6
        movf.s    $f23,$f5,$fcc6

        movn      $v1,$s1,$s0
        movn      $v1,$s1,$s0

        movn.d    $f27,$f21,$k0
        movn.d    $f27,$f21,$k0

        movn.s    $f12,$f0,$s7
        movn.s    $f12,$f0,$s7

        movt      $zero,$s4,$fcc5
        movt      $zero,$s4,$fcc5

        movt.d    $f0,$f2,$fcc0
        movt.d    $f0,$f2,$fcc0

▲ Show 20 Lines • Show All 121 Lines • Show Last 20 Lines
test/MC/Mips/mips32r5/valid.s
Show First 20 Lines • Show All 106 Lines • ▼ Show 20 Linesa:

        mfc0      $8,$15,1             # CHECK: mfc0 $8, $15, 1        # encoding: [0x40,0x08,0x78,0x01]
        mfc0      $8,$15,1             # CHECK: mfc0 $8, $15, 1        # encoding: [0x40,0x08,0x78,0x01]

        mfc1      $a3,$f27
        mfc1      $a3,$f27

        mfhc1     $s8,$f24
        mfhc1     $s8,$f24

        mfhi      $s3
        mfhi      $s3

        mfhi      $sp
        mfhi      $sp

        mflo      $s1
        mflo      $s1

        mov.d     $f20,$f14
        mov.d     $f20,$f14

        mov.s     $f2,$f27
        mov.s     $f2,$f27

        move      $s8,$a0
        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]

        move      $25,$a2
        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]

        movf      $gp,$8,$fcc7
        movf      $gp,$8,$fcc7

        movf.d    $f6,$f11,$fcc5
        movf.d    $f6,$f11,$fcc5

        movf.s    $f23,$f5,$fcc6
        movf.s    $f23,$f5,$fcc6

        movn      $v1,$s1,$s0
        movn      $v1,$s1,$s0

        movn.d    $f27,$f21,$k0
        movn.d    $f27,$f21,$k0

        movn.s    $f12,$f0,$s7
        movn.s    $f12,$f0,$s7

        movt      $zero,$s4,$fcc5
        movt      $zero,$s4,$fcc5

        movt.d    $f0,$f2,$fcc0
        movt.d    $f0,$f2,$fcc0

▲ Show 20 Lines • Show All 121 Lines • Show Last 20 Lines
test/MC/Mips/mips32r6/valid.s
Show First 20 Lines • Show All 107 Lines • ▼ Show 20 Linesa:

        jialc   $5, 256          # CHECK: jialc $5, 256    # encoding: [0xf8,0x05,0x01,0x00]
        jialc   $5, 256          # CHECK: jialc $5, 256    # encoding: [0xf8,0x05,0x01,0x00]

        jic     $5, 256          # CHECK: jic $5, 256      # encoding: [0xd8,0x05,0x01,0x00]
        jic     $5, 256          # CHECK: jic $5, 256      # encoding: [0xd8,0x05,0x01,0x00]

        lsa     $2, $3, $4, 3    # CHECK: lsa  $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0xc5]
        lsa     $2, $3, $4, 3    # CHECK: lsa  $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0xc5]

        lwpc    $2,268           # CHECK: lwpc $2, 268     # encoding: [0xec,0x48,0x00,0x43]
        lwpc    $2,268           # CHECK: lwpc $2, 268     # encoding: [0xec,0x48,0x00,0x43]

        lwupc   $2,268           # CHECK: lwupc $2, 268    # encoding: [0xec,0x50,0x00,0x43]
        lwupc   $2,268           # CHECK: lwupc $2, 268    # encoding: [0xec,0x50,0x00,0x43]

        mfc0    $8,$15,1         # CHECK: mfc0 $8, $15, 1  # encoding: [0x40,0x08,0x78,0x01]
        mfc0    $8,$15,1         # CHECK: mfc0 $8, $15, 1  # encoding: [0x40,0x08,0x78,0x01]

        mod     $2,$3,$4         # CHECK: mod $2, $3, $4   # encoding: [0x00,0x64,0x10,0xda]
        mod     $2,$3,$4         # CHECK: mod $2, $3, $4   # encoding: [0x00,0x64,0x10,0xda]

        modu    $2,$3,$4         # CHECK: modu $2, $3, $4  # encoding: [0x00,0x64,0x10,0xdb]
        modu    $2,$3,$4         # CHECK: modu $2, $3, $4  # encoding: [0x00,0x64,0x10,0xdb]

        move    $a0,$a3          # CHECK: move $4, $7        # encoding: [0x00,0xe0,0x20,0x25]

        move    $s5,$a0          # CHECK: move $21, $4      # encoding: [0x00,0x80,0xa8,0x25]

        move    $s8,$a0          # CHECK: move $fp, $4      # encoding: [0x00,0x80,0xf0,0x25]

        move    $25,$a2          # CHECK: move $25, $6      # encoding: [0x00,0xc0,0xc8,0x25]

        mtc0    $9,$15,1         # CHECK: mtc0 $9, $15, 1  # encoding: [0x40,0x89,0x78,0x01]
        mtc0    $9,$15,1         # CHECK: mtc0 $9, $15, 1  # encoding: [0x40,0x89,0x78,0x01]

        mul     $2,$3,$4         # CHECK: mul $2, $3, $4   # encoding: [0x00,0x64,0x10,0x98]
        mul     $2,$3,$4         # CHECK: mul $2, $3, $4   # encoding: [0x00,0x64,0x10,0x98]

        muh     $2,$3,$4         # CHECK: muh $2, $3, $4   # encoding: [0x00,0x64,0x10,0xd8]
        muh     $2,$3,$4         # CHECK: muh $2, $3, $4   # encoding: [0x00,0x64,0x10,0xd8]

        mulu    $2,$3,$4         # CHECK: mulu $2, $3, $4  # encoding: [0x00,0x64,0x10,0x99]
        mulu    $2,$3,$4         # CHECK: mulu $2, $3, $4  # encoding: [0x00,0x64,0x10,0x99]

        muhu    $2,$3,$4         # CHECK: muhu $2, $3, $4  # encoding: [0x00,0x64,0x10,0xd9]
        muhu    $2,$3,$4         # CHECK: muhu $2, $3, $4  # encoding: [0x00,0x64,0x10,0xd9]

        maddf.s $f2,$f3,$f4      # CHECK: maddf.s $f2, $f3, $f4  # encoding: [0x46,0x04,0x18,0x98]
        maddf.s $f2,$f3,$f4      # CHECK: maddf.s $f2, $f3, $f4  # encoding: [0x46,0x04,0x18,0x98]

        maddf.d $f2,$f3,$f4      # CHECK: maddf.d $f2, $f3, $f4  # encoding: [0x46,0x24,0x18,0x98]
        maddf.d $f2,$f3,$f4      # CHECK: maddf.d $f2, $f3, $f4  # encoding: [0x46,0x24,0x18,0x98]

        msubf.s $f2,$f3,$f4      # CHECK: msubf.s $f2, $f3, $f4  # encoding: [0x46,0x04,0x18,0x99]
        msubf.s $f2,$f3,$f4      # CHECK: msubf.s $f2, $f3, $f4  # encoding: [0x46,0x04,0x18,0x99]

▲ Show 20 Lines • Show All 66 Lines • Show Last 20 Lines
test/MC/Mips/mips4/valid.s
Show First 20 Lines • Show All 144 Lines • ▼ Show 20 Linesa:

        madd.d    $f18, $f22, $f26, $f20  # encoding: [0x4e,0xd4,0xd4,0xa1]
        madd.d    $f18, $f22, $f26, $f20  # encoding: [0x4e,0xd4,0xd4,0xa1]

        madd.s    $f2, $f30, $f18, $f24   # encoding: [0x4f,0xd8,0x90,0xa0]        
        madd.s    $f2, $f30, $f18, $f24   # encoding: [0x4f,0xd8,0x90,0xa0]        

        mfc1      $a3,$f27
        mfc1      $a3,$f27

        mfhi      $s3
        mfhi      $s3

        mfhi      $sp
        mfhi      $sp

        mflo      $s1
        mflo      $s1

        mov.d     $f20,$f14
        mov.d     $f20,$f14

        mov.s     $f2,$f27
        mov.s     $f2,$f27

        move      $a0,$a3
        move      $a0,$a3              # CHECK: move $4, $7              # encoding: [0x00,0xe0,0x20,0x25]

        move      $s5,$a0
        move      $s5,$a0              # CHECK: move $21, $4             # encoding: [0x00,0x80,0xa8,0x25]

        move      $s8,$a0
        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]

        move      $25,$a2
        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]

        movf      $gp,$8,$fcc7
        movf      $gp,$8,$fcc7

        movf.d    $f6,$f11,$fcc5
        movf.d    $f6,$f11,$fcc5

        movf.s    $f23,$f5,$fcc6
        movf.s    $f23,$f5,$fcc6

        movn      $v1,$s1,$s0
        movn      $v1,$s1,$s0

        movn.d    $f27,$f21,$k0
        movn.d    $f27,$f21,$k0

        movn.s    $f12,$f0,$s7
        movn.s    $f12,$f0,$s7

        movt      $zero,$s4,$fcc5
        movt      $zero,$s4,$fcc5

        movt.d    $f0,$f2,$fcc0
        movt.d    $f0,$f2,$fcc0

▲ Show 20 Lines • Show All 106 Lines • Show Last 20 Lines
test/MC/Mips/mips5/valid.s
Show First 20 Lines • Show All 145 Lines • ▼ Show 20 Linesa:

        madd.d    $f18, $f22, $f26, $f20  # encoding: [0x4e,0xd4,0xd4,0xa1]
        madd.d    $f18, $f22, $f26, $f20  # encoding: [0x4e,0xd4,0xd4,0xa1]

        madd.s    $f2, $f30, $f18, $f24   # encoding: [0x4f,0xd8,0x90,0xa0]
        madd.s    $f2, $f30, $f18, $f24   # encoding: [0x4f,0xd8,0x90,0xa0]

        mfc1      $a3,$f27
        mfc1      $a3,$f27

        mfhi      $s3
        mfhi      $s3

        mfhi      $sp
        mfhi      $sp

        mflo      $s1
        mflo      $s1

        mov.d     $f20,$f14
        mov.d     $f20,$f14

        mov.s     $f2,$f27
        mov.s     $f2,$f27

        move      $a0,$a3
        move      $a0,$a3              # CHECK: move $4, $7              # encoding: [0x00,0xe0,0x20,0x25]

        move      $s5,$a0
        move      $s5,$a0              # CHECK: move $21, $4             # encoding: [0x00,0x80,0xa8,0x25]

        move      $s8,$a0
        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]

        move      $25,$a2
        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]

        movf      $gp,$8,$fcc7
        movf      $gp,$8,$fcc7

        movf.d    $f6,$f11,$fcc5
        movf.d    $f6,$f11,$fcc5

        movf.s    $f23,$f5,$fcc6
        movf.s    $f23,$f5,$fcc6

        movn      $v1,$s1,$s0
        movn      $v1,$s1,$s0

        movn.d    $f27,$f21,$k0
        movn.d    $f27,$f21,$k0

        movn.s    $f12,$f0,$s7
        movn.s    $f12,$f0,$s7

        movt      $zero,$s4,$fcc5
        movt      $zero,$s4,$fcc5

        movt.d    $f0,$f2,$fcc0
        movt.d    $f0,$f2,$fcc0

▲ Show 20 Lines • Show All 107 Lines • Show Last 20 Lines
test/MC/Mips/mips64-alu-instructions.s
Show First 20 Lines • Show All 78 Lines • ▼ Show 20 Lines
# CHECK:  maddu  $6, $7          # encoding: [0x01,0x00,0xc7,0x70]
# CHECK:  maddu  $6, $7          # encoding: [0x01,0x00,0xc7,0x70]

# CHECK:  msub   $6, $7          # encoding: [0x04,0x00,0xc7,0x70]
# CHECK:  msub   $6, $7          # encoding: [0x04,0x00,0xc7,0x70]

# CHECK:  msubu  $6, $7          # encoding: [0x05,0x00,0xc7,0x70]
# CHECK:  msubu  $6, $7          # encoding: [0x05,0x00,0xc7,0x70]

# CHECK:  mult   $3, $5          # encoding: [0x18,0x00,0x65,0x00]
# CHECK:  mult   $3, $5          # encoding: [0x18,0x00,0x65,0x00]

# CHECK:  multu  $3, $5          # encoding: [0x19,0x00,0x65,0x00]
# CHECK:  multu  $3, $5          # encoding: [0x19,0x00,0x65,0x00]

# CHECK:  dsub    $9, $6, $7     # encoding: [0x2e,0x48,0xc7,0x00]
# CHECK:  dsub    $9, $6, $7     # encoding: [0x2e,0x48,0xc7,0x00]

# CHECK:  dsubu   $4, $3, $5     # encoding: [0x2f,0x20,0x65,0x00]
# CHECK:  dsubu   $4, $3, $5     # encoding: [0x2f,0x20,0x65,0x00]

# CHECK:  daddiu  $9, $6, -17767 # encoding: [0x99,0xba,0xc9,0x64]
# CHECK:  daddiu  $9, $6, -17767 # encoding: [0x99,0xba,0xc9,0x64]

# CHECK:  move    $7, $8         # encoding: [0x2d,0x38,0x00,0x01]
# CHECK:  move    $7, $8         # encoding: [0x25,0x38,0x00,0x01]

# CHECK:  .set    push
# CHECK:  .set    push

# CHECK:  .set    mips32r2
# CHECK:  .set    mips32r2

# CHECK:  rdhwr   $5, $29
# CHECK:  rdhwr   $5, $29

# CHECK:  .set    pop            # encoding: [0x3b,0xe8,0x05,0x7c]
# CHECK:  .set    pop            # encoding: [0x3b,0xe8,0x05,0x7c]




    dadd    $9,$6,$7
    dadd    $9,$6,$7

    dadd    $9,$6,17767
    dadd    $9,$6,17767

    daddu   $9,$6,-15001
    daddu   $9,$6,-15001

▲ Show 20 Lines • Show All 57 Lines • Show Last 20 Lines
test/MC/Mips/mips64/valid.s
Show First 20 Lines • Show All 157 Lines • ▼ Show 20 Linesa:

        madd.s    $f2, $f30, $f18, $f24   # encoding: [0x4f,0xd8,0x90,0xa0]
        madd.s    $f2, $f30, $f18, $f24   # encoding: [0x4f,0xd8,0x90,0xa0]

        mfc0      $8,$15,1             # CHECK: mfc0 $8, $15, 1        # encoding: [0x40,0x08,0x78,0x01]
        mfc0      $8,$15,1             # CHECK: mfc0 $8, $15, 1        # encoding: [0x40,0x08,0x78,0x01]

        mfc1      $a3,$f27
        mfc1      $a3,$f27

        mfhi      $s3
        mfhi      $s3

        mfhi      $sp
        mfhi      $sp

        mflo      $s1
        mflo      $s1

        mov.d     $f20,$f14
        mov.d     $f20,$f14

        mov.s     $f2,$f27
        mov.s     $f2,$f27

        move      $a0,$a3
        move      $a0,$a3              # CHECK: move $4, $7               # encoding: [0x00,0xe0,0x20,0x25]

        move      $s5,$a0
        move      $s5,$a0              # CHECK: move $21, $4             # encoding: [0x00,0x80,0xa8,0x25]

        move      $s8,$a0
        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]

        move      $25,$a2
        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]

        movf      $gp,$8,$fcc7
        movf      $gp,$8,$fcc7

        movf.d    $f6,$f11,$fcc5
        movf.d    $f6,$f11,$fcc5

        movf.s    $f23,$f5,$fcc6
        movf.s    $f23,$f5,$fcc6

        movn      $v1,$s1,$s0
        movn      $v1,$s1,$s0

        movn.d    $f27,$f21,$k0
        movn.d    $f27,$f21,$k0

        movn.s    $f12,$f0,$s7
        movn.s    $f12,$f0,$s7

        movt      $zero,$s4,$fcc5
        movt      $zero,$s4,$fcc5

        movt.d    $f0,$f2,$fcc0
        movt.d    $f0,$f2,$fcc0

▲ Show 20 Lines • Show All 114 Lines • Show Last 20 Lines
test/MC/Mips/mips64r2/valid.s
Show First 20 Lines • Show All 173 Lines • ▼ Show 20 Linesa:

        mfc0      $8,$15,1             # CHECK: mfc0 $8, $15, 1        # encoding: [0x40,0x08,0x78,0x01]
        mfc0      $8,$15,1             # CHECK: mfc0 $8, $15, 1        # encoding: [0x40,0x08,0x78,0x01]

        mfc1      $a3,$f27
        mfc1      $a3,$f27

        mfhc1     $s8,$f24
        mfhc1     $s8,$f24

        mfhi      $s3
        mfhi      $s3

        mfhi      $sp
        mfhi      $sp

        mflo      $s1
        mflo      $s1

        mov.d     $f20,$f14
        mov.d     $f20,$f14

        mov.s     $f2,$f27
        mov.s     $f2,$f27

        move      $a0,$a3
        move      $a0,$a3              # CHECK: move $4, $7               # encoding: [0x00,0xe0,0x20,0x25]

        move      $s5,$a0
        move      $s5,$a0              # CHECK: move $21, $4             # encoding: [0x00,0x80,0xa8,0x25]

        move      $s8,$a0
        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]

        move      $25,$a2
        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]

        movf      $gp,$8,$fcc7
        movf      $gp,$8,$fcc7

        movf.d    $f6,$f11,$fcc5
        movf.d    $f6,$f11,$fcc5

        movf.s    $f23,$f5,$fcc6
        movf.s    $f23,$f5,$fcc6

        movn      $v1,$s1,$s0
        movn      $v1,$s1,$s0

        movn.d    $f27,$f21,$k0
        movn.d    $f27,$f21,$k0

        movn.s    $f12,$f0,$s7
        movn.s    $f12,$f0,$s7

        movt      $zero,$s4,$fcc5
        movt      $zero,$s4,$fcc5

        movt.d    $f0,$f2,$fcc0
        movt.d    $f0,$f2,$fcc0

▲ Show 20 Lines • Show All 125 Lines • Show Last 20 Lines
test/MC/Mips/mips64r3/valid.s
Show First 20 Lines • Show All 173 Lines • ▼ Show 20 Linesa:

        mfc0      $8,$15,1             # CHECK: mfc0 $8, $15, 1        # encoding: [0x40,0x08,0x78,0x01]
        mfc0      $8,$15,1             # CHECK: mfc0 $8, $15, 1        # encoding: [0x40,0x08,0x78,0x01]

        mfc1      $a3,$f27
        mfc1      $a3,$f27

        mfhc1     $s8,$f24
        mfhc1     $s8,$f24

        mfhi      $s3
        mfhi      $s3

        mfhi      $sp
        mfhi      $sp

        mflo      $s1
        mflo      $s1

        mov.d     $f20,$f14
        mov.d     $f20,$f14

        mov.s     $f2,$f27
        mov.s     $f2,$f27

        move      $a0,$a3
        move      $a0,$a3              # CHECK: move $4, $7               # encoding: [0x00,0xe0,0x20,0x25]

        move      $s5,$a0
        move      $s5,$a0              # CHECK: move $21, $4             # encoding: [0x00,0x80,0xa8,0x25]

        move      $s8,$a0
        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]

        move      $25,$a2
        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]

        movf      $gp,$8,$fcc7
        movf      $gp,$8,$fcc7

        movf.d    $f6,$f11,$fcc5
        movf.d    $f6,$f11,$fcc5

        movf.s    $f23,$f5,$fcc6
        movf.s    $f23,$f5,$fcc6

        movn      $v1,$s1,$s0
        movn      $v1,$s1,$s0

        movn.d    $f27,$f21,$k0
        movn.d    $f27,$f21,$k0

        movn.s    $f12,$f0,$s7
        movn.s    $f12,$f0,$s7

        movt      $zero,$s4,$fcc5
        movt      $zero,$s4,$fcc5

        movt.d    $f0,$f2,$fcc0
        movt.d    $f0,$f2,$fcc0

▲ Show 20 Lines • Show All 125 Lines • Show Last 20 Lines
test/MC/Mips/mips64r5/valid.s
Show First 20 Lines • Show All 174 Lines • ▼ Show 20 Linesa:

        mfc0      $8,$15,1             # CHECK: mfc0 $8, $15, 1        # encoding: [0x40,0x08,0x78,0x01]
        mfc0      $8,$15,1             # CHECK: mfc0 $8, $15, 1        # encoding: [0x40,0x08,0x78,0x01]

        mfc1      $a3,$f27
        mfc1      $a3,$f27

        mfhc1     $s8,$f24
        mfhc1     $s8,$f24

        mfhi      $s3
        mfhi      $s3

        mfhi      $sp
        mfhi      $sp

        mflo      $s1
        mflo      $s1

        mov.d     $f20,$f14
        mov.d     $f20,$f14

        mov.s     $f2,$f27
        mov.s     $f2,$f27

        move      $a0,$a3
        move      $a0,$a3              # CHECK: move $4, $7               # encoding: [0x00,0xe0,0x20,0x25]

        move      $s5,$a0
        move      $s5,$a0              # CHECK: move $21, $4             # encoding: [0x00,0x80,0xa8,0x25]

        move      $s8,$a0
        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]

        move      $25,$a2
        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]

        movf      $gp,$8,$fcc7
        movf      $gp,$8,$fcc7

        movf.d    $f6,$f11,$fcc5
        movf.d    $f6,$f11,$fcc5

        movf.s    $f23,$f5,$fcc6
        movf.s    $f23,$f5,$fcc6

        movn      $v1,$s1,$s0
        movn      $v1,$s1,$s0

        movn.d    $f27,$f21,$k0
        movn.d    $f27,$f21,$k0

        movn.s    $f12,$f0,$s7
        movn.s    $f12,$f0,$s7

        movt      $zero,$s4,$fcc5
        movt      $zero,$s4,$fcc5

        movt.d    $f0,$f2,$fcc0
        movt.d    $f0,$f2,$fcc0

▲ Show 20 Lines • Show All 125 Lines • Show Last 20 Lines
test/MC/Mips/mips64r6/valid.s
Show First 20 Lines • Show All 158 Lines • ▼ Show 20 Linesa:

        maxa.s  $f0, $f2, $f4    # CHECK: maxa.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1f]
        maxa.s  $f0, $f2, $f4    # CHECK: maxa.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1f]

        min.d   $f0, $f2, $f4    # CHECK: min.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1c]
        min.d   $f0, $f2, $f4    # CHECK: min.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1c]

        min.s   $f0, $f2, $f4    # CHECK: min.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1c]
        min.s   $f0, $f2, $f4    # CHECK: min.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1c]

        mina.d  $f0, $f2, $f4    # CHECK: mina.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1e]
        mina.d  $f0, $f2, $f4    # CHECK: mina.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1e]

        mina.s  $f0, $f2, $f4    # CHECK: mina.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1e]
        mina.s  $f0, $f2, $f4    # CHECK: mina.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1e]

        mfc0    $8,$15,1         # CHECK: mfc0 $8, $15, 1      # encoding: [0x40,0x08,0x78,0x01]
        mfc0    $8,$15,1         # CHECK: mfc0 $8, $15, 1      # encoding: [0x40,0x08,0x78,0x01]

        mod     $2,$3,$4         # CHECK: mod $2, $3, $4   # encoding: [0x00,0x64,0x10,0xda]
        mod     $2,$3,$4         # CHECK: mod $2, $3, $4   # encoding: [0x00,0x64,0x10,0xda]

        modu    $2,$3,$4         # CHECK: modu $2, $3, $4  # encoding: [0x00,0x64,0x10,0xdb]
        modu    $2,$3,$4         # CHECK: modu $2, $3, $4  # encoding: [0x00,0x64,0x10,0xdb]

        move    $a0,$a3          # CHECK: move $4, $7              # encoding: [0x00,0xe0,0x20,0x25]

        move    $s5,$a0          # CHECK: move $21, $4            # encoding: [0x00,0x80,0xa8,0x25]

        move    $s8,$a0          # CHECK: move $fp, $4            # encoding: [0x00,0x80,0xf0,0x25]

        move    $25,$a2          # CHECK: move $25, $6            # encoding: [0x00,0xc0,0xc8,0x25]

        mtc0    $9,$15,1         # CHECK: mtc0 $9, $15, 1        # encoding: [0x40,0x89,0x78,0x01]
        mtc0    $9,$15,1         # CHECK: mtc0 $9, $15, 1        # encoding: [0x40,0x89,0x78,0x01]

        msubf.d $f2,$f3,$f4      # CHECK: msubf.d $f2, $f3, $f4  # encoding: [0x46,0x24,0x18,0x99]
        msubf.d $f2,$f3,$f4      # CHECK: msubf.d $f2, $f3, $f4  # encoding: [0x46,0x24,0x18,0x99]

        msubf.s $f2,$f3,$f4      # CHECK: msubf.s $f2, $f3, $f4  # encoding: [0x46,0x04,0x18,0x99]
        msubf.s $f2,$f3,$f4      # CHECK: msubf.s $f2, $f3, $f4  # encoding: [0x46,0x04,0x18,0x99]

        muh     $2,$3,$4         # CHECK: muh $2, $3, $4   # encoding: [0x00,0x64,0x10,0xd8]
        muh     $2,$3,$4         # CHECK: muh $2, $3, $4   # encoding: [0x00,0x64,0x10,0xd8]

        muhu    $2,$3,$4         # CHECK: muhu $2, $3, $4  # encoding: [0x00,0x64,0x10,0xd9]
        muhu    $2,$3,$4         # CHECK: muhu $2, $3, $4  # encoding: [0x00,0x64,0x10,0xd9]

        mul     $2,$3,$4         # CHECK: mul $2, $3, $4   # encoding: [0x00,0x64,0x10,0x98]
        mul     $2,$3,$4         # CHECK: mul $2, $3, $4   # encoding: [0x00,0x64,0x10,0x98]

        mulu    $2,$3,$4         # CHECK: mulu $2, $3, $4  # encoding: [0x00,0x64,0x10,0x99]
        mulu    $2,$3,$4         # CHECK: mulu $2, $3, $4  # encoding: [0x00,0x64,0x10,0x99]

        or      $2, 4            # CHECK: ori $2, $2, 4          # encoding: [0x34,0x42,0x00,0x04]
        or      $2, 4            # CHECK: ori $2, $2, 4          # encoding: [0x34,0x42,0x00,0x04]

▲ Show 20 Lines • Show All 42 Lines • Show Last 20 Lines