WebAssembly: implement getScalarShiftAmountTy so we can shift by amount, with type

[jfb]

Summary

This currently sets the shift amount RHS to the same type as the LHS, and assumes that the LHS is a simple type. This isn't currently the case e.g. with weird integers sizes, but will eventually be true and will assert if not. That's what you get for having an experimental backend: break it and you get to keep both pieces. Most backends either set the RHS to MVT::i32 or MVT::i64, but WebAssembly is a virtual ISA and tries to have regular-looking binary operations where both operands are the same type (even if a 64-bit RHS shifter is slightly silly, hey it's free!).

lib/Target/WebAssembly/WebAssemblyISelLowering.h

public:
   WebAssemblyTargetLowering(const TargetMachine &TM,
                             const WebAssemblySubtarget &STI);
 
 private:
   /// Keep a pointer to the WebAssemblySubtarget around so that we can make the
   /// right decision when generating code for different targets.
   const WebAssemblySubtarget *Subtarget;
 
+  MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override;
+
   bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
                       bool isVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,
                       LLVMContext &Context) const override;
 
   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,
                       const SmallVectorImpl<SDValue> &OutVals, SDLoc dl,

lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

WebAssemblyTargetLowering::WebAssemblyTargetLowering(
   addRegisterClass(MVT::f32, &WebAssembly::Float32RegClass);
   addRegisterClass(MVT::f64, &WebAssembly::Float64RegClass);
   // Compute derived properties from the register classes.
   computeRegisterProperties(Subtarget->getRegisterInfo());
 
   // FIXME: setOperationAction...
 }
 
+MVT WebAssemblyTargetLowering::getScalarShiftAmountTy(const DataLayout &DL,
+                                                      EVT VT) const {
+  return VT.getSimpleVT();
+}
+
 //===----------------------------------------------------------------------===//
 // WebAssembly Lowering private implementation.
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // Lowering Code
 //===----------------------------------------------------------------------===//
 

test/CodeGen/WebAssembly/integer64.ll

 ; CHECK-NEXT: (setlocal @1 (argument 0))
 ; CHECK-NEXT: (setlocal @2 (XOR_I64 @1 @0))
 ; CHECK-NEXT: (return @2)
 define i64 @xor64(i64 %x, i64 %y) {
   %a = xor i64 %x, %y
   ret i64 %a
 }
 
-; FIXME: 64-bit shifts have an extra truncate of the input shift value, which
-;        WebAssembly hasn't taught isel to match yet. Fix with
-;        getScalarShiftAmountTy.
-
-; C;HECK-LABEL: shl64:
-; C;HECK-NEXT: (setlocal @0 (argument 1))
-; C;HECK-NEXT: (setlocal @1 (argument 0))
-; C;HECK-NEXT: (setlocal @2 (SHL_I64 @1 @0))
-; C;HECK-NEXT: (return @2)
-;define i64 @shl64(i64 %x, i64 %y) {
-;  %a = shl i64 %x, %y
-;  ret i64 %a
-;}
-
-; C;HECK-LABEL: shr64:
-; C;HECK-NEXT: (setlocal @0 (argument 1))
-; C;HECK-NEXT: (setlocal @1 (argument 0))
-; C;HECK-NEXT: (setlocal @2 (SHR_I64 @1 @0))
-; C;HECK-NEXT: (return @2)
-;define i64 @shr64(i64 %x, i64 %y) {
-;  %a = lshr i64 %x, %y
-;  ret i64 %a
-;}
-
-; C;HECK-LABEL: sar64:
-; C;HECK-NEXT: (setlocal @0 (argument 1))
-; C;HECK-NEXT: (setlocal @1 (argument 0))
-; C;HECK-NEXT: (setlocal @2 (SAR_I64 @1 @0))
-; C;HECK-NEXT: (return @2)
-;define i64 @sar64(i64 %x, i64 %y) {
-;  %a = ashr i64 %x, %y
-;  ret i64 %a
-;}
+; CHECK-LABEL: shl64:
+; CHECK-NEXT: (setlocal @0 (argument 1))
+; CHECK-NEXT: (setlocal @1 (argument 0))
+; CHECK-NEXT: (setlocal @2 (SHL_I64 @1 @0))
+; CHECK-NEXT: (return @2)
+define i64 @shl64(i64 %x, i64 %y) {
+  %a = shl i64 %x, %y
+  ret i64 %a
+}
+
+; CHECK-LABEL: shr64:
+; CHECK-NEXT: (setlocal @0 (argument 1))
+; CHECK-NEXT: (setlocal @1 (argument 0))
+; CHECK-NEXT: (setlocal @2 (SHR_I64 @1 @0))
+; CHECK-NEXT: (return @2)
+define i64 @shr64(i64 %x, i64 %y) {
+  %a = lshr i64 %x, %y
+  ret i64 %a
+}
+
+; CHECK-LABEL: sar64:
+; CHECK-NEXT: (setlocal @0 (argument 1))
+; CHECK-NEXT: (setlocal @1 (argument 0))
+; CHECK-NEXT: (setlocal @2 (SAR_I64 @1 @0))
+; CHECK-NEXT: (return @2)
+define i64 @sar64(i64 %x, i64 %y) {
+  %a = ashr i64 %x, %y
+  ret i64 %a
+}
 
 ; CHECK-LABEL: clz64:
 ; CHECK-NEXT: (setlocal @0 (argument 0))
 ; CHECK-NEXT: (setlocal @1 (CLZ_I64 @0))
 ; CHECK-NEXT: (return @1)
 define i64 @clz64(i64 %x) {
   %a = call i64 @llvm.ctlz.i64(i64 %x, i1 false)
   ret i64 %a