[MCA] Remove the warning about experimental support for in-order CPU

[asavonic]

Summary

There are not a lot of bug reports for this feature, so let's mark it
as stable.

[andreadb]

LGTM

llvm/test/tools/llvm-mca/X86/in-order-cpu.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=atom -o /dev/null 2>&1 | FileCheck %s
+# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=atom | FileCheck %s
 movsbw  %al, %di
 
-# CHECK:      warning: support for in-order CPU 'atom' is experimental.
+# CHECK:      Iterations:        100
+# CHECK-NEXT: Instructions:      100
+# CHECK-NEXT: Total Cycles:      101
+# CHECK-NEXT: Total uOps:        100
+
+# CHECK:      Dispatch Width:    2
+# CHECK-NEXT: uOps Per Cycle:    0.99
+# CHECK-NEXT: IPC:               0.99
+# CHECK-NEXT: Block RThroughput: 1.0
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      2     1.00                        movsbw  %al, %di
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - AtomPort0
+# CHECK-NEXT: [1]   - AtomPort1
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]
+# CHECK-NEXT: 1.00   1.00
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    Instructions:
+# CHECK-NEXT: 1.00   1.00   movsbw  %al, %di

llvm/tools/llvm-mca/llvm-mca.cpp

if (MCPU == "native")
     MCPU = std::string(llvm::sys::getHostCPUName());
 
   std::unique_ptr<MCSubtargetInfo> STI(
       TheTarget->createMCSubtargetInfo(TripleName, MCPU, MATTR));
   assert(STI && "Unable to create subtarget info!");
   if (!STI->isCPUStringValid(MCPU))
     return 1;
 
-  bool IsOutOfOrder = STI->getSchedModel().isOutOfOrder();
-  if (!PrintInstructionTables && !IsOutOfOrder) {
-    WithColor::warning() << "support for in-order CPU '" << MCPU
-                         << "' is experimental.\n";
-  }
-
   if (!STI->getSchedModel().hasInstrSchedModel()) {
     WithColor::error()
         << "unable to find instruction-level scheduling information for"
         << " target triple '" << TheTriple.normalize() << "' and cpu '" << MCPU
         << "'.\n";
 
     if (STI->getSchedModel().InstrItineraries)
       WithColor::note()
           << "cpu '" << MCPU << "' provides itineraries. However, "
           << "instruction itineraries are currently unsupported.\n";
     return 1;
   }
 
   // Apply overrides to llvm-mca specific options.
+  bool IsOutOfOrder = STI->getSchedModel().isOutOfOrder();
   processViewOptions(IsOutOfOrder);
 
   std::unique_ptr<MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName));
   assert(MRI && "Unable to create target register info!");
 
   MCTargetOptions MCOptions = mc::InitMCTargetOptionsFromFlags();
   std::unique_ptr<MCAsmInfo> MAI(
       TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions));