AMDPGU/SI: Negative offsets aren't allowed in MUBUF's vaddr operand

[arsenm]

LGTM

test/CodeGen/AMDGPU/scratch-buffer.ll

101–102

I still don't really understand how this becomes a negative offset. Would another test that adds a negative offset be useful?

[• tstellarAMD]

test/CodeGen/AMDGPU/scratch-buffer.ll

101–102

Negative immediate offsets don't trigger the bug, because only unsigned immediates get folded into the MUBUF instruction. The bug occurs when %offset is negative and it is passed to the vaddr operand.

lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

bool AMDGPUDAGToDAGISel::SelectMUBUFScratch(SDValue Addr, SDValue &Rsrc,
   SDValue ScratchPtr = SDValue(CurDAG->getMachineNode(AMDGPU::REG_SEQUENCE, DL,
                                               MVT::v2i32, RsrcOps), 0);
   Rsrc = SDValue(Lowering.buildScratchRSRC(*CurDAG, DL, ScratchPtr), 0);
   SOffset = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
       MRI.getLiveInVirtReg(ScratchOffsetReg), MVT::i32);
 
   // (add n0, c1)
   if (CurDAG->isBaseWithConstantOffset(Addr)) {
+    SDValue N0 = Addr.getOperand(0);
     SDValue N1 = Addr.getOperand(1);
+    // Offsets in vaddr must be positive.
+    if (CurDAG->SignBitIsZero(N0)) {
       ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
-
       if (isLegalMUBUFImmOffset(C1)) {
-      VAddr = Addr.getOperand(0);
+        VAddr = N0;
         ImmOffset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16);
         return true;
       }
     }
+  }
 
   // (node)
   VAddr = Addr;
   ImmOffset = CurDAG->getTargetConstant(0, DL, MVT::i16);
   return true;
 }
 
 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,

test/CodeGen/AMDGPU/private-memory.ll

 }
 
 ; AMDGPUPromoteAlloca does not know how to handle ptrtoint.  When it
 ; finds one, it should stop trying to promote.
 
 ; FUNC-LABEL: ptrtoint:
 ; SI-NOT: ds_write
 ; SI: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen
-; SI: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen offset:5
+; SI: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen ;
 define void @ptrtoint(i32 addrspace(1)* %out, i32 %a, i32 %b) {
   %alloca = alloca [16 x i32]
   %tmp0 = getelementptr [16 x i32], [16 x i32]* %alloca, i32 0, i32 %a
   store i32 5, i32* %tmp0
   %tmp1 = ptrtoint [16 x i32]* %alloca to i32
   %tmp2 = add i32 %tmp1, 5
   %tmp3 = inttoptr i32 %tmp2 to i32*
   %tmp4 = getelementptr i32, i32* %tmp3, i32 %b
   %tmp5 = load i32, i32* %tmp4
   store i32 %tmp5, i32 addrspace(1)* %out
   ret void
 }

test/CodeGen/AMDGPU/scratch-buffer.ll

else:
   br label %done
 
 done:
   %value = phi i32 [%if_value, %if], [%else_value, %else]
   store i32 %value, i32 addrspace(1)* %out
   ret void
 }
 
+; CHECK-LABEL: @neg_vaddr_offset
+; Offset stored in vaddr must be postive, so the immediate value cannot be
+; folded into the offset field of the store.  It must be used to compute
+; the value of vaddr.
+; CHECK: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen{{$}}
+
+define void @neg_vaddr_offset(i32 addrspace(1)* %out, i32 %offset) {
+entry:
+  %array = alloca [8192 x i32]
+  %cmp = icmp slt i32 %offset, 0
+  br i1 %cmp, label %if, label %endif
+
+if:
+  %ptr_offset = add i32 %offset, 4
+  %array_ptr = getelementptr [8192 x i32], [8192 x i32]* %array, i32 0, i32 %ptr_offset
+  store i32 0, i32* %array_ptr
+  br label %endif
+
+endif:
+  ret void
+}
+