[DebugInfo][InstrRef] Fix Wdangling-else warning in InstrRefLDVTest

[lbenes]

Summary

Fix a dangling else that gcc-11 warned about. The EXPECT_EQ macro
expands to an if-else, so the whole construction contains a hidden
dangling else.

[jmorse]

Nice catch, thanks -- I suppose googletest or wherever EXPECT_EQ comes from should have the do {...}while(0) construct wrapping it, but that's way outside my wheelhouse.

(Landing this as you suggested elsewhere).

llvm/unittests/CodeGen/InstrRefLDVTest.cpp

TEST_F(InstrRefLDVTest, pickVPHILocDiamond) {
   Optional<ValueIDNum> Result;
 
   // Simple case: join two distinct values on entry to the block.
   VLiveOuts[1].insert({Var,  DbgValue(LiveInRsp, EmptyProps, DbgValue::Def)});
   VLiveOuts[2].insert({Var,  DbgValue(LiveInRax, EmptyProps, DbgValue::Def)});
   Result = pickVPHILoc(*MBB3, Var, VLiveOutIdx, OutLocsPtr, Preds);
   // Should have picked a PHI in $rsp in block 3.
   EXPECT_TRUE(Result);
-  if (Result)
+  if (Result) {
     EXPECT_EQ(*Result, RspPHIInBlk3);
+  }
 
   // If the incoming values are swapped between blocks, we should not
   // successfully join. The CFG merge would select the right values, but in
   // the wrong conditions.
   std::swap(VLiveOuts[1], VLiveOuts[2]);
   Result = pickVPHILoc(*MBB3, Var, VLiveOutIdx, OutLocsPtr, Preds);
   EXPECT_FALSE(Result);
 
TEST_F(InstrRefLDVTest, pickVPHILocDiamond) {
 
   // However, if we know the value of the incoming VPHI, we can search for its
   // location. Use a PHI machine-value for doing this, as VPHIs should always
   // have PHI values, or they should have been eliminated.
   OutLocs[2][0] = RspPHIInBlk2;
   VLiveOuts[2].find(Var)->second.ID = RspPHIInBlk2;
   Result = pickVPHILoc(*MBB3, Var, VLiveOutIdx, OutLocsPtr, Preds);
   EXPECT_TRUE(Result);
-  if (Result)
+  if (Result) {
     EXPECT_EQ(*Result, RspPHIInBlk3);
+  }
 
   // If that value isn't available from that block, don't join.
   OutLocs[2][0] = LiveInRsp;
   Result = pickVPHILoc(*MBB3, Var, VLiveOutIdx, OutLocsPtr, Preds);
   EXPECT_FALSE(Result);
 
   // Check that we don't pick values when the properties disagree, for example
   // different indirectness or DIExpression.
TEST_F(InstrRefLDVTest, pickVPHILocLoops) {
   Optional<ValueIDNum> Result;
 
   // See that we can merge as normal on a backedge.
   VLiveOuts[0].insert({Var, DbgValue(LiveInRsp, EmptyProps, DbgValue::Def)});
   VLiveOuts[1].insert({Var, DbgValue(LiveInRax, EmptyProps, DbgValue::Def)});
   Result = pickVPHILoc(*MBB1, Var, VLiveOutIdx, OutLocsPtr, Preds);
   // Should have picked a PHI in $rsp in block 1.
   EXPECT_TRUE(Result);
-  if (Result)
+  if (Result) {
     EXPECT_EQ(*Result, RspPHIInBlk1);
+  }
 
   // And that, if the desired values aren't available, we don't merge.
   OutLocs[1][0] = LiveInRsp;
   Result = pickVPHILoc(*MBB1, Var, VLiveOutIdx, OutLocsPtr, Preds);
   EXPECT_FALSE(Result);
 
   // Test the backedge behaviour: PHIs that feed back into themselves can
   // carry this variables value. Feed in LiveInRsp in both $rsp and $rax
   // from the entry block, but only put an appropriate backedge PHI in $rax.
   // Only the $rax location can form the correct PHI.
   OutLocs[0][0] = LiveInRsp;
   OutLocs[0][1] = LiveInRsp;
   OutLocs[1][0] = RaxPHIInBlk1;
   OutLocs[1][1] = RaxPHIInBlk1;
   VLiveOuts[0].clear();
   VLiveOuts[1].clear();
   VLiveOuts[0].insert({Var, DbgValue(LiveInRsp, EmptyProps, DbgValue::Def)});
   // Crucially, a VPHI originating in this block:
   VLiveOuts[1].insert({Var, DbgValue(1, EmptyProps, DbgValue::VPHI)});
   Result = pickVPHILoc(*MBB1, Var, VLiveOutIdx, OutLocsPtr, Preds);
   EXPECT_TRUE(Result);
-  if (Result)
+  if (Result) {
     EXPECT_EQ(*Result, RaxPHIInBlk1);
+  }
 
   // Merging should not be permitted if there's a usable PHI on the backedge,
   // but it's in the wrong place. (Overwrite $rax).
   OutLocs[1][1] = LiveInRax;
   Result = pickVPHILoc(*MBB1, Var, VLiveOutIdx, OutLocsPtr, Preds);
   EXPECT_FALSE(Result);
 
   // Additionally, if the VPHI coming back on the loop backedge isn't from
TEST_F(InstrRefLDVTest, pickVPHILocBadlyNestedLoops) {
 
   // See that we can merge as normal on a backedge.
   VLiveOuts[0].insert({Var, DbgValue(LiveInRsp, EmptyProps, DbgValue::Def)});
   VLiveOuts[1].insert({Var, DbgValue(LiveInRax, EmptyProps, DbgValue::Def)});
   VLiveOuts[2].insert({Var, DbgValue(LiveInRbx, EmptyProps, DbgValue::Def)});
   Result = pickVPHILoc(*MBB1, Var, VLiveOutIdx, OutLocsPtr, Preds);
   // Should have picked a PHI in $rsp in block 1.
   EXPECT_TRUE(Result);
-  if (Result)
+  if (Result) {
     EXPECT_EQ(*Result, RspPHIInBlk1);
+  }
 
   // Check too that permuting the live-out locations prevents merging
   OutLocs[0][0] = LiveInRax;
   OutLocs[1][0] = LiveInRbx;
   OutLocs[2][0] = LiveInRsp;
   Result = pickVPHILoc(*MBB1, Var, VLiveOutIdx, OutLocsPtr, Preds);
   EXPECT_FALSE(Result);
 
   OutLocs[0][0] = LiveInRsp;
   OutLocs[1][0] = LiveInRax;
   OutLocs[2][0] = LiveInRbx;
 
   // Feeding a PHI back on one backedge shouldn't merge (block 1 self backedge
   // wants LiveInRax).
   OutLocs[1][0] = RspPHIInBlk1;
   Result = pickVPHILoc(*MBB1, Var, VLiveOutIdx, OutLocsPtr, Preds);
   EXPECT_FALSE(Result);
 
   // If the variables value on that edge is a VPHI feeding into itself, that's
   // fine.
   VLiveOuts[1].clear();
   VLiveOuts[1].insert({Var, DbgValue(1, EmptyProps, DbgValue::VPHI)});
   Result = pickVPHILoc(*MBB1, Var, VLiveOutIdx, OutLocsPtr, Preds);
   EXPECT_TRUE(Result);
-  if (Result)
+  if (Result) {
     EXPECT_EQ(*Result, RspPHIInBlk1);
+  }
 
   // Likewise: the other backedge being a VPHI from block 1 should be accepted.
   OutLocs[2][0] = RspPHIInBlk1;
   VLiveOuts[2].clear();
   VLiveOuts[2].insert({Var, DbgValue(1, EmptyProps, DbgValue::VPHI)});
   Result = pickVPHILoc(*MBB1, Var, VLiveOutIdx, OutLocsPtr, Preds);
   EXPECT_TRUE(Result);
-  if (Result)
+  if (Result) {
     EXPECT_EQ(*Result, RspPHIInBlk1);
+  }
 
   // Here's where it becomes tricky: we should not merge if there are two
   // _distinct_ backedge PHIs. We can't have a PHI that happens in both rsp
   // and rax for example. We can only pick one location as the live-in.
   OutLocs[2][0] = RaxPHIInBlk1;
   Result = pickVPHILoc(*MBB1, Var, VLiveOutIdx, OutLocsPtr, Preds);
   EXPECT_FALSE(Result);
 
TEST_F(InstrRefLDVTest, pickVPHILocBadlyNestedLoops) {
   OutLocs[1][0] = RspPHIInBlk1;
   OutLocs[1][1] = RaxPHIInBlk1;
   OutLocs[1][2] = RbxPHIInBlk1;
   OutLocs[2][0] = LiveInRsp;
   OutLocs[2][1] = RspPHIInBlk1;
   OutLocs[2][2] = RbxPHIInBlk1;
   Result = pickVPHILoc(*MBB1, Var, VLiveOutIdx, OutLocsPtr, Preds);
   EXPECT_TRUE(Result);
-  if (Result)
+  if (Result) {
     EXPECT_EQ(*Result, RbxPHIInBlk1);
   }
+}
 
 TEST_F(InstrRefLDVTest, vlocJoinDiamond) {
   //        entry
   //        /  \
   //      br1  br2
   //        \  /
   //         ret
   setupDiamondBlocks();