[ARM] Handle commutativity when converting to tADDhirr in Thumb2

[scott-0]

Also, run thumb_rewrite.s tests in Thumb2 now that they pass.

[rengolin]

Great, thanks! LGTM.

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

case ARM::t2SUBri: {
     TmpInst.addOperand(Inst.getOperand(4));
     Inst = TmpInst;
     return true;
   }
   case ARM::t2ADDrr: {
     // If the destination and first source operand are the same, and
     // there's no setting of the flags, use encoding T2 instead of T3.
     // Note that this is only for ADD, not SUB. This mirrors the system
-    // 'as' behaviour. Make sure the wide encoding wasn't explicit.
-    if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
+    // 'as' behaviour.  Also take advantage of ADD being commutative.
+    // Make sure the wide encoding wasn't explicit.
+    bool Swap = false;
+    auto DestReg = Inst.getOperand(0).getReg();
+    bool Transform = DestReg == Inst.getOperand(1).getReg();
+    if (!Transform && DestReg == Inst.getOperand(2).getReg()) {
+      Transform = true;
+      Swap = true;
+    }
+    if (!Transform ||
         Inst.getOperand(5).getReg() != 0 ||
         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
          static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
       break;
     MCInst TmpInst;
     TmpInst.setOpcode(ARM::tADDhirr);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(0));
-    TmpInst.addOperand(Inst.getOperand(2));
+    TmpInst.addOperand(Inst.getOperand(Swap ? 1 : 2));
     TmpInst.addOperand(Inst.getOperand(3));
     TmpInst.addOperand(Inst.getOperand(4));
     Inst = TmpInst;
     return true;
   }
   case ARM::tADDrSP: {
     // If the non-SP source operand and the destination operand are not the
     // same, we need to use the 32-bit encoding if it's available.

test/MC/ARM/thumb2-narrow-dp.ll

// CHECK: it eq                     @ encoding: [0x08,0xbf]
     ADDSEQ   r1, r1, #8          // T3
 // CHECK: addseq.w r1, r1, #8       @ encoding: [0x11,0xf1,0x08,0x01]
 
 // ADD register (not SP) A8.8.6 (commutative)
     ADDS     r0, r2, r1          // ADDS has T1 narrow 3 operand
 // CHECK: adds  r0, r2, r1          @ encoding: [0x50,0x18]
     ADDS     r2, r2, r1          // ADDS has T1 narrow 3 operand
 // CHECK: adds  r2, r2, r1          @ encoding: [0x52,0x18]
+    ADD      r3, r1, r3          // T2
+// CHECK: add  r3, r1               @ encoding: [0x0b,0x44]
 
     IT EQ
 // CHECK: it eq                     @ encoding: [0x08,0xbf]
     ADDEQ    r0, r2, r1          // (In IT) ADD has T1 narrow 3 operand
 // CHECK: addeq r0, r2, r1          @ encoding: [0x50,0x18]
     IT EQ
 // CHECK: it eq                     @ encoding: [0x08,0xbf]
     ADDEQ    r2, r2, r1          // (In IT) ADD has T1 narrow 3 operand