[ARM] Thumb1 3 to 2 operand convertion for commutative operations

[scott-0]

Summary

Implements transformations like 'adcs r0, r1, r0' => 'adcs r0, r1' that are already done for Thumb2 targets.

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

void ARMAsmParser::tryConvertingToTwoOperandForm(StringRef Mnemonic,
   // e.g. 'adds r0, r0, #1' transforms to 'adds r0, #1'
   if (!(Mnemonic == "add" || Mnemonic == "sub" || Mnemonic == "and" ||
         Mnemonic == "eor" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
         Mnemonic == "asr" || Mnemonic == "adc" || Mnemonic == "sbc" ||
         Mnemonic == "ror" || Mnemonic == "orr" || Mnemonic == "bic"))
     return;
 
   bool Transform = Op3.getReg() == Op4.getReg();
+
+  // For communtative operations, we might be able to transform if we swap
+  // Op4 and Op5.  The 'ADD Rdm, SP, Rdm' form is already handled specially
+  // as tADDrsp.
+  const ARMOperand *LastOp = &Op5;
+  bool Swap = false;
+  if (!Transform && Op5.isReg() && Op3.getReg() == Op5.getReg() &&
+      ((Mnemonic == "add" && Op4.getReg() != ARM::SP) ||
+       Mnemonic == "and" || Mnemonic == "eor" ||
+       Mnemonic == "adc" || Mnemonic == "orr")) {
+    Swap = true;
+    LastOp = &Op4;
+    Transform = true;
+  }
+
   // If both registers are the same then remove one of them from
   // the operand list, with certain exceptions.
   if (Transform) {
     // Don't transform 'adds Rd, Rd, Rm' or 'sub{s} Rd, Rd, Rm' because the
     // 2 operand forms don't exist.
     if (((Mnemonic == "add" && CarrySetting) || Mnemonic == "sub") &&
-        Op5.isReg())
+        LastOp->isReg())
       Transform = false;
 
     // Don't transform 'add/sub{s} Rd, Rd, #imm' if the immediate fits into
     // 3-bits because the ARMARM says not to.
-    if ((Mnemonic == "add" || Mnemonic == "sub") && Op5.isImm0_7())
+    if ((Mnemonic == "add" || Mnemonic == "sub") && LastOp->isImm0_7())
       Transform = false;
   }
 
-  if (Transform)
+  if (Transform) {
+    if (Swap)
+      std::swap(Op4, Op5);
     Operands.erase(Operands.begin() + 3);
   }
+}
 
 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
                                           OperandVector &Operands) {
   // FIXME: This is all horribly hacky. We really need a better way to deal
   // with optional operands like this in the matcher table.
 
   // The 'mov' mnemonic is special. One variant has a cc_out operand, while
   // another does not. Specifically, the MOVW instruction does not. So we

test/MC/ARM/thumb2-narrow-dp.ll

 // CHECK: it eq                     @ encoding: [0x08,0xbf]
     ADDSEQ   r2, r2, r1          // T3
 // CHECK: addseq.w r2, r2, r1       @ encoding: [0x12,0xeb,0x01,0x02]
 
     ADD      r3, r3, r1          // T2
 // CHECK: add  r3, r1               @ encoding: [0x0b,0x44]
     ADD      r4, r4, pc          // T2
 // CHECK: add  r4, pc               @ encoding: [0x7c,0x44]
+    ADD      r4, pc, r4          // T2
+// CHECK: add  r4, pc               @ encoding: [0x7c,0x44]
     ADD      pc, pc, r2          // T2
 // CHECK: add  pc, r2               @ encoding: [0x97,0x44]
+    ADD      pc, r2, pc          // T2
+// CHECK: add  pc, r2               @ encoding: [0x97,0x44]
 
 // ADD (SP plus immediate) A8.8.9
     ADD      sp, sp, #20         // T2
 // FIXME: ARMARM says 'add   sp, sp, #20'
 // CHECK: add   sp, #20         @ encoding: [0x05,0xb0]
 
 // ADD (SP plus register) A8.8.10 (commutative)
     ADD      r9, sp, r9          // T1

test/MC/ARM/thumb_rewrites.s

 @ CHECK: adds   r0, #8              @ encoding: [0x08,0x30]
 
     adds    r0, r0, r0
 @ CHECK: adds   r0, r0, r0          @ encoding: [0x00,0x18]
 
     add     r0, r0, r8
 @ CHECK: add    r0, r8              @ encoding: [0x40,0x44]
 
+    add     r1, r8, r1
+@ CHECK: add    r1, r8              @ encoding: [0x41,0x44]
+
     add     sp, sp, r0
 @ CHECK: add    sp, r0              @ encoding: [0x85,0x44]
 
     add     r4, sp, r4
 @ CHECK: add    r4, sp, r4          @ encoding: [0x6c,0x44]
 
     add     r4, r4, sp
 @ CHECK: add    r4, sp              @ encoding: [0x6c,0x44]

 @ CHECK: subs   r3, #5              @ encoding: [0x05,0x3b]
 
     subs    r2, r2, #8
 @ CHECK: subs   r2, #8              @ encoding: [0x08,0x3a]
 
     sub     sp, sp, #16
 @ CHECK: sub    sp, #16             @ encoding: [0x84,0xb0]
 
+    ands    r0, r1, r0
+@ CHECK: ands   r0, r1              @ encoding: [0x08,0x40]
+
     ands    r0, r0, r1
 @ CHECK: ands   r0, r1              @ encoding: [0x08,0x40]
 
     eors    r0, r0, r1
 @ CHECK: eors   r0, r1              @ encoding: [0x48,0x40]
 
+    eors    r0, r1, r0
+@ CHECK: eors   r0, r1              @ encoding: [0x48,0x40]
+
     lsls    r0, r0, r1
 @ CHECK: lsls   r0, r1              @ encoding: [0x88,0x40]
 
     lsrs    r0, r0, r1
 @ CHECK: lsrs   r0, r1              @ encoding: [0xc8,0x40]
 
     asrs    r0, r0, r1
 @ CHECK: asrs   r0, r1              @ encoding: [0x08,0x41]
 
     adcs    r0, r0, r1
 @ CHECK: adcs   r0, r1              @ encoding: [0x48,0x41]
 
+    adcs    r0, r1, r0
+@ CHECK: adcs   r0, r1              @ encoding: [0x48,0x41]
+
     sbcs    r0, r0, r1
 @ CHECK: sbcs   r0, r1              @ encoding: [0x88,0x41]
 
     rors    r0, r0, r1
 @ CHECK: rors   r0, r1              @ encoding: [0xc8,0x41]
 
     orrs    r0, r0, r1
 @ CHECK: orrs   r0, r1              @ encoding: [0x08,0x43]
 
+    orrs    r0, r1, r0
+@ CHECK: orrs   r0, r1              @ encoding: [0x08,0x43]
+
     bics    r0, r0, r1
 @ CHECK: bics   r0, r1              @ encoding: [0x88,0x43]