[ARM] Add Thumb2 ADD with PC narrowing from 3 operand to 2 operand

[scott-0]

Summary

The existing Thumb2 ADD narrowing misses cases involving the PC. This patch adds them.

Depends on http://reviews.llvm.org/D11054 and http://reviews.llvm.org/D11053.

[rengolin]

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

5474

This comment could be moved down with the code...

[scott-0]

Thanks!

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

5474

Will do.

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
     else
       CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
   } else
     CanAcceptPredicationCode = true;
 }
 
 // \brief Some Thumb1 instructions have two operand forms that are not
 // available as three operand, convert to two operand form if possible.
+// For most Thumb2 cases we just generate the 3 operand form and
+// reduce it in processInstruction, but for ADD involving PC the the 3
+// operand form won't accept PC so we do the transformation here.
 //
 // FIXME: We would really like to be able to tablegen'erate this.
 void ARMAsmParser::tryConvertingToTwoOperandForm(StringRef Mnemonic,
                                                  bool CarrySetting,
                                                  OperandVector &Operands) {
-  if (Operands.size() != 6 || !isThumbOne())
+  if (Operands.size() != 6)
     return;
 
   ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
   ARMOperand &Op4 = static_cast<ARMOperand &>(*Operands[4]);
   if (!Op3.isReg() || !Op4.isReg())
     return;
 
   ARMOperand &Op5 = static_cast<ARMOperand &>(*Operands[5]);
+  if (isThumbTwo()) {
+    if (Mnemonic != "add" ||
+        !(Op3.getReg() == ARM::PC || Op4.getReg() == ARM::PC ||
+          (Op5.isReg() && Op5.getReg() == ARM::PC)))
+      return;
+  } else if (!isThumbOne())
+    return;
 
   // If first 2 operands of a 3 operand instruction are the same
   // then transform to 2 operand version of the same instruction
   // e.g. 'adds r0, r0, #1' transforms to 'adds r0, #1'
   if (!(Mnemonic == "add" || Mnemonic == "sub" || Mnemonic == "and" ||
         Mnemonic == "eor" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
         Mnemonic == "asr" || Mnemonic == "adc" || Mnemonic == "sbc" ||
         Mnemonic == "ror" || Mnemonic == "orr" || Mnemonic == "bic"))

test/MC/ARM/thumb2-narrow-dp.ll

 // CHECK: addseq.w r0, r2, r1       @ encoding: [0x12,0xeb,0x01,0x00]
     IT EQ
 // CHECK: it eq                     @ encoding: [0x08,0xbf]
     ADDSEQ   r2, r2, r1          // T3
 // CHECK: addseq.w r2, r2, r1       @ encoding: [0x12,0xeb,0x01,0x02]
 
     ADD      r3, r3, r1          // T2
 // CHECK: add  r3, r1               @ encoding: [0x0b,0x44]
+    ADD      r4, r4, pc          // T2
+// CHECK: add  r4, pc               @ encoding: [0x7c,0x44]
+    ADD      pc, pc, r2          // T2
+// CHECK: add  pc, r2               @ encoding: [0x97,0x44]
 
 // ADD (SP plus immediate) A8.8.9
     ADD      sp, sp, #20         // T2
 // FIXME: ARMARM says 'add   sp, sp, #20'
 // CHECK: add   sp, #20         @ encoding: [0x05,0xb0]
 
 // ADD (SP plus register) A8.8.10 (commutative)
     ADD      r9, sp, r9          // T1