[ARM] Add ADD tests for Thumb2 narrowing (nfc)

[scott-0]

Summary

Add missing tests. These already pass. Some actual fixes coming in later patches.

[rengolin]

test/MC/ARM/thumb2-narrow-dp.ll

67

Not testing for higher registers in T2/T3? Or conditional T2?

78

Not testing T1/3/4? Conditionals?

[scott-0]

Thanks for the review!

test/MC/ARM/thumb2-narrow-dp.ll

67

I didn't include them because the 3-to-2 operand narrowing doesn't affect them. I'm happy to add them to make this file more complete. Hireg T2 and T3 are already tested in basic-thumb2-instructions.s (line 119+, hireg T2 and T3).

I can't find a test for conditional T2. I'm happy to add one, but I think it would fit best in same part of basic-thumb2-instructions.s.

78

I can add some to basic-thumb2-instructions.s.

And, I'm happy to add them here, too, if you think that's best.

[rengolin]

test/MC/ARM/thumb2-narrow-dp.ll

67

No, that's ok. If you want, for completeness, you can add another commit later. This is related to 3-to-2 changes and should remain as such.

78

Same here.

test/MC/ARM/thumb2-narrow-dp.ll

 // RUN: llvm-mc -triple thumbv7 -show-encoding < %s | FileCheck %s
 
 // Test each of the Thumb1 data-processing instructions
 // The assembly syntax for these instructions allows an optional Rd register
 //   OP{S}{<c>}{<q>}  {<Rd>,} <Rn>, <Rm>
 // Assemblers should chose the narrow thumb encoding when possible, i.e.
 //   - Rd == Rn 
 //   - Rd, Rn and Rm are < r8
-// In addition, some operations are commutative, allowing the transormation 
+// In addition, some operations are commutative, allowing the transformation
 // when:
 //   - Rd == Rn || Rd == Rm
 //   - Rd, Rn and Rm are < r8
 
+// ADD immediate (not SP) A8.8.4
+    ADDS     r0, r0, #5          // T1
+// CHECK: adds  r0, r0, #5          @ encoding: [0x40,0x1d]
+    ADDS     r1, r1, #8          // T2
+// CHECK: adds  r1, #8              @ encoding: [0x08,0x31]
+    ADDS.W   r1, r1, #8          // .w => T3
+// CHECK: adds.w r1, r1, #8         @ encoding: [0x11,0xf1,0x08,0x01]
+    ADDS     r8, r8, #8          // T3
+// CHECK: adds.w r8, r8, #8         @ encoding: [0x18,0xf1,0x08,0x08]
+
+    IT EQ
+// CHECK: it eq                     @ encoding: [0x08,0xbf]
+    ADDEQ    r0, r0, #5          // T1
+// CHECK: addeq r0, r0, #5          @ encoding: [0x40,0x1d]
+    IT EQ
+// CHECK: it eq                     @ encoding: [0x08,0xbf]
+    ADDEQ    r1, r1, #8          // T2
+// CHECK: addeq r1, #8              @ encoding: [0x08,0x31]
+
+    IT EQ
+// CHECK: it eq                     @ encoding: [0x08,0xbf]
+    ADDSEQ   r0, r0, #5          // T3
+// CHECK: addseq.w r0, r0, #5       @ encoding: [0x10,0xf1,0x05,0x00]
+    IT EQ
+// CHECK: it eq                     @ encoding: [0x08,0xbf]
+    ADDSEQ   r1, r1, #8          // T3
+// CHECK: addseq.w r1, r1, #8       @ encoding: [0x11,0xf1,0x08,0x01]
+
+// ADD register (not SP) A8.8.6 (commutative)
+    ADDS     r0, r2, r1          // ADDS has T1 narrow 3 operand
+// CHECK: adds  r0, r2, r1          @ encoding: [0x50,0x18]
+    ADDS     r2, r2, r1          // ADDS has T1 narrow 3 operand
+// CHECK: adds  r2, r2, r1          @ encoding: [0x52,0x18]
+
+    IT EQ
+// CHECK: it eq                     @ encoding: [0x08,0xbf]
+    ADDEQ    r0, r2, r1          // (In IT) ADD has T1 narrow 3 operand
+// CHECK: addeq r0, r2, r1          @ encoding: [0x50,0x18]
+    IT EQ
+// CHECK: it eq                     @ encoding: [0x08,0xbf]
+    ADDEQ    r2, r2, r1          // (In IT) ADD has T1 narrow 3 operand
+// CHECK: addeq r2, r2, r1          @ encoding: [0x52,0x18]
+
+    IT EQ
+// CHECK: it eq                     @ encoding: [0x08,0xbf]
+    ADDSEQ   r0, r2, r1          // T3
+// CHECK: addseq.w r0, r2, r1       @ encoding: [0x12,0xeb,0x01,0x00]
+    IT EQ
+// CHECK: it eq                     @ encoding: [0x08,0xbf]
+    ADDSEQ   r2, r2, r1          // T3
+// CHECK: addseq.w r2, r2, r1       @ encoding: [0x12,0xeb,0x01,0x02]
+
+    ADD      r3, r3, r1          // T2
+// CHECK: add  r3, r1               @ encoding: [0x0b,0x44]
+
+// ADD (SP plus immediate) A8.8.9
+    ADD      sp, sp, #20         // T2
+// FIXME: ARMARM says 'add   sp, sp, #20'
+// CHECK: add   sp, #20         @ encoding: [0x05,0xb0]
+
+// ADD (SP plus register) A8.8.10 (commutative)
+    ADD      r9, sp, r9          // T1
+// CHECK: add   r9, sp, r9          @ encoding: [0xe9,0x44]
+    ADD      sp, sp, r10         // T2
+// CHECK: add   sp, r10             @ encoding: [0xd5,0x44]
+
 // AND (commutative)
     ANDS     r0, r2, r1          // Must be wide - 3 distinct registers
     ANDS     r2, r2, r1          // Should choose narrow
     ANDS     r2, r1, r2          // Should choose narrow - commutative
     ANDS.W   r0, r0, r1          // Explicitly wide
     ANDS.W   r3, r1, r3  
     AND      r0, r1, r0          // Must use wide encoding as not flag-setting
     ANDS     r7, r7, r1          // Should use narrow