[ARC] Add additional mov immediate instruction formats with a fix for u6 decoding

[thomasjohns]

Summary

This adds the mov_f_ru6 and mov_cc_f_ru6 instruction formats. Adding the f flag to these instructions revealed a bug in the u6 decoding (details to be explained in context below). This u6 decoding bug is fixed here.

Many new decoder test cases have also been added, exercising the changes mentioned above in addition to further exercising predicated binary instructions (the support for these was added here https://reviews.llvm.org/rG1cda1e618648d463f89eb5cea8c9849bc0074b24, but that patch only tested predicated rsub).

[thomasjohns]

llvm/lib/Target/ARC/ARCInstrFormats.td

289

This change was really just a rename from F32_SOP_CC_RU6 to F32_DOP_CC_RU6. The instruction is really a "dual-operand" instruction, and was just named incorrectly earlier.

The full diff shows up rather than the rename because the definition was moved to be adjacent to other dual operand instructions.

367

This field was unused.

llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp

307

This API was misinterpreted earlier to be fieldFromInstruction(..., startBit, endBit) instead of fieldFromInstruction(..., startBit, numBits) (correct). This didn't materialize earlier because all of the associated tests had 0'd out high order bits. So overreading the bits for the u6 instruction wasn't noticed because it didn't change the u6 value.

Once the f flag was added, it caused the u6 decoding here to overflow, because the f flag bit was 11 bits away from the u6 start bit.

[marksl]

llvm/test/MC/Disassembler/ARC/alu.txt

219

You should probably check something other than R0 to verify the field is defined correctly. R0 will just encode zeros which may not show up an error.

[thomasjohns]

llvm/test/MC/Disassembler/ARC/alu.txt

219

Okay thanks, that's a good idea. I will update the patch with more varied register numbers.

[thomasjohns]

Make register numbers and immediate values more varied in decoder tests.

[marksl]

Looks good to me

llvm/lib/Target/ARC/ARCInstrFormats.td

class F32_SOP_RR<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
   let Inst{23-22} = 0b00;
   let Inst{21-16} = 0b101111;
   let Inst{15} = F;
   let Inst{14-12} = B{5-3};
   let Inst{11-6} = C;
   let Inst{5-0} = subop;
 }
 
-// Single Operand Immediate Instructions.
-// 1-register, unsigned 6-bit immediate Single Operand instruction with
-// condition code.
-// |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
-// |B[2-0]  | 1| 1|            subop| F|B[5-3]  |U6           |1|cc       |
-class F32_SOP_CC_RU6<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
-                     string asmstr, list<dag> pattern> :
-  InstARC<4, outs, ins, asmstr, pattern> {
-
-  bits<5> cc;
-  bits<6> U6;
-  bits<6> B;
-
-  let Inst{31-27} = major;
-  let Inst{26-24} = B{2-0};
-  let Inst{23-22} = 0b11;
-  let Inst{21-16} = subop;
-  let Inst{15} = F;
-  let Inst{14-12} = B{5-3};
-  let Inst{11-6} = U6;
-  let Inst{5} = 1;
-  let Inst{4-0} = cc;
-
-  let DecoderMethod = "DecodeCCRU6Instruction";
-}
-
 // Dual Operand Instructions.  Inst[21-16] specifies the specific operation
 // for this format.
 
 // 3-register Dual Operand instruction.
 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
 // |B[2-0]  | 0| 0|            subop| F|B[5-3]  |C            |A          |
 class F32_DOP_RR<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
                  string asmstr, list<dag> pattern> :
class F32_DOP_RU6<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
   let Inst{23-22} = 0b01;
   let Inst{21-16} = subop;
   let Inst{15} = F;
   let Inst{14-12} = B{5-3};
   let Inst{11-6} = U6;
   let Inst{5-0} = A;
 }
 
+// 1-register, unsigned 6-bit, immediate Dual Operand instruction with
+// condition code.
+// |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
+// |B[2-0]  | 1| 1|            subop| F|B[5-3]  |U6           |1|cc       |
+class F32_DOP_CC_RU6<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
+                     string asmstr, list<dag> pattern> :
+  InstARC<4, outs, ins, asmstr, pattern> {
+
+  bits<5> cc;
+  bits<6> U6;
+  bits<6> B;
+
+  let Inst{31-27} = major;
+  let Inst{26-24} = B{2-0};
+  let Inst{23-22} = 0b11;
+  let Inst{21-16} = subop;
+  let Inst{15} = F;
+  let Inst{14-12} = B{5-3};
+  let Inst{11-6} = U6;
+  let Inst{5} = 1;
+  let Inst{4-0} = cc;
+
+  let DecoderMethod = "DecodeCCRU6Instruction";
+}
+
 // 2-register, unsigned 6-bit immediate Dual Operand instruction with
 // condition code. This instruction uses B as the first 2 operands
 // (i.e, add.cc B, B, u6).
 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
 // |B[2-0]  | 1| 1|            subop| F|B[5-3]  |U6           |1|cc       |
 class F32_DOP_CC_RRU6<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
                       string asmstr, list<dag> pattern> :
   InstARC<4, outs, ins, asmstr, pattern> {
   bits<5> cc;
   bits<6> U6;
   bits<6> B;
-  bits<6> A;
 
   let Inst{31-27} = major;
   let Inst{26-24} = B{2-0};
   let Inst{23-22} = 0b11;
   let Inst{21-16} = subop;
   let Inst{15} = F;
   let Inst{14-12} = B{5-3};
   let Inst{11-6} = U6;

llvm/lib/Target/ARC/ARCInstrInfo.td

 def MOV_rlimm : F32_DOP_RLIMM<0b00100, 0b001010, 0,
                       (outs GPR32:$B), (ins i32imm:$LImm),
                       "mov\t$B, $LImm", []>;
 
 def MOV_ru6 : F32_DOP_RU6<0b00100, 0b001010, 0,
                           (outs GPR32:$B), (ins immU6:$U6),
                           "mov\t$B, $U6", []>;
 
-def cmov : PatFrag<(ops node:$op1, node:$op2, node:$cc),
-                   (ARCcmov $op1, $op2, $cc)>;
-let Uses = [STATUS32] in {
-  def MOVcc : F32_DOP_CC_RR<0b00100, 0b001010, 0,
-                 (outs GPR32:$B),
-                 (ins GPR32:$C, GPR32:$fval, cmovpred:$cc),
-                 !strconcat("mov.", "$cc\t$B, $C"),
-                 [(set GPR32:$B, (cmov i32:$C, i32:$fval, cmovpred:$cc))]> {
-    let Constraints = "$B = $fval";
-  }
+def MOV_f_ru6 : F32_DOP_RU6<0b00100, 0b001010, 1,
+                          (outs GPR32:$B), (ins u6:$U6),
+                          "mov.f\t$B, $U6", []> {
+  let isAsCheapAsAMove=1;
+  let Defs = [STATUS32];
 
-  def MOVcc_ru6 : F32_SOP_CC_RU6<0b00100, 0b001010, 0,
-                 (outs GPR32:$b), (ins u6:$c, CCOp:$cc, GPR32:$b2),
-                 "mov.$cc\t$b, $c", []> {
-    let isAsCheapAsAMove=0;
-    let isPredicable=1;
-    let isReMaterializable=0;
-    let Constraints="$b2 = $b";
+def cmov : PatFrag<(ops node:$op1, node:$op2, node:$cc),
+                   (ARCcmov $op1, $op2, $cc)>;
+let Uses = [STATUS32], isAsCheapAsAMove = 1, isPredicable=1,
+    isReMaterializable = 0, Constraints = "$B = $B2" in {
+  def MOV_cc : F32_DOP_CC_RR<0b00100, 0b001010, 0,
+                 (outs GPR32:$B), (ins GPR32:$C, GPR32:$B2, cmovpred:$cc),
+                 "mov.$cc\t$B, $C",
+                 [(set GPR32:$B, (cmov i32:$C, i32:$B2, cmovpred:$cc))]>;
+
+  def MOV_cc_ru6 : F32_DOP_CC_RU6<0b00100, 0b001010, 0,
+                 (outs GPR32:$B), (ins u6:$C, CCOp:$cc, GPR32:$B2),
+                 "mov.$cc\t$B, $C", []>;
+
+  def MOV_cc_f_ru6 : F32_DOP_CC_RU6<0b00100, 0b001010, 1,
+                    (outs GPR32:$B), (ins u6:$C, CCOp:$cc, GPR32:$B2),
+                    "mov.$cc.f\t$B, $C", []> {
+    let Defs = [STATUS32];
   }
 }
 
 def : Pat<(ARCGAWrapper tglobaladdr:$addr),
            (MOV_rlimm tglobaladdr:$addr)>;
 
 def : Pat<(ARCGAWrapper tjumptable:$addr),
            (MOV_rlimm tjumptable:$addr)>;

llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp

 static DecodeStatus DecodeCCRU6Instruction(MCInst &Inst, uint64_t Insn,
                                            uint64_t Address,
                                            const void *Decoder) {
   unsigned DstB;
   LLVM_DEBUG(dbgs() << "Decoding CCRU6 instruction:\n");
   DstB = decodeBField(Insn);
   DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder);
   using Field = decltype(Insn);
-  Field U6Field = fieldFromInstruction(Insn, 6, 11);
+  Field U6Field = fieldFromInstruction(Insn, 6, 6);
   Inst.addOperand(MCOperand::createImm(U6Field));
   Field CCField = fieldFromInstruction(Insn, 0, 4);
   Inst.addOperand(MCOperand::createImm(CCField));
   return MCDisassembler::Success;
 }
 
 DecodeStatus ARCDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
                                              ArrayRef<uint8_t> Bytes,

llvm/test/MC/Disassembler/ARC/alu.txt

 0x00 0x20 0xc2 0x00
 
 # CHECK: add %r2, %r0, %r4 
 0x00 0x20 0x02 0x01 
 
 # CHECK: add %r2, %r7, %r4 
 0x00 0x27 0x02 0x01 
 
+# CHECK: add.eq %r0, %r0, 1
+0xc0 0x20 0x61 0x00
+
+# CHECK: add.lt %r6, %r6, 16
+0xc0 0x26 0x2b 0x04
+
+# CHECK: add.le %r15, %r15, 31
+0xc0 0x27 0xec 0x17
+
+# CHECK: add.gt %r0, %r0, 1
+0xc0 0x20 0x69 0x00
+
+# CHECK: add.ge %r6, %r6, 16
+0xc0 0x26 0x2a 0x04
+
+# CHECK: add.p %r15, %r15, 31
+0xc0 0x27 0xe3 0x17
+
+# CHECK: add.n %r0, %r0, 1
+0xc0 0x20 0x64 0x00
+
+# CHECK: add.vs %r6, %r6, 16
+0xc0 0x26 0x27 0x04
+
+# CHECK: add.pnz %r15, %r15, 31
+0xc0 0x27 0xef 0x17
+
+# CHECK: add.eq.f %r0, %r0, 1
+0xc0 0x20 0x61 0x80
+
+# CHECK: add.lt.f %r6, %r6, 16
+0xc0 0x26 0x2b 0x84
+
+# CHECK: add.le.f %r15, %r15, 31
+0xc0 0x27 0xec 0x97
+
+# CHECK: add.gt.f %r0, %r0, 1
+0xc0 0x20 0x69 0x80
+
+# CHECK: add.ge.f %r6, %r6, 16
+0xc0 0x26 0x2a 0x84
+
+# CHECK: add.p.f %r15, %r15, 31
+0xc0 0x27 0xe3 0x97
+
+# CHECK: add.n.f %r0, %r0, 1
+0xc0 0x20 0x64 0x80
+
+# CHECK: add.vs.f %r6, %r6, 16
+0xc0 0x26 0x27 0x84
+
+# CHECK: add.pnz.f %r15, %r15, 31
+0xc0 0x27 0xef 0x97
+
 # CHECK: and %r2, %r7, %r4 
 0x04 0x27 0x02 0x01 
 
 # CHECK: and.f %r2, %r7, %r4
 0x04 0x27 0x02 0x81
 
 # CHECK: and %r2, %r7, 4 
 0x44 0x27 0x02 0x01 
 
 # CHECK: and %r1, %r1, 255
 0x84 0x21 0xc3 0x0f
 
 # CHECK: and.f %r1, %r1, 255
 0x84 0x21 0xc3 0x8f
 
+# CHECK: and.eq %r0, %r0, 0
+0xc4 0x20 0x21 0x00
+
+# CHECK: and.lt %r6, %r6, 16
+0xc4 0x26 0x2b 0x04
+
+# CHECK: and.le %r15, %r15, 31
+0xc4 0x27 0xec 0x17
+
+# CHECK: and.gt %r0, %r0, 0
+0xc4 0x20 0x29 0x00
+
+# CHECK: and.ge %r6, %r6, 16
+0xc4 0x26 0x2a 0x04
+
+# CHECK: and.p %r15, %r15, 31
+0xc4 0x27 0xe3 0x17
+
+# CHECK: and.n %r0, %r0, 0
+0xc4 0x20 0x24 0x00
+
+# CHECK: and.vs %r6, %r6, 16
+0xc4 0x26 0x27 0x04
+
+# CHECK: and.pnz %r15, %r15, 31
+0xc4 0x27 0xef 0x17
+
+# CHECK: and.eq.f %r0, %r0, 0
+0xc4 0x20 0x21 0x80
+
+# CHECK: and.lt.f %r6, %r6, 16
+0xc4 0x26 0x2b 0x84
+
+# CHECK: and.le.f %r15, %r15, 31
+0xc4 0x27 0xec 0x97
+
+# CHECK: and.gt.f %r0, %r0, 0
+0xc4 0x20 0x29 0x80
+
+# CHECK: and.ge.f %r6, %r6, 16
+0xc4 0x26 0x2a 0x84
+
+# CHECK: and.p.f %r15, %r15, 31
+0xc4 0x27 0xe3 0x97
+
+# CHECK: and.n.f %r0, %r0, 0
+0xc4 0x20 0x24 0x80
+
+# CHECK: and.vs.f %r6, %r6, 16
+0xc4 0x26 0x27 0x84
+
+# CHECK: and.pnz.f %r15, %r15, 31
+0xc4 0x27 0xef 0x97
+
 # CHECK: asl %r1, %r1, 2 
 0x40 0x29 0x81 0x00 
 
 # CHECK: asl %r0, %r0, %r0
 0x00 0x28 0x00 0x00
 
 # CHECK: asl.f %r0, %r0, %r0
 0x00 0x28 0x00 0x80

 0x58 0x23 0x43 0x34
 
 # CHECK: sub3 %fp, %fp, -1
 0x99 0x23 0xff 0x3f
 
 # CHECK: sub3.f %fp, %fp, -1
 0x99 0x23 0xff 0xbf
 
-# CHECK: rsub.eq %r0, %r0, 30
-0xce 0x20 0xa1 0x07
-
 # CHECK: rsub.ne %r0, %r0, 31
 0xce 0x20 0xe2 0x07
 
+# CHECK: rsub.eq %r0, %r0, 1
+0xce 0x20 0x61 0x00
+
+# CHECK: rsub.lt %r6, %r6, 16
+0xce 0x26 0x2b 0x04
+
+# CHECK: rsub.le %r15, %r15, 31
+0xce 0x27 0xec 0x17
+
+# CHECK: rsub.gt %r0, %r0, 1
+0xce 0x20 0x69 0x00
+
+# CHECK: rsub.ge %r6, %r6, 16
+0xce 0x26 0x2a 0x04
+
+# CHECK: rsub.p %r15, %r15, 31
+0xce 0x27 0xe3 0x17
+
+# CHECK: rsub.n %r0, %r0, 1
+0xce 0x20 0x64 0x00
+
+# CHECK: rsub.vs %r6, %r6, 16
+0xce 0x26 0x27 0x04
+
+# CHECK: rsub.pnz %r15, %r15, 31
+0xce 0x27 0xef 0x17
+
 # CHECK: rsub.ne.f %r0, %r0, 31
 0xce 0x20 0xe2 0x87
+
+# CHECK: rsub.eq.f %r0, %r0, 1
+0xce 0x20 0x61 0x80
+
+# CHECK: rsub.lt.f %r6, %r6, 16
+0xce 0x26 0x2b 0x84
+
+# CHECK: rsub.le.f %r15, %r15, 31
+0xce 0x27 0xec 0x97
+
+# CHECK: rsub.gt.f %r0, %r0, 1
+0xce 0x20 0x69 0x80
+
+# CHECK: rsub.ge.f %r6, %r6, 16
+0xce 0x26 0x2a 0x84
+
+# CHECK: rsub.p.f %r15, %r15, 31
+0xce 0x27 0xe3 0x97
+
+# CHECK: rsub.n.f %r0, %r0, 1
+0xce 0x20 0x64 0x80
+
+# CHECK: rsub.vs.f %r6, %r6, 16
+0xce 0x26 0x27 0x84
+
+# CHECK: rsub.pnz.f %r15, %r15, 31
+0xce 0x27 0xef 0x97

llvm/test/MC/Disassembler/ARC/misc.txt

 0x4a 0x21 0x00 0x05
 
 # CHECK: mov.eq %r0, 32
 0xca 0x20 0x21 0x08
 
 # CHECK: mov.ne %r0, 0
 0xca 0x20 0x22 0x00
 
+# CHECK: mov.eq %r0, 0
+0xca 0x20 0x21 0x00
+
+# CHECK: mov.lt %r6, 16
+0xca 0x26 0x2b 0x04
+
+# CHECK: mov.le %r15, 31
+0xca 0x27 0xec 0x17
+
+# CHECK: mov.gt %r0, 0
+0xca 0x20 0x29 0x00
+
+# CHECK: mov.ge %r6, 16
+0xca 0x26 0x2a 0x04
+
+# CHECK: mov.p %r15, 31
+0xca 0x27 0xe3 0x17
+
+# CHECK: mov.n %r0, 0
+0xca 0x20 0x24 0x00
+
+# CHECK: mov.vs %r6, 16
+0xca 0x26 0x27 0x04
+
+# CHECK: mov.pnz %r15, 31
+0xca 0x27 0xef 0x17
+
+# CHECK: mov.f %r0, 0
+0x4a 0x20 0x00 0x80
+
+# CHECK: mov.f %r6, 16
+0x4a 0x26 0x00 0x84
+
+# CHECK: mov.f %r15, 31
+0x4a 0x27 0xc0 0x97
+
+# CHECK: mov.eq.f %r0, 0
+0xca 0x20 0x21 0x80
+
+# CHECK: mov.lt.f %r6, 16
+0xca 0x26 0x2b 0x84
+
+# CHECK: mov.le.f %r15, 31
+0xca 0x27 0xec 0x97
+
+# CHECK: mov.gt.f %r0, 0
+0xca 0x20 0x29 0x80
+
+# CHECK: mov.ge.f %r6, 16
+0xca 0x26 0x2a 0x84
+
+# CHECK: mov.p.f %r15, 31
+0xca 0x27 0xe3 0x97
+
+# CHECK: mov.n.f %r0, 0
+0xca 0x20 0x24 0x80
+
+# CHECK: mov.vs.f %r6, 16
+0xca 0x26 0x27 0x84
+
+# CHECK: mov.pnz.f %r15, 31
+0xca 0x27 0xef 0x97
+
 # CHECK: st.aw %fp, [%sp,-4]
 0xfc 0x1c 0xc8 0xb6
 
 # CHECK: ld.ab %fp, [%sp,4]
 0x04 0x14 0x1b 0x34
 
 # CHECK: bl -2028
 0x16 0x08 0xcf 0xff