Add tablegen definition for the Find Leading Set (FLS) instruction for the ARC backend

[thomasjohns]

Summary

This adds an entry for the FLS instruction to tablegen and demonstrates the ability to decode this instruction from an object file.

For example, when disassembling the object file derived from compiling:

int f(int x) {
  return __builtin_clz(x);
}

we used to have:

00000000 <f>:
       0: 2f 28 13 80   <unknown>
       4: ca 20 21 08   mov.eq  %r0, 32
       8: e0 7f         j_s.d   [%blink]
       a: ce 20 e2 07   rsub.ne %r0, %r0, 31

but now we have:

00000000 <f>:
       0: 2f 28 13 80   fls.f   %r0, %r0
       4: ca 20 21 08   mov.eq  %r0, 32
       8: e0 7f         j_s.d   [%blink]
       a: ce 20 e2 07   rsub.ne %r0, %r0, 31

[marksl]

Your changes look good to me

llvm/lib/Target/ARC/ARCInstrInfo.td

 
 multiclass ArcBinaryGEN4Inst<bits<6> mincode, string opasm, bit Commutable = 0> :
   ArcBinaryInst<0b00100, mincode, opasm, Commutable>;
 multiclass ArcBinaryEXT5Inst<bits<6> mincode, string opasm> :
   ArcBinaryInst<0b00101, mincode, opasm, 0>;
 
 multiclass ArcUnaryGEN4Inst<bits<6> mincode, string opasm> :
   ArcUnaryInst<0b00100, mincode, opasm>;
+multiclass ArcUnaryEXT5Inst<bits<6> mincode, string opasm> :
+  ArcUnaryInst<0b00101, mincode, opasm>;
 
 // Pattern generation for different instruction variants.
 multiclass MultiPat<SDPatternOperator InFrag,
                Instruction RRR, Instruction RRU6, Instruction RRLImm> {
   def _rrr : Pat<(InFrag i32:$B, i32:$C), (RRR i32:$B, i32:$C)>;
   def _rru6 : Pat<(InFrag i32:$B, immU6:$U6), (RRU6 i32:$B, immU6:$U6)>;
   def _rrlimm : Pat<(InFrag i32:$B, imm32:$LImm), (RRLImm i32:$B, imm32:$LImm)>;
 }

 
 // ---------------------------------------------------------------------------
 // Unary Instruction definitions.
 // ---------------------------------------------------------------------------
 // General unary instruction definitions.
 defm SEXB : ArcUnaryGEN4Inst<0b000101, "sexb">;
 defm SEXH : ArcUnaryGEN4Inst<0b000110, "sexh">;
 
+// Extension unary instruction definitions.
+defm FLS : ArcUnaryEXT5Inst<0b010011, "fls">;
+
 // General Unary Instruction fragments.
 def : Pat<(sext_inreg i32:$a, i8), (SEXB_rr i32:$a)>;
 def : Pat<(sext_inreg i32:$a, i16), (SEXH_rr i32:$a)>;
 
 // Comparison instruction definition
 let isCompare = 1, Defs = [STATUS32] in {
 defm CMP : ArcSpecialDOPInst<0b001100, "cmp", 1>;
 }

llvm/test/MC/Disassembler/ARC/misc.txt

 # CHECK: seteq %r3, %fp, %r1
 0x38 0x23 0x43 0x30
 
 # CHECK: seteq %r3, %fp, 17
 0x78 0x23 0x43 0x34
 
 # CHECK: seteq %fp, %fp, -1
 0xb8 0x23 0xff 0x3f 
+
+# CHECK: fls %r0, %r0
+0x2f 0x28 0x13 0x00
+
+# CHECK: fls.f %r0, %r0
+0x2f 0x28 0x13 0x80