Tablegen: Extend target register information by giving the users access to call preserved register mask names.

[arphaman]

Summary

This commit extends the TargetRegisterInfo class and TableGen so that the users of TRI can get the list of all the call preserved register masks and a list of names that correspond to each mask.

This patch is useful for MIR Serialization, as it would enable serialization of register mask machine operands.

[arphaman]

This is what tablegen would produce for the X86 TRI:

ArrayRef<const uint32_t *> X86GenRegisterInfo::getRegMasks() const {
  static const uint32_t *Masks[] = {
    CSR_32_RegMask, 
    CSR_32EHRet_RegMask, 
    CSR_64_RegMask, 
    CSR_64EHRet_RegMask, 
    CSR_64_AllRegs_RegMask, 
    CSR_64_AllRegs_AVX_RegMask, 
    CSR_64_Intel_OCL_BI_RegMask, 
    CSR_64_Intel_OCL_BI_AVX_RegMask, 
    CSR_64_Intel_OCL_BI_AVX512_RegMask, 
    CSR_64_MostRegs_RegMask, 
    CSR_64_RT_AllRegs_RegMask, 
    CSR_64_RT_AllRegs_AVX_RegMask, 
    CSR_64_RT_MostRegs_RegMask, 
    CSR_NoRegs_RegMask, 
    CSR_Win64_RegMask, 
    CSR_Win64_Intel_OCL_BI_AVX_RegMask, 
    CSR_Win64_Intel_OCL_BI_AVX512_RegMask, 
    nullptr
  };
  return ArrayRef<const uint32_t *>(Masks, (size_t)17);
}

ArrayRef<const char *> X86GenRegisterInfo::getRegMaskNames() const {
  static const char *Names[] = {
    "CSR_32",
    "CSR_32EHRet",
    "CSR_64",
    "CSR_64EHRet",
    "CSR_64_AllRegs",
    "CSR_64_AllRegs_AVX",
    "CSR_64_Intel_OCL_BI",
    "CSR_64_Intel_OCL_BI_AVX",
    "CSR_64_Intel_OCL_BI_AVX512",
    "CSR_64_MostRegs",
    "CSR_64_RT_AllRegs",
    "CSR_64_RT_AllRegs_AVX",
    "CSR_64_RT_MostRegs",
    "CSR_NoRegs",
    "CSR_Win64",
    "CSR_Win64_Intel_OCL_BI_AVX",
    "CSR_Win64_Intel_OCL_BI_AVX512",
    nullptr
  };
  return ArrayRef<const char *>(Names, (size_t)17);
}

[ab]

include/llvm/Target/TargetRegisterInfo.h

473

ArrayRef already implies 'const', no?

[arphaman]

This patch got squashed with D10673.

include/llvm/Target/TargetRegisterInfo.h

public:
   /// registers.
   ///
   virtual const uint32_t *getCallPreservedMask(const MachineFunction &MF,
                                                CallingConv::ID) const {
     // The default mask clobbers everything.  All targets should override.
     return nullptr;
   }
 
+  /// Return all the call-preserved register masks defined for this target.
+  virtual ArrayRef<const uint32_t *> getRegMasks() const = 0;
+  virtual ArrayRef<const char *> getRegMaskNames() const = 0;
+
   /// getReservedRegs - Returns a bitset indexed by physical register number
   /// indicating if a register is a special register that has particular uses
   /// and should be considered unavailable at all times, e.g. SP, RA. This is
   /// used by register scavenger to determine what registers are free.
   virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
 
   /// Prior to adding the live-out mask to a stackmap or patchpoint
   /// instruction, provide the target the opportunity to adjust it (mainly to

utils/TableGen/RegisterInfoEmitter.cpp

      << "  unsigned getNumRegPressureSets() const override;\n"
      << "  const char *getRegPressureSetName(unsigned Idx) const override;\n"
      << "  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned "
         "Idx) const override;\n"
      << "  const int *getRegClassPressureSets("
      << "const TargetRegisterClass *RC) const override;\n"
      << "  const int *getRegUnitPressureSets("
      << "unsigned RegUnit) const override;\n"
+     << "  ArrayRef<const char *> getRegMaskNames() const override;\n"
+     << "  ArrayRef<const uint32_t *> getRegMasks() const override;\n"
      << "};\n\n";
 
   const auto &RegisterClasses = RegBank.getRegClasses();
 
   if (!RegisterClasses.empty()) {
     OS << "namespace " << RegisterClasses.front().Namespace
        << " { // Register classes\n";
 

 
     OS << "static const uint32_t " << CSRSet->getName()
        << "_RegMask[] = { ";
     printBitVectorAsHex(OS, Covered, 32);
     OS << "};\n";
   }
   OS << "\n\n";
 
+  OS << "ArrayRef<const uint32_t *> " << ClassName
+     << "::getRegMasks() const {\n";
+  OS << "  static const uint32_t *Masks[] = {\n";
+  for (Record *CSRSet : CSRSets)
+    OS << "    " << CSRSet->getName() << "_RegMask, \n";
+  OS << "    nullptr\n  };\n";
+  OS << "  return ArrayRef<const uint32_t *>(Masks, (size_t)" << CSRSets.size()
+     << ");\n";
+  OS << "}\n\n";
+
+  OS << "ArrayRef<const char *> " << ClassName
+     << "::getRegMaskNames() const {\n";
+  OS << "  static const char *Names[] = {\n";
+  for (Record *CSRSet : CSRSets)
+    OS << "    " << '"' << CSRSet->getName() << '"' << ",\n";
+  OS << "    nullptr\n  };\n";
+  OS << "  return ArrayRef<const char *>(Names, (size_t)" << CSRSets.size()
+     << ");\n";
+  OS << "}\n\n";
+
   OS << "} // End llvm namespace\n";
   OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
 }
 
 void RegisterInfoEmitter::run(raw_ostream &OS) {
   CodeGenTarget Target(Records);
   CodeGenRegBank &RegBank = Target.getRegBank();
   RegBank.computeDerivedInfo();