MIR Serialization: Serialize MBB operands.

[arphaman]

Summary

This patch is based on a previous serialization patch that serializes null register operands (http://reviews.llvm.org/D10580).

This patch serializes machine basic block operands.
The following syntax is used for basic block operands:

%bb.<name>
%bb.<index>

The name is printed when the machine basic block has a name, i.e. when its basic block has a name. Otherwise, a number is printed, which is just an index into a list of machine basic blocks for that function.
Example:

JG_1 %bb.if.cond
JG_1 %bb.2

[arphaman]

Updated the MBB operand syntax based on Duncan's comments:

The YAML mapping for MBBs now includes a required number field. This number is used when referencing MBBs from machine instructions.

The syntax for basic block operands is now:

%bb.<number>[.<name>]

The name is purely optional, it's not used for MBB resolution. However, the parser still verifies that the name matches the name of the MBB with the given number.

Examples:

body:
   - number: 0
      name: entry
      instructions:
         ...
         - 'JG_1 %bb.2.exit'

 body:
    - number: 0
       instructions:
          ...
          - 'JG_1 %bb.3'
     - number: 1
       instructions:
          ...
     - number: 3
       instructions:
          ...

llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h

 } // end namespace llvm
 
 LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::StringValue)
 
 namespace llvm {
 namespace yaml {
 
 struct MachineBasicBlock {
+  unsigned ID;
   std::string Name;
   unsigned Alignment = 0;
   bool IsLandingPad = false;
   bool AddressTaken = false;
   // TODO: Serialize the successors and liveins.
 
   std::vector<StringValue> Instructions;
 };
 
 template <> struct MappingTraits<MachineBasicBlock> {
   static void mapping(IO &YamlIO, MachineBasicBlock &MBB) {
+    YamlIO.mapRequired("id", MBB.ID);
     YamlIO.mapOptional("name", MBB.Name,
                        std::string()); // Don't print out an empty name.
     YamlIO.mapOptional("alignment", MBB.Alignment);
     YamlIO.mapOptional("isLandingPad", MBB.IsLandingPad);
     YamlIO.mapOptional("addressTaken", MBB.AddressTaken);
     YamlIO.mapOptional("instructions", MBB.Instructions);
   }
 };

llvm/trunk/lib/CodeGen/MIRParser/MILexer.h

enum TokenKind {
     // Tokens with no info.
     comma,
     equal,
     underscore,
 
     // Identifier tokens
     Identifier,
     NamedRegister,
+    MachineBasicBlock,
 
     // Other tokens
     IntegerLiteral
   };
 
 private:
   TokenKind Kind;
+  unsigned StringOffset;
   StringRef Range;
   APSInt IntVal;
 
 public:
-  MIToken(TokenKind Kind, StringRef Range) : Kind(Kind), Range(Range) {}
+  MIToken(TokenKind Kind, StringRef Range, unsigned StringOffset = 0)
+      : Kind(Kind), StringOffset(StringOffset), Range(Range) {}
 
-  MIToken(TokenKind Kind, StringRef Range, const APSInt &IntVal)
-      : Kind(Kind), Range(Range), IntVal(IntVal) {}
+  MIToken(TokenKind Kind, StringRef Range, const APSInt &IntVal,
+          unsigned StringOffset = 0)
+      : Kind(Kind), StringOffset(StringOffset), Range(Range), IntVal(IntVal) {}
 
   TokenKind kind() const { return Kind; }
 
   bool isError() const { return Kind == Error; }
 
   bool isRegister() const {
     return Kind == NamedRegister || Kind == underscore;
   }
 
   bool is(TokenKind K) const { return Kind == K; }
 
   bool isNot(TokenKind K) const { return Kind != K; }
 
   StringRef::iterator location() const { return Range.begin(); }
 
-  StringRef stringValue() const { return Range; }
+  StringRef stringValue() const { return Range.drop_front(StringOffset); }
 
   const APSInt &integerValue() const { return IntVal; }
+
+  bool hasIntegerValue() const {
+    return Kind == IntegerLiteral || Kind == MachineBasicBlock;
+  }
 };
 
 /// Consume a single machine instruction token in the given source and return
 /// the remaining source string.
 StringRef lexMIToken(
     StringRef Source, MIToken &Token,
     function_ref<void(StringRef::iterator, const Twine &)> ErrorCallback);
 
 } // end namespace llvm
 
 #endif

llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp

explicit Cursor(StringRef Str) {
     Ptr = Str.data();
     End = Ptr + Str.size();
   }
 
   bool isEOF() const { return Ptr == End; }
 
   char peek(int I = 0) const { return End - Ptr <= I ? 0 : Ptr[I]; }
 
-  void advance() { ++Ptr; }
+  void advance(unsigned I = 1) { Ptr += I; }
 
   StringRef remaining() const { return StringRef(Ptr, End - Ptr); }
 
   StringRef upto(Cursor C) const {
     assert(C.Ptr >= Ptr && C.Ptr <= End);
     return StringRef(Ptr, C.Ptr - Ptr);
   }
 
static Cursor lexIdentifier(Cursor C, MIToken &Token) {
   while (isIdentifierChar(C.peek()))
     C.advance();
   auto Identifier = Range.upto(C);
   Token = MIToken(Identifier == "_" ? MIToken::underscore : MIToken::Identifier,
                   Identifier);
   return C;
 }
 
+static Cursor lexMachineBasicBlock(
+    Cursor C, MIToken &Token,
+    function_ref<void(StringRef::iterator Loc, const Twine &)> ErrorCallback) {
+  auto Range = C;
+  C.advance(4); // Skip '%bb.'
+  if (!isdigit(C.peek())) {
+    Token = MIToken(MIToken::Error, C.remaining());
+    ErrorCallback(C.location(), "expected a number after '%bb.'");
+    return C;
+  }
+  auto NumberRange = C;
+  while (isdigit(C.peek()))
+    C.advance();
+  StringRef Number = NumberRange.upto(C);
+  unsigned StringOffset = 4 + Number.size(); // Drop '%bb.<id>'
+  if (C.peek() == '.') {
+    C.advance(); // Skip '.'
+    ++StringOffset;
+    while (isIdentifierChar(C.peek()))
+      C.advance();
+  }
+  Token = MIToken(MIToken::MachineBasicBlock, Range.upto(C), APSInt(Number),
+                  StringOffset);
+  return C;
+}
+
 static Cursor lexPercent(Cursor C, MIToken &Token) {
   auto Range = C;
   C.advance(); // Skip '%'
   while (isIdentifierChar(C.peek()))
     C.advance();
-  Token = MIToken(MIToken::NamedRegister, Range.upto(C));
+  Token = MIToken(MIToken::NamedRegister, Range.upto(C),
+                  /*StringOffset=*/1); // Drop the '%'
   return C;
 }
 
 static Cursor lexIntegerLiteral(Cursor C, MIToken &Token) {
   auto Range = C;
   C.advance();
   while (isdigit(C.peek()))
     C.advance();
StringRef llvm::lexMIToken(
   if (C.isEOF()) {
     Token = MIToken(MIToken::Eof, C.remaining());
     return C.remaining();
   }
 
   auto Char = C.peek();
   if (isalpha(Char) || Char == '_')
     return lexIdentifier(C, Token).remaining();
-  if (Char == '%')
+  if (Char == '%') {
+    if (C.remaining().startswith("%bb."))
+      return lexMachineBasicBlock(C, Token, ErrorCallback).remaining();
     return lexPercent(C, Token).remaining();
+  }
   if (isdigit(Char) || (Char == '-' && isdigit(C.peek(1))))
     return lexIntegerLiteral(C, Token).remaining();
   MIToken::TokenKind Kind = symbolToken(Char);
   if (Kind != MIToken::Error)
     return lexSymbol(C, Kind, Token).remaining();
   Token = MIToken(MIToken::Error, C.remaining());
   ErrorCallback(C.location(),
                 Twine("unexpected character '") + Twine(Char) + "'");
   return C.remaining();
 }

llvm/trunk/lib/CodeGen/MIRParser/MIParser.h

 //===- MIParser.h - Machine Instructions Parser ---------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file declares the function that parses the machine instructions.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_CODEGEN_MIRPARSER_MIPARSER_H
 #define LLVM_LIB_CODEGEN_MIRPARSER_MIPARSER_H
 
+#include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/StringRef.h"
 
 namespace llvm {
 
+class MachineBasicBlock;
 class MachineInstr;
 class MachineFunction;
 class SMDiagnostic;
 class SourceMgr;
 
-MachineInstr *parseMachineInstr(SourceMgr &SM, MachineFunction &MF,
-                                StringRef Src, SMDiagnostic &Error);
+MachineInstr *
+parseMachineInstr(SourceMgr &SM, MachineFunction &MF, StringRef Src,
+                  const DenseMap<unsigned, MachineBasicBlock *> &MBBSlots,
+                  SMDiagnostic &Error);
 
 } // end namespace llvm
 
 #endif

llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp

 namespace {
 
 class MIParser {
   SourceMgr &SM;
   MachineFunction &MF;
   SMDiagnostic &Error;
   StringRef Source, CurrentSource;
   MIToken Token;
+  /// Maps from basic block numbers to MBBs.
+  const DenseMap<unsigned, MachineBasicBlock *> &MBBSlots;
   /// Maps from instruction names to op codes.
   StringMap<unsigned> Names2InstrOpCodes;
   /// Maps from register names to registers.
   StringMap<unsigned> Names2Regs;
 
 public:
   MIParser(SourceMgr &SM, MachineFunction &MF, SMDiagnostic &Error,
-           StringRef Source);
+           StringRef Source,
+           const DenseMap<unsigned, MachineBasicBlock *> &MBBSlots);
 
   void lex();
 
   /// Report an error at the current location with the given message.
   ///
   /// This function always return true.
   bool error(const Twine &Msg);
 
   /// Report an error at the given location with the given message.
   ///
   /// This function always return true.
   bool error(StringRef::iterator Loc, const Twine &Msg);
 
   MachineInstr *parse();
 
   bool parseRegister(unsigned &Reg);
   bool parseRegisterOperand(MachineOperand &Dest, bool IsDef = false);
   bool parseImmediateOperand(MachineOperand &Dest);
+  bool parseMBBOperand(MachineOperand &Dest);
   bool parseMachineOperand(MachineOperand &Dest);
 
 private:
+  /// Convert the integer literal in the current token into an unsigned integer.
+  ///
+  /// Return true if an error occurred.
+  bool getUnsigned(unsigned &Result);
+
   void initNames2InstrOpCodes();
 
   /// Try to convert an instruction name to an opcode. Return true if the
   /// instruction name is invalid.
   bool parseInstrName(StringRef InstrName, unsigned &OpCode);
 
   bool parseInstruction(unsigned &OpCode);
 
   void initNames2Regs();
 
   /// Try to convert a register name to a register number. Return true if the
   /// register name is invalid.
   bool getRegisterByName(StringRef RegName, unsigned &Reg);
 };
 
 } // end anonymous namespace
 
 MIParser::MIParser(SourceMgr &SM, MachineFunction &MF, SMDiagnostic &Error,
-                   StringRef Source)
+                   StringRef Source,
+                   const DenseMap<unsigned, MachineBasicBlock *> &MBBSlots)
     : SM(SM), MF(MF), Error(Error), Source(Source), CurrentSource(Source),
-      Token(MIToken::Error, StringRef()) {}
+      Token(MIToken::Error, StringRef()), MBBSlots(MBBSlots) {}
 
 void MIParser::lex() {
   CurrentSource = lexMIToken(
       CurrentSource, Token,
       [this](StringRef::iterator Loc, const Twine &Msg) { error(Loc, Msg); });
 }
 
 bool MIParser::error(const Twine &Msg) { return error(Token.location(), Msg); }

 }
 
 bool MIParser::parseRegister(unsigned &Reg) {
   switch (Token.kind()) {
   case MIToken::underscore:
     Reg = 0;
     break;
   case MIToken::NamedRegister: {
-    StringRef Name = Token.stringValue().drop_front(1); // Drop the '%'
+    StringRef Name = Token.stringValue();
     if (getRegisterByName(Name, Reg))
       return error(Twine("unknown register name '") + Name + "'");
     break;
   }
   // TODO: Parse other register kinds.
   default:
     llvm_unreachable("The current token should be a register");
   }
bool MIParser::parseImmediateOperand(MachineOperand &Dest) {
   if (Int.getMinSignedBits() > 64)
     // TODO: Replace this with an error when we can parse CIMM Machine Operands.
     llvm_unreachable("Can't parse large integer literals yet!");
   Dest = MachineOperand::CreateImm(Int.getExtValue());
   lex();
   return false;
 }
 
+bool MIParser::getUnsigned(unsigned &Result) {
+  assert(Token.hasIntegerValue() && "Expected a token with an integer value");
+  const uint64_t Limit = uint64_t(std::numeric_limits<unsigned>::max()) + 1;
+  uint64_t Val64 = Token.integerValue().getLimitedValue(Limit);
+  if (Val64 == Limit)
+    return error("expected 32-bit integer (too large)");
+  Result = Val64;
+  return false;
+}
+
+bool MIParser::parseMBBOperand(MachineOperand &Dest) {
+  assert(Token.is(MIToken::MachineBasicBlock));
+  unsigned Number;
+  if (getUnsigned(Number))
+    return true;
+  auto MBBInfo = MBBSlots.find(Number);
+  if (MBBInfo == MBBSlots.end())
+    return error(Twine("use of undefined machine basic block #") +
+                 Twine(Number));
+  MachineBasicBlock *MBB = MBBInfo->second;
+  if (!Token.stringValue().empty() && Token.stringValue() != MBB->getName())
+    return error(Twine("the name of machine basic block #") + Twine(Number) +
+                 " isn't '" + Token.stringValue() + "'");
+  Dest = MachineOperand::CreateMBB(MBB);
+  lex();
+  return false;
+}
+
 bool MIParser::parseMachineOperand(MachineOperand &Dest) {
   switch (Token.kind()) {
   case MIToken::underscore:
   case MIToken::NamedRegister:
     return parseRegisterOperand(Dest);
   case MIToken::IntegerLiteral:
     return parseImmediateOperand(Dest);
+  case MIToken::MachineBasicBlock:
+    return parseMBBOperand(Dest);
   case MIToken::Error:
     return true;
   default:
     // TODO: parse the other machine operands.
     return error("expected a machine operand");
   }
   return false;
 }
bool MIParser::getRegisterByName(StringRef RegName, unsigned &Reg) {
   initNames2Regs();
   auto RegInfo = Names2Regs.find(RegName);
   if (RegInfo == Names2Regs.end())
     return true;
   Reg = RegInfo->getValue();
   return false;
 }
 
-MachineInstr *llvm::parseMachineInstr(SourceMgr &SM, MachineFunction &MF,
-                                      StringRef Src, SMDiagnostic &Error) {
-  return MIParser(SM, MF, Error, Src).parse();
+MachineInstr *
+llvm::parseMachineInstr(SourceMgr &SM, MachineFunction &MF, StringRef Src,
+                        const DenseMap<unsigned, MachineBasicBlock *> &MBBSlots,
+                        SMDiagnostic &Error) {
+  return MIParser(SM, MF, Error, Src, MBBSlots).parse();
 }

llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp

 //===- MIRParser.cpp - MIR serialization format parser implementation -----===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the class that parses the optional LLVM IR and machine
 // functions that are stored in MIR files.
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/CodeGen/MIRParser/MIRParser.h"
 #include "MIParser.h"
+#include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/StringMap.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/AsmParser/Parser.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/MIRYamlMapping.h"
 #include "llvm/IR/BasicBlock.h"
public:
   /// file.
   ///
   /// Return true if error occurred.
   bool initializeMachineFunction(MachineFunction &MF);
 
   /// Initialize the machine basic block using it's YAML representation.
   ///
   /// Return true if an error occurred.
-  bool initializeMachineBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB,
-                                   const yaml::MachineBasicBlock &YamlMBB);
+  bool initializeMachineBasicBlock(
+      MachineFunction &MF, MachineBasicBlock &MBB,
+      const yaml::MachineBasicBlock &YamlMBB,
+      const DenseMap<unsigned, MachineBasicBlock *> &MBBSlots);
 
   bool initializeRegisterInfo(MachineRegisterInfo &RegInfo,
                               const yaml::MachineFunction &YamlMF);
 
 private:
   /// Return a MIR diagnostic converted from an MI string diagnostic.
   SMDiagnostic diagFromMIStringDiag(const SMDiagnostic &Error,
                                     SMRange SourceRange);
bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) {
   if (YamlMF.Alignment)
     MF.setAlignment(YamlMF.Alignment);
   MF.setExposesReturnsTwice(YamlMF.ExposesReturnsTwice);
   MF.setHasInlineAsm(YamlMF.HasInlineAsm);
   if (initializeRegisterInfo(MF.getRegInfo(), YamlMF))
     return true;
 
   const auto &F = *MF.getFunction();
+  DenseMap<unsigned, MachineBasicBlock *> MBBSlots;
   for (const auto &YamlMBB : YamlMF.BasicBlocks) {
     const BasicBlock *BB = nullptr;
     if (!YamlMBB.Name.empty()) {
       BB = dyn_cast_or_null<BasicBlock>(
           F.getValueSymbolTable().lookup(YamlMBB.Name));
       if (!BB)
         return error(Twine("basic block '") + YamlMBB.Name +
                      "' is not defined in the function '" + MF.getName() + "'");
     }
     auto *MBB = MF.CreateMachineBasicBlock(BB);
     MF.insert(MF.end(), MBB);
-    if (initializeMachineBasicBlock(MF, *MBB, YamlMBB))
+    bool WasInserted = MBBSlots.insert(std::make_pair(YamlMBB.ID, MBB)).second;
+    if (!WasInserted)
+      return error(Twine("redefinition of machine basic block with id #") +
+                   Twine(YamlMBB.ID));
+  }
+
+  // Initialize the machine basic blocks after creating them all so that the
+  // machine instructions parser can resolve the MBB references.
+  unsigned I = 0;
+  for (const auto &YamlMBB : YamlMF.BasicBlocks) {
+    if (initializeMachineBasicBlock(MF, *MF.getBlockNumbered(I++), YamlMBB,
+                                    MBBSlots))
       return true;
   }
   return false;
 }
 
 bool MIRParserImpl::initializeMachineBasicBlock(
     MachineFunction &MF, MachineBasicBlock &MBB,
-    const yaml::MachineBasicBlock &YamlMBB) {
+    const yaml::MachineBasicBlock &YamlMBB,
+    const DenseMap<unsigned, MachineBasicBlock *> &MBBSlots) {
   MBB.setAlignment(YamlMBB.Alignment);
   if (YamlMBB.AddressTaken)
     MBB.setHasAddressTaken();
   MBB.setIsLandingPad(YamlMBB.IsLandingPad);
   // Parse the instructions.
   for (const auto &MISource : YamlMBB.Instructions) {
     SMDiagnostic Error;
-    if (auto *MI = parseMachineInstr(SM, MF, MISource.Value, Error)) {
+    if (auto *MI = parseMachineInstr(SM, MF, MISource.Value, MBBSlots, Error)) {
       MBB.insert(MBB.end(), MI);
       continue;
     }
     reportDiagnostic(diagFromMIStringDiag(Error, MISource.SourceRange));
     return true;
   }
   return false;
 }

llvm/trunk/lib/CodeGen/MIRPrinter.cpp

 
 void MIRPrinter::print(const MachineFunction &MF) {
   yaml::MachineFunction YamlMF;
   YamlMF.Name = MF.getName();
   YamlMF.Alignment = MF.getAlignment();
   YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
   YamlMF.HasInlineAsm = MF.hasInlineAsm();
   convert(YamlMF, MF.getRegInfo());
+
+  int I = 0;
   for (const auto &MBB : MF) {
+    // TODO: Allow printing of non sequentially numbered MBBs.
+    // This is currently needed as the basic block references get their index
+    // from MBB.getNumber(), thus it should be sequential so that the parser can
+    // map back to the correct MBBs when parsing the output.
+    assert(MBB.getNumber() == I++ &&
+           "Can't print MBBs that aren't sequentially numbered");
     yaml::MachineBasicBlock YamlMBB;
     convert(YamlMBB, MBB);
     YamlMF.BasicBlocks.push_back(YamlMBB);
   }
   yaml::Output Out(OS);
   Out << YamlMF;
 }
 
 void MIRPrinter::convert(yaml::MachineFunction &MF,
                          const MachineRegisterInfo &RegInfo) {
   MF.IsSSA = RegInfo.isSSA();
   MF.TracksRegLiveness = RegInfo.tracksLiveness();
   MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
 }
 
 void MIRPrinter::convert(yaml::MachineBasicBlock &YamlMBB,
                          const MachineBasicBlock &MBB) {
+  assert(MBB.getNumber() >= 0 && "Invalid MBB number");
+  YamlMBB.ID = (unsigned)MBB.getNumber();
   // TODO: Serialize unnamed BB references.
   if (const auto *BB = MBB.getBasicBlock())
     YamlMBB.Name = BB->hasName() ? BB->getName() : "<unnamed bb>";
   else
     YamlMBB.Name = "";
   YamlMBB.Alignment = MBB.getAlignment();
   YamlMBB.AddressTaken = MBB.hasAddressTaken();
   YamlMBB.IsLandingPad = MBB.isLandingPad();
void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) {
   case MachineOperand::MO_Register:
     // TODO: Print register flags.
     printReg(Op.getReg(), OS, TRI);
     // TODO: Print sub register.
     break;
   case MachineOperand::MO_Immediate:
     OS << Op.getImm();
     break;
+  case MachineOperand::MO_MachineBasicBlock:
+    OS << "%bb." << Op.getMBB()->getNumber();
+    if (const auto *BB = Op.getMBB()->getBasicBlock()) {
+      if (BB->hasName())
+        OS << '.' << BB->getName();
+    }
+    break;
   default:
     // TODO: Print the other machine operands.
     llvm_unreachable("Can't print this machine operand at the moment");
   }
 }
 
 void llvm::printMIR(raw_ostream &OS, const Module &M) {
   yaml::Output Out(OS);
   Out << const_cast<Module &>(M);
 }
 
 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
   MIRPrinter Printer(OS);
   Printer.print(MF);
 }

llvm/trunk/test/CodeGen/MIR/X86/expected-machine-operand.mir

 # RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
 
 --- |
 
   define i32 @foo() {
   entry:
     ret i32 0
   }
 
 ...
 ---
 name:            foo
 body:
- - name:         entry
+ - id:           0
+   name:         entry
    instructions:
      # CHECK: [[@LINE+1]]:24: expected a machine operand
      - '%eax = XOR32rr ='
      - 'RETQ %eax'
 ...
 

llvm/trunk/test/CodeGen/MIR/X86/expected-number-after-bb.mir

+# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
+
+--- |
+
+  define i32 @foo(i32* %p) {
+  entry:
+    %a = load i32, i32* %p
+    %b = icmp sle i32 %a, 10
+    br i1 %b, label %yes, label %nah
+
+  yes:
+    ret i32 0
+
+  nah:
+    ret i32 %a
+  }
+
+...
+---
+name:            foo
+body:
+ - id: 0
+   name:   entry
+   instructions:
+     - '%eax = MOV32rm %rdi, 1, _, 0, _'
+     - 'CMP32ri8 %eax, 10'
+     # CHECK: [[@LINE+1]]:18: expected a number after '%bb.'
+     - 'JG_1 %bb.nah'
+ - id: 1
+   name: yes
+   instructions:
+     - '%eax = MOV32r0'
+ - id: 2
+   name: nah
+   instructions:
+     - 'RETQ %eax'
+...

llvm/trunk/test/CodeGen/MIR/X86/immediate-operands.mir

entry:
     ret i32 -11
   }
 
 ...
 ---
 # CHECK: name: foo
 name:            foo
 body:
- - name:         entry
+ - id:           0
+   name:         entry
    instructions:
      # CHECK:      - '%eax = MOV32ri 42'
      # CHECK-NEXT: - 'RETQ %eax'
      - '%eax = MOV32ri 42'
      - 'RETQ %eax'
 ...
 ---
 # CHECK: name: bar
 name:            bar
 body:
- - name:         entry
+ - id:           0
+   name:         entry
    instructions:
      # CHECK:      - '%eax = MOV32ri -11'
      # CHECK-NEXT: - 'RETQ %eax'
      - '%eax = MOV32ri -11'
      - 'RETQ %eax'
 ...

llvm/trunk/test/CodeGen/MIR/X86/large-index-number-error.mir

+# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
+
+--- |
+
+  define i32 @foo(i32* %p) {
+  entry:
+    %a = load i32, i32* %p
+    %b = icmp sle i32 %a, 10
+    br i1 %b, label %0, label %1
+
+  ; <label>:0
+    ret i32 0
+
+  ; <label>:1
+    ret i32 %a
+  }
+
+...
+---
+name:            foo
+body:
+ - id: 0
+   name: entry
+   instructions:
+     - '%eax = MOV32rm %rdi, 1, _, 0, _'
+     - 'CMP32ri8 %eax, 10'
+     # CHECK: [[@LINE+1]]:14: expected 32-bit integer (too large)
+     - 'JG_1 %bb.123456789123456'
+ - id: 1
+   instructions:
+     - '%eax = MOV32r0'
+ - id: 2
+   instructions:
+     - 'RETQ %eax'
+...

llvm/trunk/test/CodeGen/MIR/X86/machine-basic-block-operands.mir

+# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s
+# This test ensures that the MIR parser parses machine basic block operands.
+
+--- |
+
+  define i32 @foo(i32* %p) {
+  entry:
+    %a = load i32, i32* %p
+    %0 = icmp sle i32 %a, 10
+    br i1 %0, label %less, label %exit
+
+  less:
+    ret i32 0
+
+  exit:
+    ret i32 %a
+  }
+
+  define i32 @bar(i32* %p) {
+  entry:
+    %a = load i32, i32* %p
+    %b = icmp sle i32 %a, 10
+    br i1 %b, label %0, label %1
+
+  ; <label>:0
+    ret i32 0
+
+  ; <label>:1
+    ret i32 %a
+  }
+
+...
+---
+# CHECK: name: foo
+name:            foo
+body:
+ # CHECK: name: entry
+ - id:              0
+   name:            entry
+   instructions:
+     - '%eax = MOV32rm %rdi, 1, _, 0, _'
+     # CHECK:      - 'CMP32ri8 %eax, 10
+     # CHECK-NEXT: - 'JG_1 %bb.2.exit
+     - 'CMP32ri8 %eax, 10'
+     - 'JG_1 %bb.2.exit'
+ # CHECK: name: less
+ - id:              1
+   name:            less
+   instructions:
+     - '%eax = MOV32r0'
+ - id:              2
+   name:            exit
+   instructions:
+     - 'RETQ %eax'
+...
+---
+# CHECK: name: bar
+name:            bar
+body:
+ # CHECK: name: entry
+ - id: 0
+   name: entry
+   instructions:
+     - '%eax = MOV32rm %rdi, 1, _, 0, _'
+     # CHECK:      - 'CMP32ri8 %eax, 10
+     # CHECK-NEXT: - 'JG_1 %bb.2
+     - 'CMP32ri8 %eax, 10'
+     - 'JG_1 %bb.3'
+ - id: 1
+   instructions:
+     - '%eax = MOV32r0'
+ - id: 3
+   instructions:
+     - 'RETQ %eax'
+...

llvm/trunk/test/CodeGen/MIR/X86/machine-instructions.mir

entry:
     ret i32 %b
   }
 
 ...
 ---
 # CHECK: name: inc
 name:            inc
 body:
- - name:         entry
+ - id:           0
+   name:         entry
    instructions:
      # CHECK:      - IMUL32rri8
      # CHECK-NEXT: - RETQ
      - IMUL32rri8
      - ' RETQ '
 ...

llvm/trunk/test/CodeGen/MIR/X86/missing-comma.mir

 # RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
 
 --- |
 
   define i32 @foo() {
   entry:
     ret i32 0
   }
 
 ...
 ---
 name:            foo
 body:
- - name:         entry
+ - id:           0
+   name:         entry
    instructions:
      # CHECK: [[@LINE+1]]:29: expected ',' before the next machine operand
      - '%eax = XOR32rr %eax %eflags'
      - 'RETQ %eax'
 ...
 

llvm/trunk/test/CodeGen/MIR/X86/missing-instruction.mir

 # RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
 
 --- |
 
   define void @foo() {
   entry:
     ret void
   }
 
 ...
 ---
 name:            foo
 body:
- - name:         entry
+ - id:           0
+   name:         entry
    instructions:
      # CHECK: [[@LINE+1]]:9: expected a machine instruction
      - ''
 ...

llvm/trunk/test/CodeGen/MIR/X86/named-registers.mir

 # RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s
 # This test ensures that the MIR parser parses X86 registers correctly.
 
 --- |
 
   define i32 @foo() {
   entry:
     ret i32 0
   }
 
 ...
 ---
 # CHECK: name: foo
 name:            foo
 body:
- - name:         entry
+ - id:           0
+   name:         entry
    instructions:
      # CHECK:      - '%eax = MOV32r0
      # CHECK-NEXT: - 'RETQ %eax
      - '%eax = MOV32r0'
      - 'RETQ %eax'
 ...

llvm/trunk/test/CodeGen/MIR/X86/null-register-operands.mir

 # RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s
 # This test ensures that the MIR parser parses null register operands correctly.
 
 --- |
 
   define i32 @deref(i32* %p) {
   entry:
     %a = load i32, i32* %p
     ret i32 %a
   }
 
 ...
 ---
 # CHECK: name: deref
 name:            deref
 body:
- - name:         entry
+ - id:           0
+   name:         entry
    instructions:
      # CHECK:      - '%eax = MOV32rm %rdi, 1, _, 0, _'
      # CHECK-NEXT: - 'RETQ %eax'
      - '%eax = MOV32rm %rdi, 1, _, 0, %noreg'
      - 'RETQ %eax'
 ...

llvm/trunk/test/CodeGen/MIR/X86/unknown-instruction.mir

 # RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
 # This test ensures that an error is reported when an unknown instruction is
 # encountered.
 
 --- |
 
   define i32 @foo() {
   entry:
     ret i32 0
   }
 
 ...
 ---
 name:            foo
 body:
- - name:         entry
+ - id:           0
+   name:         entry
    instructions:
      # CHECK: [[@LINE+1]]:8: unknown machine instruction name 'retJust0'
      - retJust0
 ...

llvm/trunk/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir

+# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
+# This test ensures that an error is reported when an invalid machine basic
+# block index is used.
+
+
+--- |
+
+  define i32 @foo(i32* %p) {
+  entry:
+    %a = load i32, i32* %p
+    %b = icmp sle i32 %a, 10
+    br i1 %b, label %0, label %1
+
+  ; <label>:0
+    ret i32 0
+
+  ; <label>:1
+    ret i32 %a
+  }
+
+...
+---
+name:            foo
+body:
+ - id: 0
+   name:         entry
+   instructions:
+     - '%eax = MOV32rm %rdi, 1, _, 0, _'
+     - 'CMP32ri8 %eax, 10'
+     # CHECK: [[@LINE+1]]:14: use of undefined machine basic block #4
+     - 'JG_1 %bb.4'
+ - id: 1
+   instructions:
+     - '%eax = MOV32r0'
+ - id: 2
+   instructions:
+     - 'RETQ %eax'
+...

llvm/trunk/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir

+# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
+# This test ensures that an error is reported when an unknown named machine
+# basic block is encountered.
+
+--- |
+
+  define i32 @foo(i32* %p) {
+  entry:
+    %a = load i32, i32* %p
+    %0 = icmp sle i32 %a, 10
+    br i1 %0, label %less, label %exit
+
+  less:
+    ret i32 0
+
+  exit:
+    ret i32 %a
+  }
+
+...
+---
+name:            foo
+body:
+ - id:              0
+   name:            entry
+   instructions:
+     - '%eax = MOV32rm %rdi, 1, _, 0, _'
+     - 'CMP32ri8 %eax, 10'
+     # CHECK: [[@LINE+1]]:14: the name of machine basic block #2 isn't 'hit'
+     - 'JG_1 %bb.2.hit'
+ - id:              1
+   name:            less
+   instructions:
+     - '%eax = MOV32r0'
+ - id:              2
+   name:            exit
+   instructions:
+     - 'RETQ %eax'
+...

llvm/trunk/test/CodeGen/MIR/X86/unknown-register.mir

 # RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
 # This test ensures that an error is reported when an unknown register is
 # encountered.
 
 --- |
 
   define i32 @foo() {
   entry:
     ret i32 0
   }
 
 ...
 ---
 name:            foo
 body:
- - name:         entry
+ - id:           0
+   name:         entry
    instructions:
      # CHECK: [[@LINE+1]]:9: unknown register name 'xax'
      - '%xax = MOV32r0'
      - 'RETQ %xax'
 ...

llvm/trunk/test/CodeGen/MIR/X86/unrecognized-character.mir

 # RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
 
 --- |
 
   define void @foo() {
   entry:
     ret void
   }
 
 ...
 ---
 name:            foo
 body:
- - name:         entry
+ - id:           0
+   name:         entry
    instructions:
      # CHECK: [[@LINE+1]]:9: unexpected character '`'
      - '` RETQ'
 ...

llvm/trunk/test/CodeGen/MIR/basic-blocks.mir

--- |
   start:
     ret i32 0
   }
 
 ...
 ---
 # CHECK: name: foo
 # CHECK: body:
-# CHECK-NEXT: - name: entry
+# CHECK-NEXT: - id: 0
+# CHECK-NEXT:   name: entry
 # CHECK-NEXT:   alignment: 0
 # CHECK-NEXT:   isLandingPad: false
 # CHECK-NEXT:   addressTaken: false
 name:            foo
 body:
- - name:         entry
+ - id:           0
+   name:         entry
 ...
 ---
 # CHECK: name: bar
 # CHECK: body:
-# CHECK-NEXT: - name: start
+# CHECK-NEXT: - id: 0
+# CHECK-NEXT:   name: start
 # CHECK-NEXT:   alignment: 4
 # CHECK-NEXT:   isLandingPad: false
 # CHECK-NEXT:   addressTaken: false
-# CHECK-NEXT: - alignment: 0
+# CHECK-NEXT: - id: 1
+# CHECK-NEXT:   alignment: 0
 # CHECK-NEXT:   isLandingPad: false
 # CHECK-NEXT:   addressTaken: true
 name:            bar
 body:
- - name:         start
+ - id:           0
+   name:         start
    alignment:    4
- - addressTaken: true
+ - id:           1
+   addressTaken: true
 ...

llvm/trunk/test/CodeGen/MIR/machine-basic-block-redefinition-error.mir

+# RUN: not llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
+
+--- |
+
+  define i32 @foo() {
+  entry:
+    ret i32 0
+  }
+
+...
+---
+name:            foo
+body:
+  # CHECK: redefinition of machine basic block with id #0
+  - id:       0
+  - id:       0
+...

llvm/trunk/test/CodeGen/MIR/machine-basic-block-unknown-name.mir

 # RUN: not llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
 # This test ensures that an error is reported whenever the MIR parser can't find
 # a basic block with the machine basis block's name.
 
 --- |
 
   define i32 @foo() {
   entry:
     ret i32 0
   }
 
 ...
 ---
 name:            foo
 body:
   # CHECK: basic block 'entrie' is not defined in the function 'foo'
-  - name:         entrie
+  - id:          0
+    name:        entrie
 ...