MIR Serialization: Serialize the null register operands.

[arphaman]

Summary

This patch is based on a previous serialization patch that serializes immediate operands (http://reviews.llvm.org/D10573).

This patch serializes the null register machine operands. It uses the '_' keyword to represent them, but you can also refer to them in the input source by using the '%noreg' named register syntax. Example:

• '%eax = MOV32rm %rdi, 1, _, 0, %noreg'
• 'RETQ %eax'

llvm/trunk/lib/CodeGen/MIRParser/MILexer.h

struct MIToken {
   enum TokenKind {
     // Markers
     Eof,
     Error,
 
     // Tokens with no info.
     comma,
     equal,
+    underscore,
 
     // Identifier tokens
     Identifier,
     NamedRegister,
 
     // Other tokens
     IntegerLiteral
   };
 
 private:
   TokenKind Kind;
   StringRef Range;
   APSInt IntVal;
 
 public:
   MIToken(TokenKind Kind, StringRef Range) : Kind(Kind), Range(Range) {}
 
   MIToken(TokenKind Kind, StringRef Range, const APSInt &IntVal)
       : Kind(Kind), Range(Range), IntVal(IntVal) {}
 
   TokenKind kind() const { return Kind; }
 
   bool isError() const { return Kind == Error; }
 
-  bool isRegister() const { return Kind == NamedRegister; }
+  bool isRegister() const {
+    return Kind == NamedRegister || Kind == underscore;
+  }
 
   bool is(TokenKind K) const { return Kind == K; }
 
   bool isNot(TokenKind K) const { return Kind != K; }
 
   StringRef::iterator location() const { return Range.begin(); }
 
   StringRef stringValue() const { return Range; }

llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp

 static bool isIdentifierChar(char C) {
   return isalpha(C) || isdigit(C) || C == '_' || C == '-' || C == '.';
 }
 
 static Cursor lexIdentifier(Cursor C, MIToken &Token) {
   auto Range = C;
   while (isIdentifierChar(C.peek()))
     C.advance();
-  Token = MIToken(MIToken::Identifier, Range.upto(C));
+  auto Identifier = Range.upto(C);
+  Token = MIToken(Identifier == "_" ? MIToken::underscore : MIToken::Identifier,
+                  Identifier);
   return C;
 }
 
 static Cursor lexPercent(Cursor C, MIToken &Token) {
   auto Range = C;
   C.advance(); // Skip '%'
   while (isIdentifierChar(C.peek()))
     C.advance();

llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp

bool MIParser::parseInstruction(unsigned &OpCode) {
   if (parseInstrName(InstrName, OpCode))
     return error(Twine("unknown machine instruction name '") + InstrName + "'");
   lex();
   return false;
 }
 
 bool MIParser::parseRegister(unsigned &Reg) {
   switch (Token.kind()) {
+  case MIToken::underscore:
+    Reg = 0;
+    break;
   case MIToken::NamedRegister: {
     StringRef Name = Token.stringValue().drop_front(1); // Drop the '%'
     if (getRegisterByName(Name, Reg))
       return error(Twine("unknown register name '") + Name + "'");
     break;
   }
   // TODO: Parse other register kinds.
   default:
if (Int.getMinSignedBits() > 64)
     llvm_unreachable("Can't parse large integer literals yet!");
   Dest = MachineOperand::CreateImm(Int.getExtValue());
   lex();
   return false;
 }
 
 bool MIParser::parseMachineOperand(MachineOperand &Dest) {
   switch (Token.kind()) {
+  case MIToken::underscore:
   case MIToken::NamedRegister:
     return parseRegisterOperand(Dest);
   case MIToken::IntegerLiteral:
     return parseImmediateOperand(Dest);
   case MIToken::Error:
     return true;
   default:
     // TODO: parse the other machine operands.
if (InstrInfo == Names2InstrOpCodes.end())
     return true;
   OpCode = InstrInfo->getValue();
   return false;
 }
 
 void MIParser::initNames2Regs() {
   if (!Names2Regs.empty())
     return;
+  // The '%noreg' register is the register 0.
+  Names2Regs.insert(std::make_pair("noreg", 0));
   const auto *TRI = MF.getSubtarget().getRegisterInfo();
   assert(TRI && "Expected target register info");
   for (unsigned I = 0, E = TRI->getNumRegs(); I < E; ++I) {
     bool WasInserted =
         Names2Regs.insert(std::make_pair(StringRef(TRI->getName(I)).lower(), I))
             .second;
     (void)WasInserted;
     assert(WasInserted && "Expected registers to be unique case-insensitively");

llvm/trunk/lib/CodeGen/MIRPrinter.cpp

for (; I < E; ++I) {
     print(MI.getOperand(I), TRI);
     NeedComma = true;
   }
 }
 
 static void printReg(unsigned Reg, raw_ostream &OS,
                      const TargetRegisterInfo *TRI) {
   // TODO: Print Stack Slots.
-  // TODO: Print no register.
   // TODO: Print virtual registers.
-  if (Reg < TRI->getNumRegs())
+  if (!Reg)
+    OS << '_';
+  else if (Reg < TRI->getNumRegs())
     OS << '%' << StringRef(TRI->getName(Reg)).lower();
   else
     llvm_unreachable("Can't print this kind of register yet");
 }
 
 void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) {
   switch (Op.getType()) {
   case MachineOperand::MO_Register:

llvm/trunk/test/CodeGen/MIR/X86/null-register-operands.mir

+# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s
+# This test ensures that the MIR parser parses null register operands correctly.
+
+--- |
+
+  define i32 @deref(i32* %p) {
+  entry:
+    %a = load i32, i32* %p
+    ret i32 %a
+  }
+
+...
+---
+# CHECK: name: deref
+name:            deref
+body:
+ - name:         entry
+   instructions:
+     # CHECK:      - '%eax = MOV32rm %rdi, 1, _, 0, _'
+     # CHECK-NEXT: - 'RETQ %eax'
+     - '%eax = MOV32rm %rdi, 1, _, 0, %noreg'
+     - 'RETQ %eax'
+...