[mips] Handling of immediates bigger than 16 bits

[obucina]

Summary

Handling of immediates bigger than 16 bits

[dsanders]

There's quite a few comments here but most are about fairly small issues.

Resolves https://dmz-portal.mips.com/bugz/show_bug.cgi?id=2059

It appears that it also resolves:
https://dmz-portal.mips.com/bugz/show_bug.cgi?id=923
https://dmz-portal.mips.com/bugz/show_bug.cgi?id=689

As noted on D10537, the MIPS bugzilla isn't used by the LLVM community. Generally speaking, we shouldn't reference it.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

1696–1699

I don't understand this check. All the above instructions have the form:

insn reg, reg, imm

Can you show me a case where it's false?

1701

Not quite. For ANDi, ORi, and XORi, the range will be 0 to 65535, but for ADDi, ADDiu, SLTi, SLTiu it will be -32768 to 32767.

Also, use isInt<16>(ImmValue) and isUInt<16>(ImmValue) as appropriate.

1702–1704

Nit: Don't use redundant braces or else-after-return.

2576

What if ATReg is 0 because .set noat is in effect?

2581

The 'true' seems suspicious. Am I right in assuming support for the 64-bit equivalents will be in a later patch?

2626–2630

Nit: Avoid return-after-else like so:

  ...
  Instructions.push_back(tmpInst);
  return false
}
return true;

test/MC/Mips/instalias-imm-expanding.s

31

Nit: Inconsistent indentation of the '# encoding'.

By the way, I'm thinking about removing most of these '# encoding' checks. If we've tested it properly in test/MC/Mips/*/valid.s then we don't really need to do it again. That's something for later though.

294–298

Why? You don't check for it.

[obucina]

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

1696–1699

Check test/MC/Mips/xgot.s, line 36.

2581

Yes.

[dsanders]

LGTM with the remaining nits fixed.

I also noticed a few more on this read-through

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

1693–1700

Nit: Indentation and else-after-return

1696–1699

The 'addiu $2, $2, %lo(_gp_disp)' ? Ok, that makes sense.

1702–1704

This has been marked done but the else-after-return is still there

lib/Target/Mips/MipsInstrInfo.td

1697–1698

Indentation

[obucina]

New diff contains nit fixes and changes needed to apply and properly build this fix.

[obucina]

New diff contains nit fixes and changes needed to apply and properly build this fix.

[dsanders]

LGTM. Thanks

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

#include "MipsGenAsmMatcher.inc"
 
   void expandMemInst(MCInst &Inst, SMLoc IDLoc,
                      SmallVectorImpl<MCInst> &Instructions, bool isLoad,
                      bool isImmOpnd);
 
   bool expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc,
                                SmallVectorImpl<MCInst> &Instructions);
 
+  bool expandAliasImmediate(MCInst &Inst, SMLoc IDLoc,
+                          SmallVectorImpl<MCInst> &Instructions);
+
   bool expandBranchImm(MCInst &Inst, SMLoc IDLoc,
                        SmallVectorImpl<MCInst> &Instructions);
 
   bool expandCondBranches(MCInst &Inst, SMLoc IDLoc,
                           SmallVectorImpl<MCInst> &Instructions);
 
   bool expandUlhu(MCInst &Inst, SMLoc IDLoc,
                   SmallVectorImpl<MCInst> &Instructions);
bool MipsAsmParser::needsExpansion(MCInst &Inst) {
   case Mips::BGE:
   case Mips::BGT:
   case Mips::BLTU:
   case Mips::BLEU:
   case Mips::BGEU:
   case Mips::BGTU:
   case Mips::Ulhu:
   case Mips::Ulw:
+  case Mips::NORImm:
     return true;
+  case Mips::ADDi:
+  case Mips::ADDiu:
+  case Mips::SLTi:
+  case Mips::SLTiu:
+    if ((Inst.getNumOperands() == 3) &&
+        Inst.getOperand(0).isReg() &&
+        Inst.getOperand(1).isReg() &&
+        Inst.getOperand(2).isImm()) {
+      int64_t ImmValue = Inst.getOperand(2).getImm();
+      return !isInt<16>(ImmValue);
+  } else
+      return false;
+  case Mips::ANDi:
+  case Mips::ORi:
+  case Mips::XORi:
+    if ((Inst.getNumOperands() == 3) &&
+        Inst.getOperand(0).isReg() &&
+        Inst.getOperand(1).isReg() &&
+        Inst.getOperand(2).isImm()) {
+      int64_t ImmValue = Inst.getOperand(2).getImm();
+      return !isUInt<16>(ImmValue);
+  } else
+      return false;
   default:
     return false;
   }
 }
 
 bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
                                       SmallVectorImpl<MCInst> &Instructions) {
   switch (Inst.getOpcode()) {
bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
   case Mips::BLEU:
   case Mips::BGEU:
   case Mips::BGTU:
     return expandCondBranches(Inst, IDLoc, Instructions);
   case Mips::Ulhu:
     return expandUlhu(Inst, IDLoc, Instructions);
   case Mips::Ulw:
     return expandUlw(Inst, IDLoc, Instructions);
+  case Mips::ADDi:
+  case Mips::ADDiu:
+  case Mips::ANDi:
+  case Mips::NORImm:
+  case Mips::ORi:
+  case Mips::SLTi:
+  case Mips::SLTiu:
+  case Mips::XORi:
+    return expandAliasImmediate(Inst, IDLoc, Instructions);
   }
 }
 
 namespace {
 template <unsigned ShiftAmount>
 void createLShiftOri(MCOperand Operand, unsigned RegNo, SMLoc IDLoc,
                      SmallVectorImpl<MCInst> &Instructions) {
   MCInst tmpInst;
bool MipsAsmParser::expandUlhu(MCInst &Inst, SMLoc IDLoc,
 
   const MCOperand &DstRegOp = Inst.getOperand(0);
   assert(DstRegOp.isReg() && "expected register operand kind");
 
   const MCOperand &SrcRegOp = Inst.getOperand(1);
   assert(SrcRegOp.isReg() && "expected register operand kind");
 
   const MCOperand &OffsetImmOp = Inst.getOperand(2);
   assert(OffsetImmOp.isImm() && "expected immediate operand kind");
 
   unsigned DstReg = DstRegOp.getReg();
   unsigned SrcReg = SrcRegOp.getReg();
   int64_t OffsetValue = OffsetImmOp.getImm();
 
   // NOTE: We always need AT for ULHU, as it is always used as the source
   // register for one of the LBu's.
   unsigned ATReg = getATReg(IDLoc);
   if (!ATReg)
     return true;
 
   // When the value of offset+1 does not fit in 16 bits, we have to load the
   // offset in AT, (D)ADDu the original source register (if there was one), and
if (isLittle()) {
     FirstLbuOffset = LoadedOffsetInAT ? 0 : OffsetValue;
     SecondLbuOffset = LoadedOffsetInAT ? 1 : (OffsetValue + 1);
   }
 
   unsigned SllReg = LoadedOffsetInAT ? DstReg : ATReg;
 
   MCInst TmpInst;
   TmpInst.setOpcode(Mips::LBu);
   TmpInst.addOperand(MCOperand::createReg(FirstLbuDstReg));
   TmpInst.addOperand(MCOperand::createReg(LbuSrcReg));
   TmpInst.addOperand(MCOperand::createImm(FirstLbuOffset));
   Instructions.push_back(TmpInst);
 
   TmpInst.clear();
   TmpInst.setOpcode(Mips::LBu);
   TmpInst.addOperand(MCOperand::createReg(SecondLbuDstReg));
   TmpInst.addOperand(MCOperand::createReg(LbuSrcReg));
   TmpInst.addOperand(MCOperand::createImm(SecondLbuOffset));
   Instructions.push_back(TmpInst);
 
   TmpInst.clear();
bool MipsAsmParser::expandUlw(MCInst &Inst, SMLoc IDLoc,
   RightLoadInst.addOperand(DstRegOp);
   RightLoadInst.addOperand(MCOperand::createReg(FinalSrcReg));
   RightLoadInst.addOperand(MCOperand::createImm(RightLoadOffset ));
   Instructions.push_back(RightLoadInst);
 
   return false;
 }
 
+bool MipsAsmParser::expandAliasImmediate(MCInst &Inst, SMLoc IDLoc,
+                                         SmallVectorImpl<MCInst> &Instructions) {
+
+  assert (Inst.getNumOperands() == 3 && "Invalid operand count");
+  assert (Inst.getOperand(0).isReg() &&
+          Inst.getOperand(1).isReg() &&
+          Inst.getOperand(2).isImm() && "Invalid instruction operand.");
+
+  unsigned ATReg = Mips::NoRegister;
+  unsigned FinalDstReg = Mips::NoRegister;
+  unsigned DstReg = Inst.getOperand(0).getReg();
+  unsigned SrcReg = Inst.getOperand(1).getReg();
+  int64_t ImmValue = Inst.getOperand(2).getImm();
+  unsigned FinalOpcode = Inst.getOpcode();
+
+  if (DstReg == SrcReg) {
+    ATReg = getATReg(Inst.getLoc());
+    if (!ATReg)
+      return true;
+    FinalDstReg = DstReg;
+    DstReg = ATReg;
+  }
+
+  if (!loadImmediate(ImmValue, DstReg, Mips::NoRegister, true, Inst.getLoc(), Instructions)) {
+    switch (FinalOpcode) {
+    default:
+      llvm_unreachable("unimplemented expansion");
+    case (Mips::ADDi):
+      FinalOpcode = Mips::ADD;
+      break;
+    case (Mips::ADDiu):
+      FinalOpcode = Mips::ADDu;
+      break;
+    case (Mips::ANDi):
+      FinalOpcode = Mips::AND;
+      break;
+    case (Mips::NORImm):
+      FinalOpcode = Mips::NOR;
+      break;
+    case (Mips::ORi):
+      FinalOpcode = Mips::OR;
+      break;
+    case (Mips::SLTi):
+      FinalOpcode = Mips::SLT;
+      break;
+    case (Mips::SLTiu):
+      FinalOpcode = Mips::SLTu;
+      break;
+    case (Mips::XORi):
+      FinalOpcode = Mips::XOR;
+      break;
+    }
+
+    MCInst tmpInst;
+
+    tmpInst.clear();
+    tmpInst.setLoc(Inst.getLoc());
+    tmpInst.setOpcode(FinalOpcode);
+    if (FinalDstReg == Mips::NoRegister) {
+      tmpInst.addOperand(MCOperand::createReg(DstReg));
+      tmpInst.addOperand(MCOperand::createReg(DstReg));
+      tmpInst.addOperand(MCOperand::createReg(SrcReg));
+    } else {
+      tmpInst.addOperand(MCOperand::createReg(FinalDstReg));
+      tmpInst.addOperand(MCOperand::createReg(FinalDstReg));
+      tmpInst.addOperand(MCOperand::createReg(DstReg));
+    }
+    Instructions.push_back(tmpInst);
+    return false;
+  }
+  return true;
+}
+
 void MipsAsmParser::createNop(bool hasShortDelaySlot, SMLoc IDLoc,
                               SmallVectorImpl<MCInst> &Instructions) {
   MCInst NopInst;
   if (hasShortDelaySlot) {
     NopInst.setOpcode(Mips::MOVE16_MM);
     NopInst.addOperand(MCOperand::createReg(Mips::ZERO));
     NopInst.addOperand(MCOperand::createReg(Mips::ZERO));
   } else {

lib/Target/Mips/MipsInstrInfo.td

MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
                      !strconcat(instr_asm, "\t$rt, $imm32")> ;
 def LoadAddrImm32 : LoadAddressFromImm32<"la", uimm5, GPR32Opnd>;
 
 def JalTwoReg : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs),
                       "jal\t$rd, $rs"> ;
 def JalOneReg : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs),
                       "jal\t$rs"> ;
 
+def NORImm : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),
+                      "nor\t$rs, $rt, $imm"> ;
+
 let hasDelaySlot = 1 in {
 def BneImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),
                                (ins imm64:$imm64, brtarget:$offset),
                                "bne\t$rt, $imm64, $offset">;
 def BeqImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),
                                (ins imm64:$imm64, brtarget:$offset),
                                "beq\t$rt, $imm64, $offset">;
 

test/MC/Mips/instalias-imm-expanding.s

+# RUN: llvm-mc  %s -triple=mipsel-unknown-linux -mcpu=mips32r2 -show-encoding | FileCheck %s
+
+
+  .text
+text_label:
+
+  add $4, -0x80000000
+# CHECK: lui    $1, 32768               # encoding: [0x00,0x80,0x01,0x3c]
+# CHECK: add    $4, $4, $1              # encoding: [0x20,0x20,0x81,0x00]
+  add $4, -0x8001
+# CHECK: lui    $1, 65535               # encoding: [0xff,0xff,0x01,0x3c]
+# CHECK: ori    $1, $1, 32767           # encoding: [0xff,0x7f,0x21,0x34]
+# CHECK: add    $4, $4, $1              # encoding: [0x20,0x20,0x81,0x00]
+  add $4, -0x8000
+# CHECK: addi   $4, $4, -32768          # encoding: [0x00,0x80,0x84,0x20]
+  add $4, 0
+# CHECK: addi   $4, $4, 0               # encoding: [0x00,0x00,0x84,0x20]
+  add $4, 0xFFFF
+# CHECK: ori    $1, $zero, 65535        # encoding: [0xff,0xff,0x01,0x34]
+# CHECK: add    $4, $4, $1              # encoding: [0x20,0x20,0x81,0x00]
+  add $4, 0x10000
+# CHECK: lui    $1, 1                   # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: add    $4, $4, $1              # encoding: [0x20,0x20,0x81,0x00]
+  add $4, 0xFFFFFFFF
+# CHECK: lui    $1, 65535               # encoding: [0xff,0xff,0x01,0x3c]
+# CHECK: ori    $1, $1, 65535           # encoding: [0xff,0xff,0x21,0x34]
+# CHECK: add    $4, $4, $1              # encoding: [0x20,0x20,0x81,0x00]
+
+  add $4, $5, -0x80000000
+# CHECK: lui    $4, 32768               # encoding: [0x00,0x80,0x04,0x3c]
+# CHECK: add    $4, $4, $5              # encoding: [0x20,0x20,0x85,0x00]
+  add $4, $5, -0x8001
+# CHECK: lui    $4, 65535               # encoding: [0xff,0xff,0x04,0x3c]
+# CHECK: ori    $4, $4, 32767           # encoding: [0xff,0x7f,0x84,0x34]
+# CHECK: add    $4, $4, $5              # encoding: [0x20,0x20,0x85,0x00]
+  add $4, $5, -0x8000
+# CHECK: addi   $4, $5, -32768          # encoding: [0x00,0x80,0xa4,0x20]
+  add $4, $5, 0
+# CHECK: addi   $4, $5, 0               # encoding: [0x00,0x00,0xa4,0x20]
+  add $4, $5, 0xFFFF
+# CHECK: ori    $4, $zero, 65535        # encoding: [0xff,0xff,0x04,0x34]
+# CHECK: add    $4, $4, $5              # encoding: [0x20,0x20,0x85,0x00]
+  add $4, $5, 0x10000
+# CHECK: lui    $4, 1                   # encoding: [0x01,0x00,0x04,0x3c]
+# CHECK: add    $4, $4, $5              # encoding: [0x20,0x20,0x85,0x00]
+  add $4, $5, 0xFFFFFFFF
+# CHECK: lui    $4, 65535               # encoding: [0xff,0xff,0x04,0x3c]
+# CHECK: ori    $4, $4, 65535           # encoding: [0xff,0xff,0x84,0x34]
+# CHECK: add    $4, $4, $5              # encoding: [0x20,0x20,0x85,0x00]
+
+  addu $4, -0x80000000
+# CHECK: lui    $1, 32768               # encoding: [0x00,0x80,0x01,0x3c]
+# CHECK: addu   $4, $4, $1              # encoding: [0x21,0x20,0x81,0x00]
+  addu $4, -0x8001
+# CHECK: lui    $1, 65535               # encoding: [0xff,0xff,0x01,0x3c]
+# CHECK: ori    $1, $1, 32767           # encoding: [0xff,0x7f,0x21,0x34]
+# CHECK: addu   $4, $4, $1              # encoding: [0x21,0x20,0x81,0x00]
+  addu $4, -0x8000
+# CHECK: addiu  $4, $4, -32768          # encoding: [0x00,0x80,0x84,0x24]
+  addu $4, 0
+# CHECK: addiu  $4, $4, 0               # encoding: [0x00,0x00,0x84,0x24]
+  addu $4, 0xFFFF
+# CHECK: ori    $1, $zero, 65535        # encoding: [0xff,0xff,0x01,0x34]
+# CHECK: addu   $4, $4, $1              # encoding: [0x21,0x20,0x81,0x00]
+  addu $4, 0x10000
+# CHECK: lui    $1, 1                   # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: addu   $4, $4, $1              # encoding: [0x21,0x20,0x81,0x00]
+  addu $4, 0xFFFFFFFF
+# CHECK: lui    $1, 65535               # encoding: [0xff,0xff,0x01,0x3c]
+# CHECK: ori    $1, $1, 65535           # encoding: [0xff,0xff,0x21,0x34]
+# CHECK: addu   $4, $4, $1              # encoding: [0x21,0x20,0x81,0x00]
+
+  addu $4, $5, -0x80000000
+# CHECK: lui    $4, 32768               # encoding: [0x00,0x80,0x04,0x3c]
+# CHECK: addu   $4, $4, $5              # encoding: [0x21,0x20,0x85,0x00]
+  addu $4, $5, -0x8001
+# CHECK: lui    $4, 65535               # encoding: [0xff,0xff,0x04,0x3c]
+# CHECK: ori    $4, $4, 32767           # encoding: [0xff,0x7f,0x84,0x34]
+# CHECK: addu   $4, $4, $5              # encoding: [0x21,0x20,0x85,0x00]
+  addu $4, $5, -0x8000
+# CHECK: addiu  $4, $5, -32768          # encoding: [0x00,0x80,0xa4,0x24]
+  addu $4, $5, 0
+# CHECK: addiu  $4, $5, 0               # encoding: [0x00,0x00,0xa4,0x24]
+  addu $4, $5, 0xFFFF
+# CHECK: ori    $4, $zero, 65535        # encoding: [0xff,0xff,0x04,0x34]
+# CHECK: addu   $4, $4, $5              # encoding: [0x21,0x20,0x85,0x00]
+  addu $4, $5, 0x10000
+# CHECK: lui    $4, 1                   # encoding: [0x01,0x00,0x04,0x3c]
+# CHECK: addu   $4, $4, $5              # encoding: [0x21,0x20,0x85,0x00]
+  addu $4, $5, 0xFFFFFFFF
+# CHECK: lui    $4, 65535               # encoding: [0xff,0xff,0x04,0x3c]
+# CHECK: ori    $4, $4, 65535           # encoding: [0xff,0xff,0x84,0x34]
+# CHECK: addu   $4, $4, $5              # encoding: [0x21,0x20,0x85,0x00]
+
+  and $4, -0x80000000
+# CHECK: lui    $1, 32768               # encoding: [0x00,0x80,0x01,0x3c]
+# CHECK: and    $4, $4, $1              # encoding: [0x24,0x20,0x81,0x00]
+  and $4, -0x8001
+# CHECK: lui    $1, 65535               # encoding: [0xff,0xff,0x01,0x3c]
+# CHECK: ori    $1, $1, 32767           # encoding: [0xff,0x7f,0x21,0x34]
+# CHECK: and    $4, $4, $1              # encoding: [0x24,0x20,0x81,0x00]
+  and $4, -0x8000
+# CHECK: addiu  $1, $zero, -32768       # encoding: [0x00,0x80,0x01,0x24]
+  and $4, 0
+# CHECK: andi   $4, $4, 0               # encoding: [0x00,0x00,0x84,0x30]
+  and $4, 0xFFFF
+# CHECK: andi   $4, $4, 65535           # encoding: [0xff,0xff,0x84,0x30]
+  and $4, 0x10000
+# CHECK: lui    $1, 1                   # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: and    $4, $4, $1              # encoding: [0x24,0x20,0x81,0x00]
+  and $4, 0xFFFFFFFF
+# CHECK: lui    $1, 65535               # encoding: [0xff,0xff,0x01,0x3c]
+# CHECK: ori    $1, $1, 65535           # encoding: [0xff,0xff,0x21,0x34]
+# CHECK: and    $4, $4, $1              # encoding: [0x24,0x20,0x81,0x00]
+
+  and $4, $5, -0x80000000
+# CHECK: lui    $4, 32768               # encoding: [0x00,0x80,0x04,0x3c]
+# CHECK: and    $4, $4, $5              # encoding: [0x24,0x20,0x85,0x00]
+  and $4, $5, -0x8001
+# CHECK: lui    $4, 65535               # encoding: [0xff,0xff,0x04,0x3c]
+# CHECK: ori    $4, $4, 32767           # encoding: [0xff,0x7f,0x84,0x34]
+# CHECK: and    $4, $4, $5              # encoding: [0x24,0x20,0x85,0x00]
+  and $4, $5, -0x8000
+# CHECK: addiu  $4, $zero, -32768       # encoding: [0x00,0x80,0x04,0x24]
+# CHECK: and    $4, $4, $5              # encoding: [0x24,0x20,0x85,0x00]
+  and $4, $5, 0
+# CHECK: andi   $4, $5, 0               # encoding: [0x00,0x00,0xa4,0x30]
+  and $4, $5, 0xFFFF
+# CHECK: andi   $4, $5, 65535           # encoding: [0xff,0xff,0xa4,0x30]
+  and $4, $5, 0x10000
+# CHECK: lui    $4, 1                   # encoding: [0x01,0x00,0x04,0x3c]
+# CHECK: and    $4, $4, $5              # encoding: [0x24,0x20,0x85,0x00]
+  and $4, $5, 0xFFFFFFFF
+# CHECK: lui    $4, 65535               # encoding: [0xff,0xff,0x04,0x3c]
+# CHECK: ori    $4, $4, 65535           # encoding: [0xff,0xff,0x84,0x34]
+# CHECK: and    $4, $4, $5              # encoding: [0x24,0x20,0x85,0x00]
+
+  nor $4,$5,0
+# CHECK: ori    $4, $zero, 0            # encoding: [0x00,0x00,0x04,0x34]
+# CHECK: nor    $4, $4, $5              # encoding: [0x27,0x20,0x85,0x00]
+  nor $4,$5,1
+# CHECK: ori    $4, $zero, 1            # encoding: [0x01,0x00,0x04,0x34]
+# CHECK: nor    $4, $4, $5              # encoding: [0x27,0x20,0x85,0x00]
+  nor $4,$5,0x8000
+# CHECK: ori    $4, $zero, 32768        # encoding: [0x00,0x80,0x04,0x34]
+# CHECK: nor    $4, $4, $5              # encoding: [0x27,0x20,0x85,0x00]
+  nor $4,$5,-0x8000
+# CHECK: addiu  $4, $zero, -32768       # encoding: [0x00,0x80,0x04,0x24]
+# CHECK: nor    $4, $4, $5              # encoding: [0x27,0x20,0x85,0x00]
+  nor $4,$5,0x10000
+# CHECK: lui    $4, 1                   # encoding: [0x01,0x00,0x04,0x3c]
+# CHECK: nor    $4, $4, $5              # encoding: [0x27,0x20,0x85,0x00]
+  nor $4,$5,0x1a5a5
+# CHECK: lui    $4, 1                   # encoding: [0x01,0x00,0x04,0x3c]
+# CHECK: ori    $4, $4, 42405           # encoding: [0xa5,0xa5,0x84,0x34]
+# CHECK: nor    $4, $4, $5              # encoding: [0x27,0x20,0x85,0x00]
+
+  or $4, -0x80000000
+# CHECK: lui    $1, 32768               # encoding: [0x00,0x80,0x01,0x3c]
+# CHECK: or     $4, $4, $1              # encoding: [0x25,0x20,0x81,0x00]
+  or $4, -0x8001
+# CHECK: lui    $1, 65535               # encoding: [0xff,0xff,0x01,0x3c]
+# CHECK: ori    $1, $1, 32767           # encoding: [0xff,0x7f,0x21,0x34]
+# CHECK: or     $4, $4, $1              # encoding: [0x25,0x20,0x81,0x00]
+  or $4, -0x8000
+# CHECK: addiu  $1, $zero, -32768       # encoding: [0x00,0x80,0x01,0x24]
+# CHECK: or     $4, $4, $1              # encoding: [0x25,0x20,0x81,0x00]
+  or $4, 0
+# CHECK: ori    $4, $4, 0               # encoding: [0x00,0x00,0x84,0x34]
+  or $4, 0xFFFF
+# CHECK: ori    $4, $4, 65535           # encoding: [0xff,0xff,0x84,0x34]
+  or $4, 0x10000
+# CHECK: lui    $1, 1                   # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: or     $4, $4, $1              # encoding: [0x25,0x20,0x81,0x00]
+  or $4, 0xFFFFFFFF
+# CHECK: lui    $1, 65535               # encoding: [0xff,0xff,0x01,0x3c]
+# CHECK: ori    $1, $1, 65535           # encoding: [0xff,0xff,0x21,0x34]
+# CHECK: or     $4, $4, $1              # encoding: [0x25,0x20,0x81,0x00]
+
+  or $4, $5, -0x80000000
+# CHECK: lui    $4, 32768               # encoding: [0x00,0x80,0x04,0x3c]
+# CHECK: or     $4, $4, $5              # encoding: [0x25,0x20,0x85,0x00]
+  or $4, $5, -0x8001
+# CHECK: lui    $4, 65535               # encoding: [0xff,0xff,0x04,0x3c]
+# CHECK: ori    $4, $4, 32767           # encoding: [0xff,0x7f,0x84,0x34]
+# CHECK: or     $4, $4, $5              # encoding: [0x25,0x20,0x85,0x00]
+  or $4, $5, -0x8000
+# CHECK: addiu  $4, $zero, -32768       # encoding: [0x00,0x80,0x04,0x24]
+# CHECK: or     $4, $4, $5              # encoding: [0x25,0x20,0x85,0x00]
+  or $4, $5, 0
+# CHECK: ori    $4, $5, 0               # encoding: [0x00,0x00,0xa4,0x34]
+  or $4, $5, 0xFFFF
+# CHECK: ori    $4, $5, 65535           # encoding: [0xff,0xff,0xa4,0x34]
+  or $4, $5, 0x10000
+# CHECK: lui    $4, 1                   # encoding: [0x01,0x00,0x04,0x3c]
+# CHECK: or     $4, $4, $5              # encoding: [0x25,0x20,0x85,0x00]
+  or $4, $5, 0xFFFFFFFF
+# CHECK: lui    $4, 65535               # encoding: [0xff,0xff,0x04,0x3c]
+# CHECK: ori    $4, $4, 65535           # encoding: [0xff,0xff,0x84,0x34]
+# CHECK: or     $4, $4, $5              # encoding: [0x25,0x20,0x85,0x00]
+
+  slt $4, $5, -0x80000000
+# CHECK: lui    $4, 32768               # encoding: [0x00,0x80,0x04,0x3c]
+# CHECK: slt    $4, $4, $5              # encoding: [0x2a,0x20,0x85,0x00]
+  slt $4, $5, -0x8001
+# CHECK: lui    $4, 65535               # encoding: [0xff,0xff,0x04,0x3c]
+# CHECK: ori    $4, $4, 32767           # encoding: [0xff,0x7f,0x84,0x34]
+# CHECK: slt    $4, $4, $5              # encoding: [0x2a,0x20,0x85,0x00]
+  slt $4, $5, -0x8000
+# CHECK: slti   $4, $5, -32768          # encoding: [0x00,0x80,0xa4,0x28]
+  slt $4, $5, 0
+# CHECK: slti   $4, $5, 0               # encoding: [0x00,0x00,0xa4,0x28]
+  slt $4, $5, 0xFFFF
+# CHECK: ori    $4, $zero, 65535        # encoding: [0xff,0xff,0x04,0x34]
+  slt $4, $5, 0x10000
+# CHECK: lui    $4, 1                   # encoding: [0x01,0x00,0x04,0x3c]
+# CHECK: slt    $4, $4, $5              # encoding: [0x2a,0x20,0x85,0x00]
+  slt $4, $5, 0xFFFFFFFF
+# CHECK: lui    $4, 65535               # encoding: [0xff,0xff,0x04,0x3c]
+# CHECK: ori    $4, $4, 65535           # encoding: [0xff,0xff,0x84,0x34]
+# CHECK: slt    $4, $4, $5              # encoding: [0x2a,0x20,0x85,0x00]
+
+  sltu $4, $5, -0x80000000
+# CHECK: lui    $4, 32768               # encoding: [0x00,0x80,0x04,0x3c]
+# CHECK: sltu   $4, $4, $5              # encoding: [0x2b,0x20,0x85,0x00]
+  sltu $4, $5, -0x8001
+# CHECK: lui    $4, 65535               # encoding: [0xff,0xff,0x04,0x3c]
+# CHECK: ori    $4, $4, 32767           # encoding: [0xff,0x7f,0x84,0x34]
+# CHECK: sltu   $4, $4, $5              # encoding: [0x2b,0x20,0x85,0x00]
+  sltu $4, $5, -0x8000
+# CHECK: sltiu  $4, $5, -32768          # encoding: [0x00,0x80,0xa4,0x2c]
+  sltu $4, $5, 0
+# CHECK: sltiu  $4, $5, 0               # encoding: [0x00,0x00,0xa4,0x2c]
+  sltu $4, $5, 0xFFFF
+# CHECK: ori    $4, $zero, 65535        # encoding: [0xff,0xff,0x04,0x34]
+  sltu $4, $5, 0x10000
+# CHECK: lui    $4, 1                   # encoding: [0x01,0x00,0x04,0x3c]
+# CHECK: sltu   $4, $4, $5              # encoding: [0x2b,0x20,0x85,0x00]
+  sltu $4, $5, 0xFFFFFFFF
+# CHECK: lui    $4, 65535               # encoding: [0xff,0xff,0x04,0x3c]
+# CHECK: ori    $4, $4, 65535           # encoding: [0xff,0xff,0x84,0x34]
+# CHECK: sltu   $4, $4, $5              # encoding: [0x2b,0x20,0x85,0x00]
+
+  xor $4, -0x80000000
+# CHECK: lui    $1, 32768               # encoding: [0x00,0x80,0x01,0x3c]
+# CHECK: xor    $4, $4, $1              # encoding: [0x26,0x20,0x81,0x00]
+  xor $4, -0x8001
+# CHECK: lui    $1, 65535               # encoding: [0xff,0xff,0x01,0x3c]
+# CHECK: ori    $1, $1, 32767           # encoding: [0xff,0x7f,0x21,0x34]
+# CHECK: xor    $4, $4, $1              # encoding: [0x26,0x20,0x81,0x00]
+  xor $4, -0x8000
+# CHECK: addiu  $1, $zero, -32768       # encoding: [0x00,0x80,0x01,0x24]
+  xor $4, 0
+# CHECK: xori   $4, $4, 0               # encoding: [0x00,0x00,0x84,0x38]
+  xor $4, 0xFFFF
+# CHECK: xori   $4, $4, 65535           # encoding: [0xff,0xff,0x84,0x38]
+  xor $4, 0x10000
+# CHECK: lui    $1, 1                   # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: xor    $4, $4, $1              # encoding: [0x26,0x20,0x81,0x00]
+  xor $4, 0xFFFFFFFF
+# CHECK: lui    $1, 65535               # encoding: [0xff,0xff,0x01,0x3c]
+# CHECK: ori    $1, $1, 65535           # encoding: [0xff,0xff,0x21,0x34]
+# CHECK: xor    $4, $4, $1              # encoding: [0x26,0x20,0x81,0x00]
+
+  xor $4, $5, -0x80000000
+# CHECK: lui    $4, 32768               # encoding: [0x00,0x80,0x04,0x3c]
+# CHECK: xor    $4, $4, $5              # encoding: [0x26,0x20,0x85,0x00]
+  xor $4, $5, -0x8001
+# CHECK: lui    $4, 65535               # encoding: [0xff,0xff,0x04,0x3c]
+# CHECK: ori    $4, $4, 32767           # encoding: [0xff,0x7f,0x84,0x34]
+# CHECK: xor    $4, $4, $5              # encoding: [0x26,0x20,0x85,0x00]
+  xor $4, $5, -0x8000
+# CHECK: addiu  $4, $zero, -32768       # encoding: [0x00,0x80,0x04,0x24]
+# CHECK: xor $4, $4, $5                 # encoding: [0x26,0x20,0x85,0x00]
+  xor $4, $5, 0
+# CHECK: xori   $4, $5, 0               # encoding: [0x00,0x00,0xa4,0x38]
+  xor $4, $5, 0xFFFF
+# CHECK: xori   $4, $5, 65535           # encoding: [0xff,0xff,0xa4,0x38]
+  xor $4, $5, 0x10000
+# CHECK: lui    $4, 1                   # encoding: [0x01,0x00,0x04,0x3c]
+# CHECK: xor    $4, $4, $5              # encoding: [0x26,0x20,0x85,0x00]
+  xor $4, $5, 0xFFFFFFFF
+# CHECK: lui    $4, 65535               # encoding: [0xff,0xff,0x04,0x3c]
+# CHECK: ori    $4, $4, 65535           # encoding: [0xff,0xff,0x84,0x34]
+# CHECK: xor    $4, $4, $5              # encoding: [0x26,0x20,0x85,0x00]
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+    .space  8