MIR Serialization: Start serializing machine operands by serializing physical register operands.

[arphaman]

Summary

This patch is based on a patch that introduces MILexer (http://reviews.llvm.org/D10521).

This patch begins to implement serialization of machine operands by serializing the physical register
machine operands.

[arphaman]

Update this patch to use the new lexing approach that was introduces in the updated patch for http://reviews.llvm.org/D10521.

[arphaman]

Rebase and update the patch to add the fixes suggested by Duncan.

lib/CodeGen/MIRParser/MILexer.h

 
 namespace mitok {
 
 enum Kind {
   // Markers
   Eof,
   Error,
 
+  // Tokens with no info.
+  comma,
+  equal,
+
   // Identifier tokens
-  Identifier
+  Identifier,
+  NamedRegister
 };
 
 } // end namespace mitok
 
 class MILexer {
   SourceMgr &SM;
   SMDiagnostic &Error;
   const char *BufStart;
public:
   /// Report an error at the given location with the given message, and return
   /// mitok::Error.
   mitok::Kind error(SMLoc Loc, const Twine &Msg);
 
   bool isError() const { return CurKind == mitok::Error; }
 
   SMLoc getLoc() const { return CurLoc; }
 
+  bool isRegister() const { return CurKind == mitok::NamedRegister; }
+
   mitok::Kind getKind() const { return CurKind; }
 
   StringRef getStringValue() const { return StrVal; }
 
   void lex() { CurKind = lexToken(); }
 
 private:
   bool isEOF() const;
   void skipWhitespace();
   mitok::Kind lexToken();
   mitok::Kind lexIdentifier();
+  mitok::Kind lexPercent();
 };
 
 } // end namespace llvm
 
 #endif

lib/CodeGen/MIRParser/MILexer.cpp

 mitok::Kind MILexer::lexIdentifier() {
   auto Start = CurPtr - 1;
   while (!isEOF() && isIdentifierChar(*CurPtr))
     ++CurPtr;
   StrVal = StringRef(Start, CurPtr - Start);
   return mitok::Identifier;
 }
 
+mitok::Kind MILexer::lexPercent() {
+  auto Start = CurPtr;
+  while (!isEOF() && isIdentifierChar(*CurPtr))
+    ++CurPtr;
+  StrVal = StringRef(Start, CurPtr - Start);
+  if (StrVal.empty())
+    return error(Twine("expected a name after '%'"));
+  return mitok::NamedRegister;
+}
+
 mitok::Kind MILexer::lexToken() {
   skipWhitespace();
   CurLoc = SMLoc::getFromPointer(CurPtr);
   if (isEOF())
     return mitok::Eof;
 
   char CurChar = *CurPtr++;
+  switch (CurChar) {
+  case ',':
+    return mitok::comma;
+  case '=':
+    return mitok::equal;
+  case '%':
+    return lexPercent();
+  default:
     if (isalpha(CurChar) || CurChar == '_')
       return lexIdentifier();
     return error(Twine("unexpected character '") + Twine(CurChar) + "'");
   }
+}

lib/CodeGen/MIRParser/MIParser.cpp

 
 namespace {
 
 class MIParser {
   MachineFunction &MF;
   MILexer Lex;
   /// Maps from instruction names to op codes.
   StringMap<unsigned> Names2InstrOpCodes;
+  /// Maps from register names to registers.
+  StringMap<unsigned> Names2Regs;
 
 public:
   MIParser(SourceMgr &SM, MachineFunction &MF, SMDiagnostic &Error,
            StringRef Source);
 
   /// Report an error at the current location with the given message.
   ///
   /// This function always return true.
   bool error(const Twine &Msg);
 
   MachineInstr *parse();
 
+  bool parseRegister(unsigned &Reg);
+
+  bool parseRegisterOperand(MachineOperand &Dest, bool IsDef = false);
+
+  bool parseMachineOperand(MachineOperand &Dest);
+
 private:
   void initNames2InstrOpCodes();
 
   /// Try to convert an instruction name to an opcode. Return true if the
   /// instruction name is invalid.
   bool parseInstrName(StringRef InstrName, unsigned &OpCode);
 
   bool parseInstruction(unsigned &OpCode);
+
+  void initNames2Regs();
+
+  /// Try to convert a register name to a register number. Return true if the
+  /// register name is invalid.
+  bool getRegisterByName(StringRef RegName, unsigned &Reg);
 };
 
 } // end anonymous namespace
 
 MIParser::MIParser(SourceMgr &SM, MachineFunction &MF, SMDiagnostic &Error,
                    StringRef Source)
     : MF(MF), Lex(SM, Error, Source) {}
 
 bool MIParser::error(const Twine &Msg) {
   Lex.error(Msg);
   return true;
 }
 
 MachineInstr *MIParser::parse() {
   Lex.lex();
 
+  // Parse any register operands before '='
+  // TODO: Allow parsing of multiple operands before '='
+  MachineOperand MO = MachineOperand::CreateImm(0);
+  SmallVector<MachineOperand, 8> Operands;
+  if (Lex.isRegister()) {
+    if (parseRegisterOperand(MO, /*IsDef=*/true))
+      return nullptr;
+    Operands.push_back(MO);
+    if (Lex.getKind() != mitok::equal) {
+      error("expected '='");
+      return nullptr;
+    }
+    Lex.lex();
+  }
+
   unsigned OpCode;
   if (Lex.isError() || parseInstruction(OpCode))
     return nullptr;
 
-  // TODO: Parse the rest of instruction - machine operands, etc.
+  // TODO: Parse the instruction flags and memory operands.
+
+  // Parse the remaining machine operands.
+  while (Lex.getKind() != mitok::Eof) {
+    if (parseMachineOperand(MO))
+      return nullptr;
+    Operands.push_back(MO);
+    if (Lex.getKind() == mitok::Eof)
+      break;
+    if (Lex.getKind() != mitok::comma) {
+      error("expected ',' before the next machine operand");
+      return nullptr;
+    }
+    Lex.lex();
+  }
+
   const auto &MCID = MF.getSubtarget().getInstrInfo()->get(OpCode);
-  auto *MI = MF.CreateMachineInstr(MCID, DebugLoc());
+
+  // Verify machine operands
+  if (!MCID.isVariadic()) {
+    for (size_t I = 0, E = Operands.size(); I < E; ++I) {
+      if (I < MCID.getNumOperands())
+        continue;
+      // Mark this register as implicit to prevent an assertion when it's added
+      // to an instruction. This is a temporary workaround until the implicit
+      // register flag can be parsed.
+      Operands[I].setImplicit();
+    }
+  }
+
+  // TODO: Determine the implicit behaviour when implicit register flags are
+  // parsed.
+  auto *MI = MF.CreateMachineInstr(MCID, DebugLoc(), /*NoImplicit=*/true);
+  for (const auto &Operand : Operands) {
+    MI->addOperand(MF, Operand);
+  }
   return MI;
 }
 
 bool MIParser::parseInstruction(unsigned &OpCode) {
   if (Lex.getKind() != mitok::Identifier)
     return error("expected a machine instruction");
   StringRef InstrName = Lex.getStringValue();
   if (parseInstrName(InstrName, OpCode))
     return error(Twine("unknown machine instruction name '") + InstrName + "'");
+  Lex.lex();
+  return false;
+}
+
+bool MIParser::parseRegister(unsigned &Reg) {
+  switch (Lex.getKind()) {
+  case mitok::NamedRegister:
+    if (getRegisterByName(Lex.getStringValue(), Reg))
+      return error(Twine("unknown register name '") + Lex.getStringValue() +
+                   "'");
+    break;
+  // TODO: Parse other register kinds.
+  default:
+    llvm_unreachable("The current token should be a register");
+  }
+  return false;
+}
+
+bool MIParser::parseRegisterOperand(MachineOperand &Dest, bool IsDef) {
+  unsigned Reg;
+  // TODO: Parse register flags
+  if (parseRegister(Reg))
+    return true;
+  Lex.lex();
+  // TODO: Parse subregister.
+  Dest = MachineOperand::CreateReg(Reg, IsDef);
+  return false;
+}
+
+bool MIParser::parseMachineOperand(MachineOperand &Dest) {
+  switch (Lex.getKind()) {
+  case mitok::NamedRegister:
+    return parseRegisterOperand(Dest);
+  case mitok::Error:
+    return true;
+  default:
+    // TODO: parse the other machine operands.
+    return error("expected a machine operand");
+  }
   return false;
 }
 
 void MIParser::initNames2InstrOpCodes() {
   if (!Names2InstrOpCodes.empty())
     return;
   const auto *TII = MF.getSubtarget().getInstrInfo();
   assert(TII && "Expected target instruction info");
   for (unsigned I = 0, E = TII->getNumOpcodes(); I < E; ++I)
     Names2InstrOpCodes.insert(
         std::make_pair(StringRef(TII->getName(I)).lower(), I));
 }
 
 bool MIParser::parseInstrName(StringRef InstrName, unsigned &OpCode) {
   initNames2InstrOpCodes();
   auto InstrInfo = Names2InstrOpCodes.find(InstrName);
   if (InstrInfo == Names2InstrOpCodes.end())
     return true;
   OpCode = InstrInfo->getValue();
   return false;
 }
 
+void MIParser::initNames2Regs() {
+  if (!Names2Regs.empty())
+    return;
+  const auto *TRI = MF.getSubtarget().getRegisterInfo();
+  assert(TRI && "Expected target register info");
+  for (unsigned I = 0, E = TRI->getNumRegs(); I < E; ++I)
+    Names2Regs.insert(std::make_pair(StringRef(TRI->getName(I)).lower(), I));
+}
+
+bool MIParser::getRegisterByName(StringRef RegName, unsigned &Reg) {
+  initNames2Regs();
+  auto RegInfo = Names2Regs.find(RegName);
+  if (RegInfo == Names2Regs.end())
+    return true;
+  Reg = RegInfo->getValue();
+  return false;
+}
+
 MachineInstr *llvm::parseMachineInstr(SourceMgr &SM, MachineFunction &MF,
                                       StringRef Src, SMDiagnostic &Error) {
   return MIParser(SM, MF, Error, Src).parse();
 }

lib/CodeGen/MIRPrinter.cpp

 /// format.
 class MIPrinter {
   raw_ostream &OS;
 
 public:
   MIPrinter(raw_ostream &OS) : OS(OS) {}
 
   void print(const MachineInstr &MI);
+
+  void print(const MachineOperand &Op, const TargetRegisterInfo *TRI);
 };
 
 } // end anonymous namespace
 
 namespace llvm {
 namespace yaml {
 
 /// This struct serializes the LLVM IR module.
for (const auto &MI : MBB) {
     MIPrinter(StrOS).print(MI);
     YamlMBB.Instructions.push_back(StrOS.str());
     Str.clear();
   }
 }
 
 void MIPrinter::print(const MachineInstr &MI) {
   const auto &SubTarget = MI.getParent()->getParent()->getSubtarget();
+  const auto *TRI = SubTarget.getRegisterInfo();
+  assert(TRI && "Expected target register info");
   const auto *TII = SubTarget.getInstrInfo();
 
+  unsigned I = 0, E = MI.getNumOperands();
+  for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
+         !MI.getOperand(I).isImplicit();
+       ++I) {
+    if (I)
+      OS << ", ";
+    print(MI.getOperand(I), TRI);
+  }
+
+  if (I)
+    OS << " = ";
   OS << StringRef(TII->getName(MI.getOpcode())).lower();
-  // TODO: Print the instruction flags, machine operands, machine mem operands.
+  // TODO: Print the instruction flags, machine mem operands.
+  if (I < E)
+    OS << ' ';
+
+  bool NeedComma = false;
+  for (; I < E; ++I) {
+    if (NeedComma)
+      OS << ", ";
+    print(MI.getOperand(I), TRI);
+    NeedComma = true;
+  }
+}
+
+static void printReg(unsigned Reg, raw_ostream &OS,
+                     const TargetRegisterInfo *TRI) {
+  // TODO: Print Stack Slots
+  // TODO: Print no register
+  // TODO: Print virtual registers
+  if (Reg < TRI->getNumRegs())
+    OS << '%' << StringRef(TRI->getName(Reg)).lower();
+  else
+    llvm_unreachable("Can't print this kind of register yet");
+}
+
+void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) {
+  switch (Op.getType()) {
+  case MachineOperand::MO_Register:
+    // TODO: Print register flags.
+    printReg(Op.getReg(), OS, TRI);
+    // TODO: Print sub register.
+    break;
+  default:
+    // TODO: Print the other machine operands.
+    llvm_unreachable("Can't print this machine operand at the moment");
+  }
 }
 
 void llvm::printMIR(raw_ostream &OS, const Module &M) {
   yaml::Output Out(OS);
   Out << const_cast<Module &>(M);
 }
 
 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
   MIRPrinter Printer(OS);
   Printer.print(MF);
 }

test/CodeGen/MIR/X86/expected-machine-operand.mir

+# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
+
+--- |
+
+  define i32 @foo() {
+  entry:
+    ret i32 0
+  }
+
+...
+---
+name:            foo
+body:
+ - name:         entry
+   instructions:
+     # CHECK: 1:16: expected a machine operand
+     - '%eax = xor32rr ='
+     - 'retq %eax'
+...
+

test/CodeGen/MIR/X86/missing-comma.mir

+# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
+
+--- |
+
+  define i32 @foo() {
+  entry:
+    ret i32 0
+  }
+
+...
+---
+name:            foo
+body:
+ - name:         entry
+   instructions:
+     # CHECK: 1:21: expected ',' before the next machine operand
+     - '%eax = xor32rr %eax %eflags'
+     - 'retq %eax'
+...
+

test/CodeGen/MIR/X86/named-registers.mir

+# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s
+# This test ensures that the MIR parser parses X86 registers coorectly.
+
+--- |
+
+  define i32 @foo() {
+  entry:
+    ret i32 0
+  }
+
+...
+---
+# CHECK: name: foo
+name:            foo
+body:
+ - name:         entry
+   instructions:
+     # CHECK:      - '%eax = mov32r0
+     # CHECK-NEXT: - 'retq %eax
+     - '%eax = mov32r0'
+     - 'retq %eax'
+...

test/CodeGen/MIR/X86/unknown-register.mir

+# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
+# This test ensures that an error is reported when an unknown register is
+# encountered.
+
+--- |
+
+  define i32 @foo() {
+  entry:
+    ret i32 0
+  }
+
+...
+---
+name:            foo
+body:
+ - name:         entry
+   instructions:
+     # CHECK: 1:1: unknown register name 'xax'
+     - '%xax = mov32r0'
+     - 'retq %xax'
+...