[polly] In IslNodeBuilder::createForVector() use isl::noexception bindings [NFC]

[refactormyself]

Summary

The C++ bindings in isl_noexception provide better pointer management.
This allows the use of convenient memory management tools in C++.

• Replace the isl C entities with isl_noexception bindings
• Refactor calls to this function

No functional changes were made.

[Meinersbur]

polly/lib/CodeGen/IslNodeBuilder.cpp

453

In addition to converting the function arguments, please also use the smart pointer inside the method.

polly/include/polly/CodeGen/IslNodeBuilder.h

protected:
   ///
   /// This function will preload the representing load from @p IAClass and
   /// map all members of @p IAClass to that preloaded value, potentially casted
   /// to the required type.
   ///
   /// @returns False, iff a problem occurred and the load was not preloaded.
   bool preloadInvariantEquivClass(InvariantEquivClassTy &IAClass);
 
-  void createForVector(__isl_take isl_ast_node *For, int VectorWidth);
+  void createForVector(isl::ast_node For, int VectorWidth);
   void createForSequential(isl::ast_node For, bool MarkParallel);
 
   /// Create LLVM-IR that executes a for node thread parallel.
   ///
   /// @param For The FOR isl_ast_node for which code is generated.
   void createForParallel(__isl_take isl_ast_node *For);
 
   /// Create new access functions for modified memory accesses.

polly/lib/CodeGen/IslNodeBuilder.cpp

void IslNodeBuilder::createMark(__isl_take isl_ast_node *Node) {
   isl_ast_node_free(Node);
   // If a child node of a 'SIMD mark' is a loop that has a single iteration,
   // it will be optimized away and we should skip it.
   if (strcmp(isl_id_get_name(Id), "SIMD") == 0 &&
       isl_ast_node_get_type(Child) == isl_ast_node_for) {
     bool Vector = PollyVectorizerChoice == VECTORIZER_POLLY;
     int VectorWidth = getNumberOfIterations(isl::manage_copy(Child));
     if (Vector && 1 < VectorWidth && VectorWidth <= 16)
-      createForVector(Child, VectorWidth);
+      createForVector(isl::manage(Child), VectorWidth);
     else
       createForSequential(isl::manage(Child), true);
     isl_id_free(Id);
     return;
   }
   if (strcmp(isl_id_get_name(Id), "Inter iteration alias-free") == 0) {
     auto *BasePtr = static_cast<Value *>(isl_id_get_user(Id));
     Annotator.addInterIterationAliasFreeBasePtr(BasePtr);
if (ChildLoopAttr) {
     assert(Annotator.getStagingAttrEnv() == ChildLoopAttr &&
            "Nest must not overwrite loop attr environment");
     Annotator.getStagingAttrEnv() = AncestorLoopAttr;
   }
 
   isl_id_free(Id);
 }
 
-void IslNodeBuilder::createForVector(__isl_take isl_ast_node *For,
-                                     int VectorWidth) {
-  isl_ast_node *Body = isl_ast_node_for_get_body(For);
-  isl_ast_expr *Init = isl_ast_node_for_get_init(For);
-  isl_ast_expr *Inc = isl_ast_node_for_get_inc(For);
-  isl_ast_expr *Iterator = isl_ast_node_for_get_iterator(For);
+void IslNodeBuilder::createForVector(isl::ast_node For, int VectorWidth) {
+  isl_ast_node *Body = isl_ast_node_for_get_body(For.get());
+  isl_ast_expr *Init = isl_ast_node_for_get_init(For.get());
+  isl_ast_expr *Inc = isl_ast_node_for_get_inc(For.get());
+  isl_ast_expr *Iterator = isl_ast_node_for_get_iterator(For.get());
   isl_id *IteratorID = isl_ast_expr_get_id(Iterator);
 
   Value *ValueLB = ExprBuilder.create(Init);
   Value *ValueInc = ExprBuilder.create(Inc);
 
   Type *MaxType = ExprBuilder.getType(Iterator);
   MaxType = ExprBuilder.getWidestType(MaxType, ValueLB->getType());
   MaxType = ExprBuilder.getWidestType(MaxType, ValueInc->getType());
 
   if (MaxType != ValueLB->getType())
     ValueLB = Builder.CreateSExt(ValueLB, MaxType);
   if (MaxType != ValueInc->getType())
     ValueInc = Builder.CreateSExt(ValueInc, MaxType);
 
   std::vector<Value *> IVS(VectorWidth);
   IVS[0] = ValueLB;
 
   for (int i = 1; i < VectorWidth; i++)
     IVS[i] = Builder.CreateAdd(IVS[i - 1], ValueInc, "p_vector_iv");
 
-  isl::union_map Schedule = getScheduleForAstNode(isl::manage_copy(For));
+  isl::union_map Schedule = getScheduleForAstNode(For);
   assert(!Schedule.is_null() &&
          "For statement annotation does not contain its schedule");
 
   IDToValue[IteratorID] = ValueLB;
 
   switch (isl_ast_node_get_type(Body)) {
   case isl_ast_node_user:
     createUserVector(Body, IVS, isl_id_copy(IteratorID), Schedule.copy());
void IslNodeBuilder::createForVector(isl::ast_node For, int VectorWidth) {
   default:
     isl_ast_node_dump(Body);
     llvm_unreachable("Unhandled isl_ast_node in vectorizer");
   }
 
   IDToValue.erase(IDToValue.find(IteratorID));
   isl_id_free(IteratorID);
 
-  isl_ast_node_free(For);
   isl_ast_expr_free(Iterator);
 
   VectorLoops++;
 }
 
 /// Restore the initial ordering of dimensions of the band node
 ///
 /// In case the band node represents all the dimensions of the iteration

 
 void IslNodeBuilder::createFor(__isl_take isl_ast_node *For) {
   bool Vector = PollyVectorizerChoice == VECTORIZER_POLLY;
 
   if (Vector && IslAstInfo::isInnermostParallel(isl::manage_copy(For)) &&
       !IslAstInfo::isReductionParallel(isl::manage_copy(For))) {
     int VectorWidth = getNumberOfIterations(isl::manage_copy(For));
     if (1 < VectorWidth && VectorWidth <= 16 && !hasPartialAccesses(For)) {
-      createForVector(For, VectorWidth);
+      createForVector(isl::manage(For), VectorWidth);
       return;
     }
   }
 
   if (IslAstInfo::isExecutedInParallel(isl::manage_copy(For))) {
     createForParallel(For);
     return;
   }