[Target/AArch64] Introduce OptimizeBarriersPass

[davide]

Summary

This is largely modeled after the OptimizeBarriers ARM pass. I hope it sounds reasonable to you two.
Tim, Renato, I noticed this is on also with -O0 on ARM as well, maybe we should disable this if optimization-level == 0? (it can be done in a subsequent commit)

[davide]

Also, this fixes https://llvm.org/bugs/show_bug.cgi?id=23339

[rengolin]

This seems like a plain copy of ARMOptimizeBarriersPass.cpp, minus the comments. I think we ought to avoid copy&paste as much as possible.

We should probably make this into a generic codegen pass.

cheers,
--renato

[davide]

In D9632#171042, @rengolin wrote:

This seems like a plain copy of ARMOptimizeBarriersPass.cpp, minus the comments. I think we ought to avoid copy&paste as much as possible.

We should probably make this into a generic codegen pass.

cheers,
--renato

It makes sense, thanks! I'll go further and propse a new patch for that soon.

Davide

[davide]

Abandon this. After discussion it seems such a better idea to implement this as LLVM IR pass.
For now, r237837 prevents this to be enabled at -O0.

lib/Target/AArch64/AArch64.h

 class AArch64TargetMachine;
 class FunctionPass;
 class MachineFunctionPass;
 
 FunctionPass *createAArch64DeadRegisterDefinitions();
 FunctionPass *createAArch64ConditionalCompares();
 FunctionPass *createAArch64AdvSIMDScalar();
 FunctionPass *createAArch64BranchRelaxation();
+FunctionPass *createAArch64OptimizeBarriersPass();
 FunctionPass *createAArch64ISelDag(AArch64TargetMachine &TM,
                                  CodeGenOpt::Level OptLevel);
 FunctionPass *createAArch64StorePairSuppressPass();
 FunctionPass *createAArch64ExpandPseudoPass();
 FunctionPass *createAArch64LoadStoreOptimizationPass();
 ModulePass *createAArch64PromoteConstantPass();
 FunctionPass *createAArch64ConditionOptimizerPass();
 FunctionPass *createAArch64AddressTypePromotionPass();

lib/Target/AArch64/AArch64OptimizeBarriersPass.cpp

+//===------------- AArch64OptimizeBarriersPass.cpp ------------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//===----------------------------------------------------------------------===//
+
+#include "AArch64.h"
+#include "AArch64InstrInfo.h"
+#include "AArch64MachineFunctionInfo.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+using namespace llvm;
+
+#define DEBUG_TYPE "double barriers"
+
+STATISTIC(NumDMBsRemoved, "Number of DMBs removed");
+
+namespace {
+class AArch64OptimizeBarriersPass : public MachineFunctionPass {
+  public:
+    static char ID;
+    AArch64OptimizeBarriersPass() : MachineFunctionPass(ID) {}
+
+    bool runOnMachineFunction(MachineFunction &Fn) override;
+
+    const char *getPassName() const override {
+      return "optimise barriers pass";
+    }
+  };
+  char AArch64OptimizeBarriersPass::ID = 0;
+}
+
+static bool CanMovePastDMB(const MachineInstr *MI) {
+  return !(MI->mayLoad() || MI->mayStore() ||
+          MI->hasUnmodeledSideEffects() || MI->isCall() ||
+          MI->isReturn());
+}
+
+bool AArch64OptimizeBarriersPass::runOnMachineFunction(MachineFunction &MF) {
+  std::vector<MachineInstr *> ToRemove;
+  int64_t DMBType = -1;
+
+  for (auto &MBB: MF) {
+    bool IsRemovableNextDMB = false;
+    for (auto &MI : MBB) {
+      if (MI.getOpcode() == AArch64::DMB) {
+        if (IsRemovableNextDMB) {
+          if (MI.getOperand(0).getImm() == DMBType) {
+            ToRemove.push_back(&MI);
+          } else
+            DMBType = MI.getOperand(0).getImm();
+        } else {
+          IsRemovableNextDMB = true;
+          DMBType = MI.getOperand(0).getImm();
+        }
+      } else if (!CanMovePastDMB(&MI))
+        IsRemovableNextDMB = false;
+    }
+  }
+
+  for (auto MI : ToRemove) {
+    MI->eraseFromParent();
+    ++NumDMBsRemoved;
+  }
+  return NumDMBsRemoved > 0;
+}
+
+FunctionPass *llvm::createAArch64OptimizeBarriersPass() {
+  return new AArch64OptimizeBarriersPass();
+}

lib/Target/AArch64/AArch64TargetMachine.cpp

void AArch64PassConfig::addPreEmitPass() {
   if (EnableA53Fix835769)
     addPass(createAArch64A53Fix835769());
   // Relax conditional branch instructions if they're otherwise out of
   // range of their destination.
   addPass(createAArch64BranchRelaxation());
   if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
       Triple(TM->getTargetTriple()).isOSBinFormatMachO())
     addPass(createAArch64CollectLOHPass());
+  addPass(createAArch64OptimizeBarriersPass());
 }

lib/Target/AArch64/CMakeLists.txt

add_llvm_target(AArch64CodeGen
   AArch64A53Fix835769.cpp
   AArch64FrameLowering.cpp
   AArch64ConditionOptimizer.cpp
   AArch64ISelDAGToDAG.cpp
   AArch64ISelLowering.cpp
   AArch64InstrInfo.cpp
   AArch64LoadStoreOptimizer.cpp
   AArch64MCInstLower.cpp
+  AArch64OptimizeBarriersPass.cpp
   AArch64PromoteConstant.cpp
   AArch64PBQPRegAlloc.cpp
   AArch64RegisterInfo.cpp
   AArch64SelectionDAGInfo.cpp
   AArch64StorePairSuppress.cpp
   AArch64Subtarget.cpp
   AArch64TargetMachine.cpp
   AArch64TargetObjectFile.cpp

test/CodeGen/AArch64/optimize-dmbs.ll

+; RUN: llc < %s -mtriple arm64-linux-gnueabi -mcpu cortex-a53 | FileCheck %s
+
+define i32 @t1() {
+entry:
+  fence seq_cst
+  fence seq_cst
+  fence seq_cst
+  fence seq_cst
+  ret i32 0
+}
+
+; CHECK: .cfi_startproc
+; CHECK-NEXT: // BB#0: // %entry
+; CHECK-NEXT: dmb     ish
+; CHECK-NEXT: mov      w0, wzr
+; CHECK-NEXT: ret