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[ARM] Try to rematerialize VCTP instructions
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Authored by samparker on Tue, Sep 8, 5:19 AM.

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Summary

We really want to try and avoid spilling P0, which can be difficult since there's only one register, so try to rematerialize any VCTP instructions.

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Event Timeline

samparker created this revision.Tue, Sep 8, 5:19 AM
samparker requested review of this revision.Tue, Sep 8, 5:19 AM
SjoerdMeijer added inline comments.Tue, Sep 8, 5:43 AM
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
6138

Since I don't think this there's much difference in really trivial and trivial, probably isTriviallyReMaterializable is enough to capture this.

llvm/test/CodeGen/Thumb2/LowOverheadLoops/remat-vctp.ll
15

I haven't seen the codegen before this change, so it wasn't immediately clear to me what exactly the clue here is. I.e., is this testing something that isn't tested with the other changed tests? I am guessing the high register pressure?
Perhaps function name arm_vdiv_q31_mve can be made a bit more informative.

samparker updated this revision to Diff 290475.Tue, Sep 8, 6:49 AM

Rebased after pre-committing the test, of which I've changed the function name too. The isTrullyReallyTrivial is a virtual function so I haven't chosen the name for it.

SjoerdMeijer accepted this revision.Tue, Sep 8, 6:58 AM

Rebased after pre-committing the test, of which I've changed the function name too.

Cheers, that's all clear now.

The isTrullyReallyTrivial is a virtual function so I haven't chosen the name for it.

Ah, blimey, I missed that.

LGTM.

This revision is now accepted and ready to land.Tue, Sep 8, 6:58 AM
dmgreen added inline comments.Tue, Sep 8, 6:59 AM
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
6144

This probably wants to check that the VCTP is not predicated.

llvm/test/CodeGen/Thumb2/LowOverheadLoops/remat-vctp.ll
2

A full triple would be better. I think the ".main" is important.

Otherwise, how come it is still not tail predicated?

4

You can remove hidden.

samparker added inline comments.Tue, Sep 8, 7:20 AM
llvm/test/CodeGen/Thumb2/LowOverheadLoops/remat-vctp.ll
2

Cheers, I was just investigating what was going on there!

samparker added inline comments.Tue, Sep 8, 8:01 AM
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
6144

Do you know a nice way to write IR to guarantee a predicated vctp?

dmgreen added inline comments.Tue, Sep 8, 8:08 AM
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
6144

There's an intrinsic for it: https://godbolt.org/z/aPz3s5

This revision was automatically updated to reflect the committed changes.

Thanks both. Addressed comments before committing.