[RISCV] add the MC layer support of riscv vector Zvqmac extension

[StephenFan]

Summary

change the VALUr_IV_V_X to VALUr_IV_X, change the 0b111111 to 0b111111

[HsiangKai]

These instructions and encodings are already removed from vector specification. We could postpone the patch after these instructions are included in the vector specification.

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

988

0b111111

989

VALUr_IV_X

[StephenFan]

change the VALUr_IV_V_X to VALUr_IV_X, change the 0b111111 to 0b111111

[StephenFan]

rebaes to the latest upstream master

llvm/lib/Target/RISCV/RISCV.td

def HasStdExtZvlsseg : Predicate<"Subtarget->hasStdExtZvlsseg()">,
                         "'Zvlsseg' (Vector segment load/store instructions)">;
 def FeatureExtZvamo
     : SubtargetFeature<"experimental-zvamo", "HasStdExtZvamo", "true",
                        "'Zvamo'(Vector AMO Operations)",
                        [FeatureStdExtV]>;
 def HasStdExtZvamo : Predicate<"Subtarget->hasStdExtZvamo()">,
                               AssemblerPredicate<(all_of FeatureExtZvamo),
                               "'Zvamo'(Vector AMO Operations)">;
+def FeatureExtZvqmac
+    : SubtargetFeature<"experimental-zvqmac", "HasStdExtZvqmac", "true",
+                       "'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)",
+                       [FeatureStdExtV]>;
+def HasStdExtZvqmac : Predicate<"Subtarget->hasStdExtZvqmac()">,
+                                AssemblerPredicate<(all_of FeatureExtZvqmac),
+                                "'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)">;
 
 def Feature64Bit
     : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
 def IsRV64 : Predicate<"Subtarget->is64Bit()">,
                        AssemblerPredicate<(all_of Feature64Bit),
                        "RV64I Base Instruction Set">;
 def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
                        AssemblerPredicate<(all_of (not Feature64Bit)),

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

 }
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 } // Predicates = [HasStdExtV]
 
 let Predicates = [HasStdExtZvlsseg] in {
   foreach nf=2-8 in {
     def VLSEG#nf#E8_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth8, "vlseg"#nf#"e8.v">;
     def VLSEG#nf#E16_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth16, "vlseg"#nf#"e16.v">;
     def VLSEG#nf#E32_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth32, "vlseg"#nf#"e32.v">;
     def VLSEG#nf#E64_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth64, "vlseg"#nf#"e64.v">;
     def VLSEG#nf#E128_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth128, "vlseg"#nf#"e128.v">;
     def VLSEG#nf#E256_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth256, "vlseg"#nf#"e256.v">;
     def VLSEG#nf#E512_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth512, "vlseg"#nf#"e512.v">;
     def VLSEG#nf#E1024_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth1024, "vlseg"#nf#"e1024.v">;
 
     def VLSEG#nf#E8FF_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStrideFF, LSWidth8, "vlseg"#nf#"e8ff.v">;
     def VLSEG#nf#E16FF_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStrideFF, LSWidth16, "vlseg"#nf#"e16ff.v">;
     def VLSEG#nf#E32FF_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStrideFF, LSWidth32, "vlseg"#nf#"e32ff.v">;
let Predicates = [HasStdExtZvamo, HasStdExtA, IsRV64] in {
   defm VAMOXOREI64 : VAMO<AMOOPVamoXor, LSWidth64, "vamoxorei64.v">;
   defm VAMOANDEI64 : VAMO<AMOOPVamoAnd, LSWidth64, "vamoandei64.v">;
   defm VAMOOREI64 : VAMO<AMOOPVamoOr, LSWidth64, "vamoorei64.v">;
   defm VAMOMINEI64 : VAMO<AMOOPVamoMin, LSWidth64, "vamominei64.v">;
   defm VAMOMAXEI64 : VAMO<AMOOPVamoMax, LSWidth64, "vamomaxei64.v">;
   defm VAMOMINUEI64 : VAMO<AMOOPVamoMinu, LSWidth64, "vamominuei64.v">;
   defm VAMOMAXUEI64 : VAMO<AMOOPVamoMaxu, LSWidth64, "vamomaxuei64.v">;
 } // Predicates = [HasStdExtZvamo, HasStdExtA, IsRV64]
+
+// Vector Quad-Widening Integer Multiply-Add Instructions (Extension Zvqmac)
+let Predicates = [HasStdExtZvqmac], Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in {
+defm VQMACCU_V : VALUr_IV_V_X<"vqmaccu", 0b111100>;
+defm VQMACC_V : VALUr_IV_V_X<"vqmacc", 0b111101>;
+defm VQMACCSU_V : VALUr_IV_V_X<"vqmaccsu", 0b111111>;
+defm VQMACCUS_V : VALUr_IV_X<"vqmaccus", 0b111110>;
+} // Predicates = [HasStdExtZvqmac], Constraints = "@earlyclobber $vd", RVVConstraint = WidenV
 No newline at end of file

llvm/lib/Target/RISCV/RISCVSchedRocket32.td

 
 // Rocket machine model for scheduling and other instruction cost heuristics.
 def Rocket32Model : SchedMachineModel {
   let MicroOpBufferSize = 0; // Explicitly set to zero since Rocket is in-order.
   let IssueWidth = 1;        // 1 micro-ops are dispatched per cycle.
   let LoadLatency = 3;
   let MispredictPenalty = 3;
   let CompleteModel = 1;
-  let UnsupportedFeatures = [HasStdExtV, HasStdExtZvlsseg, HasStdExtZvamo];
+  let UnsupportedFeatures = [HasStdExtV, HasStdExtZvlsseg, HasStdExtZvamo, HasStdExtZvqmac];
 }
 
 //===----------------------------------------------------------------------===//
 // Define each kind of processor resource and number available.
 
 // Modeling each pipeline as a ProcResource using the BufferSize = 0 since
 // Rocket is in-order.
 

llvm/lib/Target/RISCV/RISCVSchedRocket64.td

 // This works with MachineScheduler. See MCSchedule.h for details.
 
 // Rocket machine model for scheduling and other instruction cost heuristics.
 def Rocket64Model : SchedMachineModel {
   let MicroOpBufferSize = 0; // Explicitly set to zero since Rocket is in-order.
   let IssueWidth = 1;        // 1 micro-ops are dispatched per cycle.
   let LoadLatency = 3;
   let MispredictPenalty = 3;
-  let UnsupportedFeatures = [HasStdExtV, HasStdExtZvlsseg, HasStdExtZvamo];
+  let UnsupportedFeatures = [HasStdExtV, HasStdExtZvlsseg, HasStdExtZvamo, HasStdExtZvqmac];
 }
 
 //===----------------------------------------------------------------------===//
 // Define each kind of processor resource and number available.
 
 // Modeling each pipeline as a ProcResource using the BufferSize = 0 since
 // Rocket is in-order.
 

llvm/lib/Target/RISCV/RISCVSubtarget.h

class RISCVSubtarget : public RISCVGenSubtargetInfo {
   bool HasStdExtZbp = false;
   bool HasStdExtZbr = false;
   bool HasStdExtZbs = false;
   bool HasStdExtZbt = false;
   bool HasStdExtZbproposedc = false;
   bool HasStdExtV = false;
   bool HasStdExtZvlsseg = false;
   bool HasStdExtZvamo = false;
+  bool HasStdExtZvqmac = false;
   bool HasRV64 = false;
   bool IsRV32E = false;
   bool EnableLinkerRelax = false;
   bool EnableRVCHintInstrs = true;
   bool EnableSaveRestore = false;
   unsigned XLen = 32;
   MVT XLenVT = MVT::i32;
   RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
public:
   bool hasStdExtZbp() const { return HasStdExtZbp; }
   bool hasStdExtZbr() const { return HasStdExtZbr; }
   bool hasStdExtZbs() const { return HasStdExtZbs; }
   bool hasStdExtZbt() const { return HasStdExtZbt; }
   bool hasStdExtZbproposedc() const { return HasStdExtZbproposedc; }
   bool hasStdExtV() const { return HasStdExtV; }
   bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; }
   bool hasStdExtZvamo() const { return HasStdExtZvamo; }
+  bool hasStdExtZvqmac() const { return HasStdExtZvqmac; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return IsRV32E; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }
   bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; }
   bool enableSaveRestore() const { return EnableSaveRestore; }
   MVT getXLenVT() const { return XLenVT; }
   unsigned getXLen() const { return XLen; }
   RISCVABI::ABI getTargetABI() const { return TargetABI; }

llvm/test/MC/RISCV/rvv/zvqmac.s

+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-zvqmac %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zvqmac %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-zvqmac - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zvqmac %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vqmaccu.vv v8, v20, v4, v0.t
+# CHECK-INST: vqmaccu.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xf0]
+# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
+# CHECK-UNKNOWN: 57 04 4a f0 <unknown>
+
+vqmaccu.vv v8, v20, v4
+# CHECK-INST: vqmaccu.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xf2]
+# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
+# CHECK-UNKNOWN: 57 04 4a f2 <unknown>
+
+vqmaccu.vx v8, a0, v4, v0.t
+# CHECK-INST: vqmaccu.vx v8, a0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0xf0]
+# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
+# CHECK-UNKNOWN: 57 44 45 f0 <unknown>
+
+vqmaccu.vx v8, a0, v4
+# CHECK-INST: vqmaccu.vx v8, a0, v4
+# CHECK-ENCODING: [0x57,0x44,0x45,0xf2]
+# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
+# CHECK-UNKNOWN: 57 44 45 f2 <unknown>
+
+vqmacc.vv v8, v20, v4, v0.t
+# CHECK-INST: vqmacc.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xf4]
+# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
+# CHECK-UNKNOWN: 57 04 4a f4 <unknown>
+
+vqmacc.vv v8, v20, v4
+# CHECK-INST: vqmacc.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xf6]
+# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
+# CHECK-UNKNOWN: 57 04 4a f6 <unknown>
+
+vqmacc.vx v8, a0, v4, v0.t
+# CHECK-INST: vqmacc.vx v8, a0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0xf4]
+# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
+# CHECK-UNKNOWN: 57 44 45 f4 <unknown>
+
+vqmacc.vx v8, a0, v4
+# CHECK-INST: vqmacc.vx v8, a0, v4
+# CHECK-ENCODING: [0x57,0x44,0x45,0xf6]
+# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
+# CHECK-UNKNOWN: 57 44 45 f6 <unknown>
+
+vqmaccsu.vv v8, v20, v4, v0.t
+# CHECK-INST: vqmaccsu.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xfc]
+# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
+# CHECK-UNKNOWN: 57 04 4a fc <unknown>
+
+vqmaccsu.vv v8, v20, v4
+# CHECK-INST: vqmaccsu.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xfe]
+# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
+# CHECK-UNKNOWN: 57 04 4a fe <unknown>
+
+vqmaccsu.vx v8, a0, v4, v0.t
+# CHECK-INST: vqmaccsu.vx v8, a0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0xfc]
+# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
+# CHECK-UNKNOWN: 57 44 45 fc <unknown>
+
+vqmaccsu.vx v8, a0, v4
+# CHECK-INST: vqmaccsu.vx v8, a0, v4
+# CHECK-ENCODING: [0x57,0x44,0x45,0xfe]
+# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
+# CHECK-UNKNOWN: 57 44 45 fe <unknown>
+
+vqmaccus.vx v8, a0, v4, v0.t
+# CHECK-INST: vqmaccus.vx v8, a0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0xf8]
+# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
+# CHECK-UNKNOWN: 57 44 45 f8 <unknown>
+
+vqmaccus.vx v8, a0, v4
+# CHECK-INST: vqmaccus.vx v8, a0, v4
+# CHECK-ENCODING: [0x57,0x44,0x45,0xfa]
+# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
+# CHECK-UNKNOWN: 57 44 45 fa <unknown>