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[ARM] Fix Asm/Disasm of TBB/TBH instructions
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Authored by DavidSpickett on Jul 21 2020, 3:24 AM.

Details

Summary

This fixes Bugzilla #46616 in which it was reported
that "tbb [pc, r0]" was marked as SoftFail
(aka unpredictable) incorrectly.

Expected behaviour is:

  • ARMv8 is required to use sp as rn or rm (tbb/tbh only have a Thumb encoding so using Arm mode is not an option)
  • If rm is the pc then the instruction is always unpredictable

Some of this was implemented already and this fixes the
rest. Added tests cover the new and pre-existing handling.

Diff Detail

Event Timeline

DavidSpickett created this revision.Jul 21 2020, 3:24 AM
DavidSpickett marked an inline comment as done.
DavidSpickett added inline comments.
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
10601

There is a similar register class "rGPR" but this also removes the PC, which is allowed here. Everything else that had a register like this tells you to use arm mode when you need SP, but tbb/tbh don't have arm encodings.

Seems like it would be a common thing but I couldn't find any other instructions like this.

This revision is now accepted and ready to land.Jul 21 2020, 8:20 AM
This revision was automatically updated to reflect the committed changes.