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[GlobalISel][InlineAsm] Add support for matching input constraints
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Authored by Petar.Avramovic on Jun 26 2020, 5:58 AM.

Details

Summary

Find def operand that corresponds to matching constraint and
tie input to that operand.

Diff Detail

Event Timeline

Herald added a project: Restricted Project. · View Herald TranscriptJun 26 2020, 5:58 AM
arsenm added inline comments.Jun 26 2020, 6:00 AM
llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
235

const reference

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
251

Should use named values in tests

293

Can you add some cases that use different and mixed register classes

Added tests for matching constraints that involve sgpr. Also added one more test file with comparison between 'register class constraint' and 'matching constraint' in final asm output.

arsenm accepted this revision.Jun 29 2020, 7:43 AM
This revision is now accepted and ready to land.Jun 29 2020, 7:43 AM
This revision was automatically updated to reflect the committed changes.
john.brawn reopened this revision.Jul 3 2020, 5:54 AM
john.brawn added a subscriber: john.brawn.

This is causing libcxx test failures in AArch64 -O0. Reduced testcase (the inline asm ultimately comes from DoNotOptimize in libcxx/test/support/test_macros.h):

target triple = "aarch64-none-eabi"
define void @fn() {
entry:
  %ap = alloca i8*, align 8
  %0 = load i8*, i8** %ap, align 8
  call void asm sideeffect "", "=*r|m,0,~{memory}"(i8** %ap, i8* %0)
  ret void
}

llc -O0 results in the assertion failure "Register class not set, wrong accessor" coming from the call to MRI->getRegClass(Def) at line 414.

This revision is now accepted and ready to land.Jul 3 2020, 5:54 AM

I see. I expected that reg class was already determined when previous operand was processed. I will take a look, first operand should have probably asked TargetRegisterInfo for PointerRegClass.

Another AArch64 failure from this (bugpointed from a failure in http://green.lab.llvm.org/green/job/test-suite-verify-machineinstrs-aarch64-O0-g)

Given the following:

define void @main() {
  %1 = call i16 asm sideeffect "", "=r,0"(i16 undef)
  unreachable
}

Compile with:

llc -global-isel -mtriple aarch64-apple-ios -verify-machineinstrs

And you'll get the following error:

# After IRTranslator
# Machine code for function main: IsSSA, TracksLiveness

bb.1 (%ir-block.0):
  %1:_(s16) = G_IMPLICIT_DEF
  %2:gpr32common = COPY %1:_(s16)
  INLINEASM &"" [sideeffect] [attdialect], $0:[regdef:GPR32common], def %0:gpr32common, $1:[reguse tiedto:$0], %2:gpr32common(tied-def 3)
  %4:_(s32) = COPY %0:gpr32common
  %3:_(s16) = G_TRUNC %4:_(s32)

# End machine code for function main.

*** Bad machine code: Copy Instruction is illegal with mismatching sizes ***
- function:    main
- basic block: %bb.1  (0x7fdea2021d40)
- instruction: %2:gpr32common = COPY %1:_(s16)
Def Size = 32, Src Size = 16
LLVM ERROR: Found 1 machine code errors.
miyuki added a subscriber: miyuki.Jul 8 2020, 9:03 AM
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