There is a stall if two different sgpr operands come from the same bank,
unless they form an even-odd pair, in which case they are fetched
together and there is no stall even though they are in the same bank.
analyzeInst tries to count the number of stalls that an instruction
would have if all uses of Reg were replaced with a new register chosen
from Bank, but it can't do this accurately without knowing whether the
new register might form an even-odd pair with any of the other operands.
Because of this the CyclesSaved metric is not always accurate, so there
is no point in trying to verify it.