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[AArch64] Emit warning when disassembling unpredictable LDRAA and LDRAB
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Authored by vhscampos on Jun 25 2020, 4:35 AM.

Details

Summary

LDRAA and LDRAB in their writeback variant should softfail when the same
register is used as result and base.

This patch adds a custom decoder that catches such case and emits a
warning when it occurs.

Diff Detail

Event Timeline

vhscampos created this revision.Jun 25 2020, 4:35 AM
DavidSpickett added inline comments.
llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
1511

This should be 5, 9. I presume the tests pass because they all use x0.

1521

What does this first decode do, is it not enough to Decode it below?

vhscampos marked 2 inline comments as done.Jun 25 2020, 6:58 AM
vhscampos added inline comments.
llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
1511

Are you sure? The third argument is the number of bits to be read.

1521

The writeback variants have an additional operand: the writeback register. Therefore when decoding those variants, it is necessary to perform one additional operand decoding.

DavidSpickett accepted this revision.Jun 25 2020, 7:45 AM

LGTM

llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
1511

Yes you're right, just happened that the numbers lined up.

This revision is now accepted and ready to land.Jun 25 2020, 7:45 AM
This revision was automatically updated to reflect the committed changes.