[LLVM] Add support for armv6k subtarget

[tinti]

Summary

Add support for ARMV6K subtarget variant which is another layer between ARMV6
and ARMV6T2.

ARMV6 family LLVM implementation.

+-------------------------------------+
| ARMV6                               |
+----------------+--------------------+
| ARMV6M (thumb) | ARMV6K (arm,thumb) | <- From ARMV6K and ARMV6M processors
+----------------+--------------------+    have support for hint instructions
| ARMV6T2 (arm,thumb,thumb2)          |    (SEV/WFE/WFI/NOP/YIELD). They can
+-------------------------------------+    be either real or default to NOP.
| ARMV7 (arm,thumb,thumb2)            |    The two processors also use
+-------------------------------------+    different encoding for them.

[rengolin]

Apart from my silly comment, looks good. I'd like Tim to have a look as well, since he has a better eye than I do for these things.

include/llvm/Support/ARMBuildAttributes.h

102

That's actually ARM1176JZ_S, pure ARMv6K is more like MPCore. Ie. keep the comment. :)

[tinti]

In D8126#135991, @rengolin wrote:

Apart from my silly comment, looks good. I'd like Tim to have a look as well, since he has a better eye than I do for these things.

Right. I believe that there is more things to do but I would prefer to make small steps first and fix other things later.

For now this patch fixes arm1176jz-s, arm1176jzf-s and armv6k.

include/llvm/Support/ARMBuildAttributes.h

102

The problem is that we have many subtargets and many processors and it is still fuzzy how to link them:

Processors (ARM11):

• arm1126j (never seen but there is one reference on ARM11 manual)
• arm1136j-s (revision 0)
• arm1136jf-s (revision 0)
• arm1136j-s (revision 1)
• arm1136jf-s (revision 1)
• arm1156t2-s
• arm1156t2f-s
• arm1176jz-s
• arm1176jzf-s
• mpcorenovfp
• mpcore

Subarches:

• v6
• v6j
• v6k
• v6z
• v6kz
• v6t2
• v6core <== guessing a name

My guess of the best map:

• v6 -> arm1126j arm1136j-s (r0) arm1136jf-s (r0)
• v6j -> alias for v6
• v6k -> arm1136j-s (r1) arm1136jf-s (r1); inherits v6; adds HINT
• v6z -> arm1176jz-s arm1176jzf-s; inherits v6k; adds TRUSTZONE
• v6kz -> alias for v6z
• v6t2 -> arm1156t2-s arm1156t2f-s; inherits v6k; adds THUMB2
• v6core -> mpcorenovfp mpcore; inherits v6k; adds MULTICORE

This does not reflect this patch because:

• I'm ignoring that a arm1136 revisions can be v6k. Hence I'm being really strict in keeping the old behavior of LLVM that is to not allow HINT on this arm1136.
• There is no support for MULTICORE and TRUSTZONE on the backend or I am afraid to use them and break things. Therefore I am merging mpcore and arm1176 as one being.

What do you think? For now I will do as you suggested but would be great to organize this later.

[rengolin]

include/llvm/Support/ARMBuildAttributes.h

102

v6core is actually v6k. Multi-core and trust-zone are irrelevant for the compiler, that's why we ignore. But we still have to recognize the arch name and associate with the right CPU (and vice-versa).

[tinti]

Add back comments for v6KZ and fix minor typo.

[t.p.northover]

I think it looks fine too, as long as one test is made a bit stricter.

Tim.

test/MC/ARM/arm11-hint-instr.s

4–6

Probably best to put actual FileCheck tests in here (with the ARM encoding). It's very easy to accidentally make a Thumb encoding available on ARM (or vice-versa) with a slightly dodgy InstAlias.

I don't think you have, but for future changes...

[tinti]

Check enconding as requested by Tim.

[t.p.northover]

test/MC/ARM/arm11-hint-instr.s

49–50

I think this is a bit misleading. A v6T2 CPU ought to assemble the instructions in both ARM and Thumb mode. It's your triple that forces it to use in ARM mode, not an intrinsic property of the processor.

I'd suggest merging CHECK-V6K and CHECK-V6T2 into CHECK-ARM. V6M is always special (possibly with a capital 'S'), it's fine as is.

[tinti]

Improve tests on ARM11:

• Merge v6k and v6t2 tests as suggested by Tim into a single CHECK-ARM.
• Add CHECK-THUMB for v6t2 by using thumb triple.
• Remove miss comment on using default encoding.
• Keep a separate check only for v6m since it is very special.

[tinti]

I have also reordered the instructions based on the encoding for readability.

[rengolin]

Thanks Vinicius, r232468.

include/llvm/ADT/Triple.h

     ARMSubArch_v7s,
     ARMSubArch_v6,
     ARMSubArch_v6m,
+    ARMSubArch_v6k,
     ARMSubArch_v6t2,
     ARMSubArch_v5,
     ARMSubArch_v5te,

include/llvm/Support/ARMBuildAttributes.h

   v5TEJ    = 5,   // e.g. ARM926EJ_S
   v6       = 6,   // e.g. ARM1136J_S
   v6KZ     = 7,   // e.g. ARM1176JZ_S
-  v6T2     = 8,   // e.g. ARM1156T2F_S
-  v6K      = 9,   // e.g. ARM1136J_S
+  v6T2     = 8,   // e.g. ARM1156T2_S
+  v6K      = 9,   // e.g. ARM1176JZ_S
   v7       = 10,  // e.g. Cortex A8, Cortex M3
   v6_M     = 11,  // e.g. Cortex M1
   v6S_M    = 12,  // v6_M with the System extensions

lib/Support/Triple.cpp

     .EndsWith("v6", Triple::ARMSubArch_v6)
     .EndsWith("v6m", Triple::ARMSubArch_v6m)
     .EndsWith("v6sm", Triple::ARMSubArch_v6m)
+    .EndsWith("v6k", Triple::ARMSubArch_v6k)
     .EndsWith("v6t2", Triple::ARMSubArch_v6t2)
     .EndsWith("v5", Triple::ARMSubArch_v5)
     .EndsWith("v5e", Triple::ARMSubArch_v5)

       .Cases("v5", "v5t", "arm10tdmi")
       .Cases("v5e", "v5te", "arm1022e")
       .Case("v5tej", "arm926ej-s")
-      .Cases("v6", "v6k", "arm1136jf-s")
+      .Case("v6", "arm1136jf-s")
       .Case("v6j", "arm1136j-s")
-      .Cases("v6z", "v6zk", "arm1176jzf-s")
+      .Cases("v6k", "v6z", "v6zk", "arm1176jzf-s")
       .Case("v6t2", "arm1156t2-s")
       .Cases("v6m", "v6-m", "v6sm", "v6s-m", "cortex-m0")
       .Cases("v7", "v7a", "v7-a", "v7l", "v7-l", "cortex-a8")

lib/Target/ARM/ARM.td

 def HasV6MOps   : SubtargetFeature<"v6m", "HasV6MOps", "true",
                                    "Support ARM v6M instructions",
                                    [HasV6Ops]>;
+def HasV6KOps   : SubtargetFeature<"v6k", "HasV6KOps", "true",
+                                   "Support ARM v6k instructions",
+                                   [HasV6Ops]>;
 def HasV6T2Ops  : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
                                    "Support ARM v6t2 instructions",
-                                   [HasV6MOps, FeatureThumb2]>;
+                                   [HasV6MOps, HasV6KOps, FeatureThumb2]>;
 def HasV7Ops    : SubtargetFeature<"v7", "HasV7Ops", "true",
                                    "Support ARM v7 instructions",
                                    [HasV6T2Ops, FeaturePerfMon]>;

 def : Processor<"arm1136j-s",       ARMV6Itineraries, [HasV6Ops]>;
 def : Processor<"arm1136jf-s",      ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
                                                        FeatureHasSlowFPVMLx]>;
-def : Processor<"arm1176jz-s",      ARMV6Itineraries, [HasV6Ops]>;
-def : Processor<"arm1176jzf-s",     ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
-                                                       FeatureHasSlowFPVMLx]>;
-def : Processor<"mpcorenovfp",      ARMV6Itineraries, [HasV6Ops]>;
-def : Processor<"mpcore",           ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
-                                                       FeatureHasSlowFPVMLx]>;
 
 // V6M Processors.
 def : Processor<"cortex-m0",        ARMV6Itineraries, [HasV6MOps, FeatureNoARM,

 def : Processor<"sc000",            ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
                                                        FeatureDB, FeatureMClass]>;
 
+// V6K Processors.
+def : Processor<"arm1176jz-s",      ARMV6Itineraries, [HasV6KOps]>;
+def : Processor<"arm1176jzf-s",     ARMV6Itineraries, [HasV6KOps, FeatureVFP2,
+                                                       FeatureHasSlowFPVMLx]>;
+def : Processor<"mpcorenovfp",      ARMV6Itineraries, [HasV6KOps]>;
+def : Processor<"mpcore",           ARMV6Itineraries, [HasV6KOps, FeatureVFP2,
+                                                       FeatureHasSlowFPVMLx]>;
+
 // V6T2 Processors.
 def : Processor<"arm1156t2-s",      ARMV6Itineraries, [HasV6T2Ops,
                                                        FeatureDSPThumb2]>;

lib/Target/ARM/ARMBaseInstrInfo.cpp

 }
 
 bool ARMBaseInstrInfo::hasNOP() const {
-  return (Subtarget.getFeatureBits() & ARM::HasV6T2Ops) != 0;
+  return (Subtarget.getFeatureBits() & ARM::HasV6KOps) != 0;
 }
 
 bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {

lib/Target/ARM/ARMInstrInfo.td

 def HasV6T2          : Predicate<"Subtarget->hasV6T2Ops()">,
                                  AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
 def NoV6T2           : Predicate<"!Subtarget->hasV6T2Ops()">;
+def HasV6K           : Predicate<"Subtarget->hasV6KOps()">,
+                                 AssemblerPredicate<"HasV6KOps", "armv6k">;
+def NoV6K            : Predicate<"!Subtarget->hasV6KOps()">;
 def HasV7            : Predicate<"Subtarget->hasV7Ops()">,
                                  AssemblerPredicate<"HasV7Ops", "armv7">;
 def HasV8            : Predicate<"Subtarget->hasV8Ops()">,

   let Inst{7-0} = imm;
 }
 
-def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6T2]>;
-def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6T2]>;
-def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>;
-def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>;
-def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>;
+def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6K]>;
+def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6K]>;
+def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6K]>;
+def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>;
+def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>;
 def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
 
 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",

lib/Target/ARM/ARMSubtarget.h

   ARMProcClassEnum ARMProcClass;
 
   /// HasV4TOps, HasV5TOps, HasV5TEOps,
-  /// HasV6Ops, HasV6MOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
+  /// HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
   /// Specify whether target support specific ARM ISA variants.
   bool HasV4TOps;
   bool HasV5TOps;
   bool HasV5TEOps;
   bool HasV6Ops;
   bool HasV6MOps;
+  bool HasV6KOps;
   bool HasV6T2Ops;
   bool HasV7Ops;
   bool HasV8Ops;

   bool hasV5TEOps() const { return HasV5TEOps; }
   bool hasV6Ops()   const { return HasV6Ops;   }
   bool hasV6MOps()  const { return HasV6MOps;  }
+  bool hasV6KOps()  const { return HasV6KOps; }
   bool hasV6T2Ops() const { return HasV6T2Ops; }
   bool hasV7Ops()   const { return HasV7Ops;  }
   bool hasV8Ops()   const { return HasV8Ops;  }

lib/Target/ARM/ARMSubtarget.cpp

   HasV5TEOps = false;
   HasV6Ops = false;
   HasV6MOps = false;
+  HasV6KOps = false;
   HasV6T2Ops = false;
   HasV7Ops = false;
   HasV8Ops = false;

lib/Target/ARM/MCTargetDesc/ARMArchName.def

 ARM_ARCH_NAME("armv5te", ARMV5TE, "5TE",     v5TE)
 ARM_ARCH_NAME("armv6",   ARMV6,   "6",       v6)
 ARM_ARCH_NAME("armv6j",  ARMV6J,  "6J",      v6)
+ARM_ARCH_NAME("armv6k",  ARMV6K,  "6K",      v6K)
 ARM_ARCH_NAME("armv6t2", ARMV6T2, "6T2",     v6T2)
 ARM_ARCH_NAME("armv6z",  ARMV6Z,  "6Z",      v6KZ)
 ARM_ARCH_NAME("armv6zk", ARMV6ZK, "6ZK",     v6KZ)

lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp

     setAttributeItem(THUMB_ISA_use, AllowThumb32, false);
     break;
 
+  case ARM::ARMV6K:
   case ARM::ARMV6Z:
   case ARM::ARMV6ZK:
     setAttributeItem(ARM_ISA_use, Allowed, false);

lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

   case Triple::ARMSubArch_v6t2:
     ARMArchFeature = "+v6t2";
     break;
+  case Triple::ARMSubArch_v6k:
+    ARMArchFeature = "+v6k";
+    break;
   case Triple::ARMSubArch_v6m:
     isThumb = true;
     if (NoCPU)

test/CodeGen/ARM/build-attributes.ll

 ; RUN: llc < %s -mtriple=armv6-none-linux-gnueabi -mcpu=arm1136j-s | FileCheck %s --check-prefix=STRICT-ALIGN
 ; RUN: llc < %s -mtriple=armv6-none-linux-gnueabi -mcpu=arm1136j-s -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN
 ; RUN: llc < %s -mtriple=armv6-none-linux-gnueabi -mcpu=arm1136j-s -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
+; ARMv6k
+; RUN: llc < %s -mtriple=armv6k-none-netbsd-gnueabi -mcpu=arm1176j-s | FileCheck %s --check-prefix=NO-STRICT-ALIGN
+; RUN: llc < %s -mtriple=armv6k-none-linux-gnueabi -mcpu=arm1176j-s | FileCheck %s --check-prefix=STRICT-ALIGN
+; RUN: llc < %s -mtriple=armv6k-none-linux-gnueabi -mcpu=arm1176j-s -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN
+; RUN: llc < %s -mtriple=armv6k-none-linux-gnueabi -mcpu=arm1176j-s -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
 ; ARMv6m
 ; RUN: llc < %s -mtriple=thumb-none-linux-gnueabi -arm-no-strict-align -mcpu=cortex-m0 | FileCheck %s --check-prefix=STRICT-ALIGN
 ; RUN: llc < %s -mtriple=thumb-none-linux-gnueabi -arm-strict-align -mcpu=cortex-m0 | FileCheck %s --check-prefix=STRICT-ALIGN

test/MC/ARM/arm11-hint-instr.s

+@ RUN: not llvm-mc -triple=armv6 -show-encoding < %s > %t1 2> %t2
+@ RUN: FileCheck --check-prefix=CHECK-V6 %s < %t1
+@ RUN: FileCheck --check-prefix=CHECK-ERROR-V6 %s < %t2
+@ RUN: llvm-mc -triple=armv6k -show-encoding < %s \
+@ RUN:     | FileCheck --check-prefix=CHECK-ARM %s
+@ RUN: llvm-mc -triple=armv6t2 -show-encoding < %s \
+@ RUN:     | FileCheck --check-prefix=CHECK-ARM %s
+@ RUN: llvm-mc -triple=thumb -mcpu=arm1156t2-s -show-encoding < %s \
+@ RUN:     | FileCheck --check-prefix=CHECK-THUMB %s
+@ RUN: llvm-mc -triple=armv6m -show-encoding < %s \
+@ RUN:     | FileCheck --check-prefix=CHECK-V6M %s
+
+  .syntax unified
+
+@------------------------------------------------------------------------------
+@ YIELD/WFE/WFI/SEV - are not supported pre v6K
+@------------------------------------------------------------------------------
+        nop
+        yield
+        wfe
+        wfi
+        sev
+
+
+@------------------------------------------------------------------------------
+@ v6 using ARM encoding
+@------------------------------------------------------------------------------
+@ CHECK-V6: mov  r0, r0                  @ encoding: [0x00,0x00,0xa0,0xe1]
+@ CHECK-ERROR-V6: error: instruction requires: armv6k
+@ CHECK-ERROR-V6: yield
+@ CHECK-ERROR-V6: ^
+@ CHECK-ERROR-V6: error: instruction requires: armv6k
+@ CHECK-ERROR-V6: wfe
+@ CHECK-ERROR-V6: ^
+@ CHECK-ERROR-V6: error: instruction requires: armv6k
+@ CHECK-ERROR-V6: wfi
+@ CHECK-ERROR-V6: error: instruction requires: armv6k
+@ CHECK-ERROR-V6: sev
+@ CHECK-ERROR-V6: ^
+
+@------------------------------------------------------------------------------
+@ v6K using ARM encoding
+@------------------------------------------------------------------------------
+@------------------------------------------------------------------------------
+@ v6T2 using ARM encoding (arm triple)
+@------------------------------------------------------------------------------
+@ CHECK-ARM: nop                             @ encoding: [0x00,0xf0,0x20,0xe3]
+@ CHECK-ARM: yield                           @ encoding: [0x01,0xf0,0x20,0xe3]
+@ CHECK-ARM: wfe                             @ encoding: [0x02,0xf0,0x20,0xe3]
+@ CHECK-ARM: wfi                             @ encoding: [0x03,0xf0,0x20,0xe3]
+@ CHECK-ARM: sev                             @ encoding: [0x04,0xf0,0x20,0xe3]
+
+@------------------------------------------------------------------------------
+@ v6T2 using THUMB encoding (thumb triple)
+@------------------------------------------------------------------------------
+@ CHECK-THUMB: nop                             @ encoding: [0x00,0xbf]
+@ CHECK-THUMB: yield                           @ encoding: [0x10,0xbf]
+@ CHECK-THUMB: wfe                             @ encoding: [0x20,0xbf]
+@ CHECK-THUMB: wfi                             @ encoding: [0x30,0xbf]
+@ CHECK-THUMB: sev                             @ encoding: [0x40,0xbf]
+
+@------------------------------------------------------------------------------
+@ v6M using THUMB encoding
+@------------------------------------------------------------------------------
+@ CHECK-V6M: nop                             @ encoding: [0x00,0xbf]
+@ CHECK-V6M: yield                           @ encoding: [0x10,0xbf]
+@ CHECK-V6M: wfe                             @ encoding: [0x20,0xbf]
+@ CHECK-V6M: wfi                             @ encoding: [0x30,0xbf]
+@ CHECK-V6M: sev                             @ encoding: [0x40,0xbf]

test/MC/ARM/directive-arch-armv6k.s

+@ Test the .arch directive for armv6k
+
+@ This test case will check the default .ARM.attributes value for the
+@ armv6k architecture.
+
+@ RUN: llvm-mc -triple arm-eabi -filetype asm %s \
+@ RUN:   | FileCheck %s -check-prefix CHECK-ASM
+@ RUN: llvm-mc -triple arm-eabi -filetype obj %s \
+@ RUN:   | llvm-readobj -arm-attributes | FileCheck %s -check-prefix CHECK-ATTR
+
+  .syntax unified
+  .arch armv6k
+
+@ CHECK-ASM:  .arch armv6k
+
+@ CHECK-ATTR: FileAttributes {
+@ CHECK-ATTR:   Attribute {
+@ CHECK-ATTR:     TagName: CPU_name
+@ CHECK-ATTR:     Value: 6K
+@ CHECK-ATTR:   }
+@ CHECK-ATTR:   Attribute {
+@ CHECK-ATTR:     TagName: CPU_arch
+@ CHECK-ATTR:     Description: ARM v6K
+@ CHECK-ATTR:   }
+@ CHECK-ATTR:   Attribute {
+@ CHECK-ATTR:     TagName: ARM_ISA_use
+@ CHECK-ATTR:     Description: Permitted
+@ CHECK-ATTR:   }
+@ CHECK-ATTR:   Attribute {
+@ CHECK-ATTR:     TagName: THUMB_ISA_use
+@ CHECK-ATTR:     Description: Thumb-1
+@ CHECK-ATTR:   }
+@ CHECK-ATTR: }
+

test/MC/ARM/thumb-diagnostics.s

 @ CHECK-ERRORS: error: branch target out of range
 
 @------------------------------------------------------------------------------
-@ WFE/WFI/YIELD - are not supported pre v6T2
+@ SEV/WFE/WFI/YIELD - are not supported pre v6M or v6T2
 @------------------------------------------------------------------------------
+        sev
         wfe
         wfi
         yield
 
 @ CHECK-ERRORS: error: instruction requires: armv6m or armv6t2
+@ CHECK-ERRORS: sev
+@ CHECK-ERRORS: ^
+@ CHECK-ERRORS: error: instruction requires: armv6m or armv6t2
 @ CHECK-ERRORS: wfe
 @ CHECK-ERRORS: ^
 @ CHECK-ERRORS: error: instruction requires: armv6m or armv6t2