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[NFC?][SCEV][LoopVectorize] Add datalayout to the X86/float-induction-x86.ll test
ClosedPublic

Authored by lebedev.ri on Jan 30 2020, 8:37 AM.

Details

Summary

Currently, SCEVExpander::isHighCostExpansionHelper() has the following logic:

if (auto *UDivExpr = dyn_cast<SCEVUDivExpr>(S)) {
  // If the divisor is a power of two and the SCEV type fits in a native
  // integer (and the LHS not expensive), consider the division cheap
  // irrespective of whether it occurs in the user code since it can be
  // lowered into a right shift.
  if (auto *SC = dyn_cast<SCEVConstant>(UDivExpr->getRHS()))
    if (SC->getAPInt().isPowerOf2()) {
      if (isHighCostExpansionHelper(UDivExpr->getLHS(), L, At,
                                    BudgetRemaining, TTI, Processed))
        return true;
      const DataLayout &DL =
          L->getHeader()->getParent()->getParent()->getDataLayout();
      unsigned Width = cast<IntegerType>(UDivExpr->getType())->getBitWidth();
      return DL.isIllegalInteger(Width);
    }

Since this test does not have a datalayout specified,
SCEVExpander::isHighCostExpansionHelper() says that
[[TMP2:%.*]] = lshr exact i64 [[TMP1]], 5 is high-cost, and didn't perform it.

But future patches will change that logic to solely rely on cost-model,
without any such datalayout checks, so i think it is best to show
that that change is ephemeral, and can already happen without costmodel changes.

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