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[AArch64] Add lowering pattern for llvm.aarch64.neon.vcvtfxs2fp.f16.i64
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Authored by dnsampaio on Apr 4 2019, 4:11 AM.

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pbarrio
DavidSpickett
LukeGeeson

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rG8ddfd46c61ab: [AArch64] Add lowering pattern for llvm.aarch64.neon.vcvtfxs2fp.f16.i64
rL358171: [AArch64] Add lowering pattern for llvm.aarch64.neon.vcvtfxs2fp.f16.i64

Summary

Add lowering pattern for llvm.aarch64.neon.vcvtfxs2fp.f16.i64

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Repository: rL LLVM

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dnsampaio created this revision.Apr 4 2019, 4:11 AM

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dnsampaio added a parent revision: D60212: [AArch64] Add lowering pattern for scalar fp16 facge and facgt.Apr 4 2019, 4:11 AM

Would it be possible to see the surrounding tests for fp16_intrinic_scalar_2op? It'd be good to double check formatting

In D60259#1454767, @LukeGeeson wrote:

Would it be possible to see the surrounding tests for fp16_intrinic_scalar_2op? It'd be good to double check formatting

Did not understand you question, the diff file is with full context.

Oops my bad, can see it now

Ping

LGTM

This revision is now accepted and ready to land.Apr 11 2019, 3:40 AM

Closed by commit rL358171: [AArch64] Add lowering pattern for llvm.aarch64.neon.vcvtfxs2fp.f16.i64 (authored by dnsampaio). · Explain WhyApr 11 2019, 7:19 AM

This revision was automatically updated to reflect the committed changes.

Revision Contents

Path

Size

llvm/

trunk/

lib/

Target/

AArch64/

AArch64InstrInfo.td

2 lines

test/

CodeGen/

AArch64/

fp16_intrinsic_scalar_2op.ll

10 lines

Diff 194678

llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td

This file is larger than 256 KB, so syntax highlighting is disabled by default.

Show First 20 Lines • Show All 5,321 Lines • ▼ Show 20 Lines	def : Pat<(int_aarch64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),
(SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;		(SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;

// Patterns for FP16 Instrinsics - requires reg copy to/from as i16s not supported.		// Patterns for FP16 Instrinsics - requires reg copy to/from as i16s not supported.

def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i32 (sext_inreg FPR32:$Rn, i16)), vecshiftR16:$imm)),		def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i32 (sext_inreg FPR32:$Rn, i16)), vecshiftR16:$imm)),
(SCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>;		(SCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>;
def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i32 FPR32:$Rn), vecshiftR16:$imm)),		def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i32 FPR32:$Rn), vecshiftR16:$imm)),
(SCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>;		(SCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>;
		def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR16:$imm)),
		(SCVTFh (EXTRACT_SUBREG FPR64:$Rn, hsub), vecshiftR16:$imm)>;
def : Pat<(f16 (int_aarch64_neon_vcvtfxu2fp		def : Pat<(f16 (int_aarch64_neon_vcvtfxu2fp
(and FPR32:$Rn, (i32 65535)),		(and FPR32:$Rn, (i32 65535)),
vecshiftR16:$imm)),		vecshiftR16:$imm)),
(UCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>;		(UCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>;
def : Pat<(f16 (int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR16:$imm)),		def : Pat<(f16 (int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR16:$imm)),
(UCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>;		(UCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>;
def : Pat<(f16 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR16:$imm)),		def : Pat<(f16 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR16:$imm)),
(UCVTFh (EXTRACT_SUBREG FPR64:$Rn, hsub), vecshiftR16:$imm)>;		(UCVTFh (EXTRACT_SUBREG FPR64:$Rn, hsub), vecshiftR16:$imm)>;
▲ Show 20 Lines • Show All 1,494 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.ll

	Show First 20 Lines • Show All 336 Lines • ▼ Show 20 Lines
	; CHECK: facgt h0, h0, h1			; CHECK: facgt h0, h0, h1
	; CHECK-NEXT: fmov w0, s0			; CHECK-NEXT: fmov w0, s0
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%facg = tail call i32 @llvm.aarch64.neon.facgt.i32.f16(half %a, half %b)			%facg = tail call i32 @llvm.aarch64.neon.facgt.i32.f16(half %a, half %b)
	%0 = trunc i32 %facg to i16			%0 = trunc i32 %facg to i16
	ret i16 %0			ret i16 %0
	}			}

				define dso_local half @vcvth_n_f16_s64_test(i64 %a) {
				; CHECK-LABEL: vcvth_n_f16_s64_test:
				; CHECK: fmov d0, x0
				; CHECK-NEXT: scvtf h0, h0, #16
				; CHECK-NEXT: ret
				entry:
				%vcvth_n_f16_s64 = tail call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i64(i64 %a, i32 16)
				ret half %vcvth_n_f16_s64
				}