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pbarrio (Pablo Barrio)
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User Since
Jan 15 2015, 3:04 AM (301 w, 2 h)

Recent Activity

Jun 5 2020

pbarrio accepted D81257: [AArch64] Allow BTI mnemonics in the HINT space with BTI disabled.
Jun 5 2020, 8:55 AM · Restricted Project
pbarrio added a comment to D81257: [AArch64] Allow BTI mnemonics in the HINT space with BTI disabled.

This is the same logic that we applied to PAC mnemonics in https://reviews.llvm.org/D78372. I'll approve but I would recommend to wait for a few days in case anyone else has something to say.

Jun 5 2020, 8:55 AM · Restricted Project

Apr 24 2020

pbarrio committed rGd4e7b000b2eb: [AArch64] Allow PAC mnemonics in the HINT space with PAC disabled (authored by pbarrio).
[AArch64] Allow PAC mnemonics in the HINT space with PAC disabled
Apr 24 2020, 9:11 AM
pbarrio closed D78372: [AArch64] Allow PAC mnemonics in the HINT space with PAC disabled.
Apr 24 2020, 9:11 AM · Restricted Project

Apr 21 2020

pbarrio updated the diff for D78372: [AArch64] Allow PAC mnemonics in the HINT space with PAC disabled.

Another rebase to pass C.I. - looks like it was broken outside this commit

Apr 21 2020, 10:47 AM · Restricted Project
pbarrio updated the diff for D78372: [AArch64] Allow PAC mnemonics in the HINT space with PAC disabled.

Rebase to trigger C.I.

Apr 21 2020, 3:46 AM · Restricted Project

Apr 17 2020

pbarrio created D78372: [AArch64] Allow PAC mnemonics in the HINT space with PAC disabled.
Apr 17 2020, 8:05 AM · Restricted Project

Mar 5 2020

pbarrio committed rGe440e0a71572: Fix MemTagSanitizer docs to point at Armv8.5-A MTE (authored by pbarrio).
Fix MemTagSanitizer docs to point at Armv8.5-A MTE
Mar 5 2020, 9:52 AM

Jan 22 2020

pbarrio committed rGa8ff6c0b0971: [AArch64] Add test for DWARF return address signing (authored by pbarrio).
[AArch64] Add test for DWARF return address signing
Jan 22 2020, 8:41 AM
pbarrio closed D72835: [AArch64] Add test for DWARF return address signing.
Jan 22 2020, 8:41 AM · Restricted Project
pbarrio added a reviewer for D72835: [AArch64] Add test for DWARF return address signing: keith.walker.arm.
Jan 22 2020, 3:49 AM · Restricted Project

Jan 16 2020

pbarrio created D72835: [AArch64] Add test for DWARF return address signing.
Jan 16 2020, 4:36 AM · Restricted Project

Jan 13 2020

pbarrio committed rGda33762de853: [AArch64] Emit HINT instead of PAC insns in Armv8.2-A or below (authored by pbarrio).
[AArch64] Emit HINT instead of PAC insns in Armv8.2-A or below
Jan 13 2020, 6:17 AM
pbarrio closed D71658: [AArch64] Emit HINT instead of PAC insns in Armv8.2-A or below.
Jan 13 2020, 6:16 AM · Restricted Project
pbarrio updated the diff for D71658: [AArch64] Emit HINT instead of PAC insns in Armv8.2-A or below.

Updated tests and rebase conflict with new "isAuthenticated" predicate

Jan 13 2020, 4:06 AM · Restricted Project

Jan 2 2020

pbarrio added a comment to D71658: [AArch64] Emit HINT instead of PAC insns in Armv8.2-A or below.

Ping

Jan 2 2020, 2:16 AM · Restricted Project

Dec 18 2019

pbarrio created D71658: [AArch64] Emit HINT instead of PAC insns in Armv8.2-A or below.
Dec 18 2019, 5:30 AM · Restricted Project

Sep 30 2019

pbarrio committed rGffac4e860329: Fix doc for t inline asm constraints for ARM/Thumb (authored by pbarrio).
Fix doc for t inline asm constraints for ARM/Thumb
Sep 30 2019, 9:54 AM

Sep 27 2019

pbarrio updated the diff for D68090: Fix doc for t inline asm constraints for ARM/Thumb.

Reworded all the FP & SIMD constraints

Sep 27 2019, 10:47 AM · Restricted Project
pbarrio added a comment to D68090: Fix doc for t inline asm constraints for ARM/Thumb.

Discussing with @chill on a chat, he was happier with the following wording:

Sep 27 2019, 3:15 AM · Restricted Project
pbarrio added a reviewer for D68090: Fix doc for t inline asm constraints for ARM/Thumb: chill.
Sep 27 2019, 3:13 AM · Restricted Project

Sep 26 2019

pbarrio created D68090: Fix doc for t inline asm constraints for ARM/Thumb.
Sep 26 2019, 9:21 AM · Restricted Project

Sep 23 2019

pbarrio accepted D67840: Cosmetic; don't use the magic constant 35 when HASH is more readable. This matches other MCK__<THING>_* usage better..
Sep 23 2019, 2:57 AM · Restricted Project

Sep 18 2019

pbarrio added a comment to D62394: [ARM][CMSE] Add CMSE header & builtins.

Hi, CMSE upstreaming is indeed one of our priorities. So yes, we are very interested in your feedback. And no, CMSE upstreaming is not abandoned, just going a bit slow ATM :( but any help reviewing is much appreciated! :)

Sep 18 2019, 8:54 AM

Aug 9 2019

pbarrio committed rG3cdd586be28f: [AArch64] Set pref. func. align to 8 bytes on Neoverse E1 & Cortex-A65 (authored by pbarrio).
[AArch64] Set pref. func. align to 8 bytes on Neoverse E1 & Cortex-A65
Aug 9 2019, 4:05 AM

Aug 8 2019

pbarrio created D65937: [AArch64] Set pref. func. align to 8 bytes on Neoverse E1 & Cortex-A65.
Aug 8 2019, 4:00 AM · Restricted Project

Aug 5 2019

pbarrio committed rGa8426b43f8b9: [AArch64] Set preferred function alignment to 16 bytes on Neoverse N1 (authored by pbarrio).
[AArch64] Set preferred function alignment to 16 bytes on Neoverse N1
Aug 5 2019, 10:39 AM

Aug 2 2019

pbarrio added inline comments to D65654: [AArch64] Set preferred function alignment to 16 bytes on Neoverse N1.
Aug 2 2019, 8:30 AM · Restricted Project
pbarrio created D65654: [AArch64] Set preferred function alignment to 16 bytes on Neoverse N1.
Aug 2 2019, 6:26 AM · Restricted Project

Jul 25 2019

pbarrio committed rG275954539d1e: [ARM][AArch64] Support for Cortex-A65 & A65AE, Neoverse E1 & N1 (authored by pbarrio).
[ARM][AArch64] Support for Cortex-A65 & A65AE, Neoverse E1 & N1
Jul 25 2019, 4:03 AM

Jul 19 2019

pbarrio updated the diff for D64406: [ARM][AArch64] Cortex-A65AE, Neoverse E1 and Neoverse N1 support.

Oooops sorry, not sure how I missed that. I've added SSBS to all the CPUs now.

Jul 19 2019, 9:32 AM · Restricted Project

Jul 18 2019

pbarrio updated the diff for D64406: [ARM][AArch64] Cortex-A65AE, Neoverse E1 and Neoverse N1 support.

Add Cortex-A65 and a few features that were missed in the first patch. I think all the features should be in now.

Jul 18 2019, 2:41 AM · Restricted Project

Jul 11 2019

pbarrio added a comment to D63707: [AArch64] Define ETE and TRBE system registers.

These are trace extensions that will be used by a niche group of developers. They add no instructions (only system registers) and they will not be generated by the compiler. Adding them by default does not have any side-effect, i.e. everyone will still see the same behavior in their code unless they start using these registers on purpose.

Jul 11 2019, 6:26 AM · Restricted Project

Jul 9 2019

pbarrio created D64406: [ARM][AArch64] Cortex-A65AE, Neoverse E1 and Neoverse N1 support.
Jul 9 2019, 5:33 AM · Restricted Project

Jan 25 2019

pbarrio accepted D57060: [NFC][Clang] Add driver tests for sb and predres.

Same idea as https://reviews.llvm.org/D54961 but for two other command line options. Approved!

Jan 25 2019, 2:37 AM

Dec 3 2018

pbarrio updated the diff for D54629: [AArch64] Add command-line option for SSBS.

Rebased onto master after a recent refactoring of the AArch64 target parser.

Dec 3 2018, 5:58 AM

Nov 27 2018

pbarrio added a comment to D54629: [AArch64] Add command-line option for SSBS.

Thank you for the review, Sam :)

Nov 27 2018, 11:09 AM
pbarrio created D54961: [AArch64] Add command-line option for SSBS.
Nov 27 2018, 11:06 AM

Nov 19 2018

pbarrio added a comment to D54629: [AArch64] Add command-line option for SSBS.

The Armv8.5-A specification is available here: https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools

Nov 19 2018, 4:22 AM

Nov 16 2018

pbarrio created D54629: [AArch64] Add command-line option for SSBS.
Nov 16 2018, 5:20 AM

Mar 1 2018

pbarrio added a comment to D42574: [ARM] Lower lower saturate to 0 and lower saturate to -1 using bit-operations.

Buildbot failing here: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap-msan/builds/2998

Mar 1 2018, 2:59 AM

Feb 28 2018

pbarrio added inline comments to D42574: [ARM] Lower lower saturate to 0 and lower saturate to -1 using bit-operations.
Feb 28 2018, 6:17 AM

Feb 23 2018

pbarrio added a comment to D42574: [ARM] Lower lower saturate to 0 and lower saturate to -1 using bit-operations.

If nobody does it before, I'll give it a try early next week.

Feb 23 2018, 8:34 AM

Feb 15 2018

pbarrio added a comment to D43342: [ARM] Fix redirect in inline assembly test.

I'll commit this fix now to prevent other buildbots to fail.

Feb 15 2018, 11:14 AM
pbarrio added a comment to D42962: [ARM] Allow 64- and 128-bit types with 't' inline asm constraint.

Related fix for a silly errata in one of the tests that is breaking some Windows buildbots:

Feb 15 2018, 11:11 AM
pbarrio added a reviewer for D43342: [ARM] Fix redirect in inline assembly test: apilipenko.
Feb 15 2018, 10:23 AM
pbarrio created D43342: [ARM] Fix redirect in inline assembly test.
Feb 15 2018, 10:18 AM
pbarrio added a comment to D42962: [ARM] Allow 64- and 128-bit types with 't' inline asm constraint.

Committed now. @rengolin many thanks for the review!

Feb 15 2018, 6:49 AM
pbarrio added a comment to D42962: [ARM] Allow 64- and 128-bit types with 't' inline asm constraint.

What about 32-bit integers?

Feb 15 2018, 1:54 AM

Feb 13 2018

pbarrio added a comment to D42962: [ARM] Allow 64- and 128-bit types with 't' inline asm constraint.

There is still the possibility that someone tries to use 't' for a vector of two doubles. Only single-precision is allowed in vector operations for 32-bit architectures, so doing something like this would be illegal:

Feb 13 2018, 7:08 AM
pbarrio updated the diff for D42962: [ARM] Allow 64- and 128-bit types with 't' inline asm constraint.

Added tests for int vectors. Allowing integers to go to FP/vector registers is
useful because FP/int conversion instructions (i.e. VCVT) need that.

Feb 13 2018, 6:51 AM

Feb 12 2018

pbarrio added a comment to D42962: [ARM] Allow 64- and 128-bit types with 't' inline asm constraint.

AFAICS, the current approach just checks the size of the type, not the size of the sub-type. f64 or even integer types could still leak in, no?

To prove they're not, we need tests making sure they break if you try.

Feb 12 2018, 10:45 AM
pbarrio added a comment to D42962: [ARM] Allow 64- and 128-bit types with 't' inline asm constraint.

I was wrong when I said the GNU modifiers are q/e, which actually makes things easier. The correct operand modifiers to select a quad/double vector register in GCC are q/P. These already work in LLVM (they are just ignored according to the documentation and also my local testing). So, I think there is no need for an additional patch; we should be able to handle inline assembly written for GCC with the 't' constraint.

I'm not sure I get this. Are you saying this patch can be abandoned?

Feb 12 2018, 10:25 AM
pbarrio added a comment to D42962: [ARM] Allow 64- and 128-bit types with 't' inline asm constraint.

This goes against the documentation, which only supports sN:
https://gcc.gnu.org/onlinedocs/gcc/Machine-Constraints.html#Machine-Constraints

Though it's not completely wrong to support the low part of D/Q registers, I'm not sure the code in question is making sure this is true.

Feb 12 2018, 10:18 AM
pbarrio added a comment to D42962: [ARM] Allow 64- and 128-bit types with 't' inline asm constraint.

This behaviour still differs from that of GCC but I think it is actually more correct, since LLVM picks up the right register type based on the datatype of x, while GCC would need an extra operand modifier to achieve the same result

If we're not going to match gcc, what's the point?

This patch allows specifying the lower Q/D vector registers from inline assembly, which is something that can be done in GCC but not in LLVM. In order to mimic the GCC behaviour completely, we should also add support for the q/e/f operand modifiers with the 't' constraint. These modifiers are already allowed with the 'w' constraint for the complete vector register set, so it shouldn't be hard to do. However, I think it should be a separate patch with additional testing.

Feb 12 2018, 9:59 AM
pbarrio added a comment to D42962: [ARM] Allow 64- and 128-bit types with 't' inline asm constraint.

Ping

Feb 12 2018, 7:28 AM

Feb 7 2018

pbarrio added inline comments to D42962: [ARM] Allow 64- and 128-bit types with 't' inline asm constraint.
Feb 7 2018, 6:46 AM
pbarrio added a comment to D42962: [ARM] Allow 64- and 128-bit types with 't' inline asm constraint.

This behaviour still differs from that of GCC but I think it is actually more correct, since LLVM picks up the right register type based on the datatype of x, while GCC would need an extra operand modifier to achieve the same result

If we're not going to match gcc, what's the point?

Feb 7 2018, 3:23 AM

Feb 6 2018

pbarrio created D42962: [ARM] Allow 64- and 128-bit types with 't' inline asm constraint.
Feb 6 2018, 6:46 AM

Feb 1 2018

pbarrio added a comment to D42574: [ARM] Lower lower saturate to 0 and lower saturate to -1 using bit-operations.

Sorry, I missed the sanitizer failure in yesterday's buildbot message and thought it wasn't related to this patch. I will leave some time for @thebolt to fix it, otherwise maybe I can take a look.

Feb 1 2018, 2:55 AM

Jan 31 2018

pbarrio added a comment to D42574: [ARM] Lower lower saturate to 0 and lower saturate to -1 using bit-operations.

Committed now. Thanks for the patch @thebolt!

Jan 31 2018, 5:25 AM
pbarrio added a comment to D42574: [ARM] Lower lower saturate to 0 and lower saturate to -1 using bit-operations.

I'll do it.

Jan 31 2018, 3:37 AM

Jan 29 2018

pbarrio accepted D42574: [ARM] Lower lower saturate to 0 and lower saturate to -1 using bit-operations.

LGTM now. In other circumstances, I would wait for someone more experienced than me, but this is a small peephole optimization. I've also tested the patch and it works correctly, so I think it has very little risk.

Jan 29 2018, 5:07 AM

Jan 26 2018

pbarrio requested changes to D42574: [ARM] Lower lower saturate to 0 and lower saturate to -1 using bit-operations.

The logic & testing LGTM. Just a couple of coding standard nits.

Jan 26 2018, 12:41 PM

Jan 23 2018

pbarrio added a comment to D42235: [AArch64] Avoid unnecessary vector byte-swapping in big-endian.

Waiting a bit just in case there's extra feedback for the last change. I will commit this patch later today.

Jan 23 2018, 6:31 AM

Jan 22 2018

pbarrio updated the diff for D42235: [AArch64] Avoid unnecessary vector byte-swapping in big-endian.

VT should be a vector in addTypeForNEON, so the check can be an assert
instead of a proper test in the conditional.

Jan 22 2018, 11:44 AM
pbarrio added a comment to D42235: [AArch64] Avoid unnecessary vector byte-swapping in big-endian.

Thanks for the suggestion, very helpful :)

Jan 22 2018, 4:07 AM
pbarrio updated the diff for D42235: [AArch64] Avoid unnecessary vector byte-swapping in big-endian.

Instead of an ugly switch, reuse already-existing functionality in LLVM to do
the conversion of FP vector types into int vector types.

Jan 22 2018, 4:06 AM

Jan 18 2018

pbarrio created D42235: [AArch64] Avoid unnecessary vector byte-swapping in big-endian.
Jan 18 2018, 2:33 AM

Jan 17 2018

pbarrio added inline comments to D41863: [AArch64] Fix incorrect LD1 of 16-bit FP vectors in big endian.
Jan 17 2018, 5:14 AM
pbarrio updated the diff for D41863: [AArch64] Fix incorrect LD1 of 16-bit FP vectors in big endian.

Fixed big-endian bitconvert patterns and extensive testing for half-float vectors.

Jan 17 2018, 4:49 AM

Jan 16 2018

pbarrio updated the diff for D41863: [AArch64] Fix incorrect LD1 of 16-bit FP vectors in big endian.

I have fixed the bug as olista01 suggested, which is more straightforward than
my previous fix.

Jan 16 2018, 7:07 AM

Jan 15 2018

pbarrio added a comment to D41863: [AArch64] Fix incorrect LD1 of 16-bit FP vectors in big endian.

Hi Sjoerd, thanks for the review. I have attached some thoughts on your comments and I will upload a new patch soon.

Jan 15 2018, 10:57 AM

Jan 9 2018

pbarrio created D41863: [AArch64] Fix incorrect LD1 of 16-bit FP vectors in big endian.
Jan 9 2018, 7:25 AM

Dec 4 2017

pbarrio added a comment to D40706: Fix function pointer tail calls in armv8-M.base.

@efriedma , @olista01 , thank you for the reviews. I will commit upstream now.

Dec 4 2017, 5:13 AM

Dec 1 2017

pbarrio added a comment to D40706: Fix function pointer tail calls in armv8-M.base.

I have also updated the existing tests and added a couple more.

Dec 1 2017, 10:08 AM
pbarrio updated the diff for D40706: Fix function pointer tail calls in armv8-M.base.

Use !isa<GlobalAddressSDNode> to check if the call is through a function pointer

Dec 1 2017, 10:06 AM
pbarrio created D40706: Fix function pointer tail calls in armv8-M.base.
Dec 1 2017, 2:34 AM

Nov 17 2016

pbarrio added a comment to D26748: [ARM] Relax restriction on variadic functions for tailcall optimization.

Thanks all for the reviews!

Nov 17 2016, 3:05 AM
pbarrio updated the diff for D26748: [ARM] Relax restriction on variadic functions for tailcall optimization.

Cleaned up tests as per Renato's comments.

Nov 17 2016, 2:59 AM

Nov 16 2016

pbarrio updated the diff for D26748: [ARM] Relax restriction on variadic functions for tailcall optimization.

More testing: add tests for AAPCS and for floating-point arguments to variadic/non-variadic functions.

Nov 16 2016, 12:06 PM
pbarrio added a comment to D26748: [ARM] Relax restriction on variadic functions for tailcall optimization.

Could you have a look at this patch? I see no reason to restrict the tail call optimizations to variadic functions: the AAPCS restrictions seem to be already checked for non-variadic functions. The LLVM regression tests passed, and I have also tested with a few benchmarks and they all seem to work fine.

Nov 16 2016, 7:20 AM
pbarrio retitled D26748: [ARM] Relax restriction on variadic functions for tailcall optimization from to [ARM] Relax restriction on variadic functions for tailcall optimization.
Nov 16 2016, 7:14 AM

Nov 11 2016

pbarrio updated the diff for D26450: [JumpThreading] Prevent non-deterministic use lists.

Traverse use list instead of user list to naturally avoid duplicates. Commit message modified accordingly.

Nov 11 2016, 6:07 AM
pbarrio added a comment to D26450: [JumpThreading] Prevent non-deterministic use lists.

Sorry, forget what I said. I didn't get what you were trying to do at first (I've never used the "uses"). I will do the change, as this makes more clear that the operand we are interested in is the condition (i.e. operand 0).

Nov 11 2016, 1:54 AM

Nov 10 2016

pbarrio added a comment to D26450: [JumpThreading] Prevent non-deterministic use lists.

I have investigated the -preserve-ll-uselistorder option. It sets option "ShouldPreserveUseListOrder" to true in the module printer. According to the documentation:

Nov 10 2016, 5:55 AM

Nov 9 2016

pbarrio added a comment to D26450: [JumpThreading] Prevent non-deterministic use lists.

Could you have a look at this fix as per your comments in D26391?

Nov 9 2016, 6:42 AM
pbarrio retitled D26450: [JumpThreading] Prevent non-deterministic use lists from to [JumpThreading] Prevent non-deterministic use lists.
Nov 9 2016, 6:38 AM
pbarrio added a comment to D26391: [JumpThreading] Unfold selects that depend on the same condition.

Thanks for the comment @efriedma. I committed before I saw it, but I agree with you that this change will affect determinism of the use-lists when two of the selects on the list depend on each other. I will create a separate revision for the change and add you as reviewer.

Nov 9 2016, 3:30 AM

Nov 8 2016

pbarrio added a comment to D26391: [JumpThreading] Unfold selects that depend on the same condition.

@sebpop , thanks for the quick response!

Nov 8 2016, 6:57 AM
pbarrio added a comment to D26391: [JumpThreading] Unfold selects that depend on the same condition.

Could you review this patch to JumpThreading? This is an update to D25477, which was reverted two weeks ago as it was breaking LNT and some bootstrap buildbots.

Nov 8 2016, 5:00 AM
pbarrio retitled D26391: [JumpThreading] Unfold selects that depend on the same condition from to [JumpThreading] Unfold selects that depend on the same condition.
Nov 8 2016, 4:46 AM

Oct 21 2016

pbarrio updated the diff for D25477: [JumpThreading] Unfold selects that depend on the same condition.

Thanks all for the reviews. Could you please review the requested formatting changes and approve if appropriate?

Oct 21 2016, 8:31 AM

Oct 17 2016

pbarrio added a comment to D25477: [JumpThreading] Unfold selects that depend on the same condition.

James, thanks for the review and also for adding the new reviewers. I will change the lower/upper case problem with the next round of comments, when I get feedback from others.

Oct 17 2016, 8:53 AM

Oct 11 2016

pbarrio retitled D25477: [JumpThreading] Unfold selects that depend on the same condition from to [JumpThreading] Unfold selects that depend on the same condition.
Oct 11 2016, 8:33 AM

Sep 13 2016

pbarrio added a comment to D24337: Fix the Thumb test for vfloat intrinsics.

Renato, James, thank you very much for the review.

Sep 13 2016, 2:43 AM

Sep 12 2016

pbarrio updated the diff for D24337: Fix the Thumb test for vfloat intrinsics.

Removed vector float intrinsic test from this review. That
part of the patch has now been committed and the review can
be followed in https://reviews.llvm.org/D24398

Sep 12 2016, 8:13 AM

Sep 9 2016

pbarrio added a comment to D24337: Fix the Thumb test for vfloat intrinsics.

On second thoughts, I have tested with a modern gcc and it marks all functions with either .thumb or .arm (equivalent to .code 16/32). So, essentially, that behaviour is what this patch suggests. Another thing that surprised me is that Thumb appears to be the default, contrary to the LLVM default which is ARM.

Sep 9 2016, 8:18 AM
pbarrio added a comment to D24398: Fix the Thumb test for vfloat intrinsics.

Hello James,

Sep 9 2016, 8:08 AM
pbarrio retitled D24398: Fix the Thumb test for vfloat intrinsics from to Fix the Thumb test for vfloat intrinsics.
Sep 9 2016, 8:05 AM